CN102193868B - Data stack storage circuit and microcontroller - Google Patents
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- CN102193868B CN102193868B CN 201010123197 CN201010123197A CN102193868B CN 102193868 B CN102193868 B CN 102193868B CN 201010123197 CN201010123197 CN 201010123197 CN 201010123197 A CN201010123197 A CN 201010123197A CN 102193868 B CN102193868 B CN 102193868B
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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Abstract
The invention provides a data stack storage circuit and a microcontroller. The data stack storage circuit comprises a data stack storage and a data stack control circuit which are connected with each other, wherein the data stack storage is connected to a data bus; and the data stack control circuit is connected to a control bus and is used for pushing data prepared for stack in the data bus into the stack top of the data stack storage according to a push operating signal in the control bus or ejecting data prepared for stack from the stack top of the data stack storage into the data bus according to a pop operating signal in the control bus. By adopting the data stack storage circuit and the microcontroller, the aim of completing push and pop operation through a command is fulfilled, and the execution efficiencies of push and pop operations on a data stack are increased.
Description
Technical field
The present invention relates to field of computer technology, relate in particular to a kind of data stack memory circuit and microcontroller.
Background technology
Pushing on and going out stack operation as a kind of data processing method of storehouse is widely adopted in microcontroller.Storehouse mainly comprises program stack and data stack, wherein, and in the microcontroller that program stack almost should be all, when main program redirect or interruption are processed, to preservation and the recovery of present procedure address.Because the microcontroller need data processing amount to be processed of early stage comparatively low side is relatively less, and application structure is relatively simple, therefore seldom relates to data stack.But along with the widespread use of microcontroller, and the lifting of application system complexity, make the complexity of data processing amount and application structure increase, a large amount of function variable of frequent Save and restore is wanted in the particularly use of higher level lanquage development environment; In this case; can realize easily protection and the recovery of mass data due to data stack, therefore, increasing microcontroller begins the application data storehouse; simultaneously data stack manipulation mode is also being updated, carried out efficient to promote a large amount of function variable of Save and restore.
Fig. 4 is the stack architecture schematic diagram of the low and middle-end microcontroller of prior art.As shown in Figure 4, in the prior art, for the low and middle-end microcontroller, seldom adopt the data stack of hardware configuration, and mainly with conventional data storer in sheet as hardware foundation, and the operation of the mode simulated data storehouse by software.Particularly, with the storer in a sector address space of conventional data storer as data stack; With certain conventional data storer or register as stack pointer, the address of the current stack top of storage, and all to push on going out stack operation be all to complete by common memory transfer exclusive disjunction instruction.In the low side microcontroller, need take the partial data space of conventional data storer due to data stack in these, the relative independentability of protected data and these other data of conventional data storer in very difficult this data stack of assurance.Particularly; when calling other data of this conventional data storer carrying out relative program; content in very possible meeting maloperation data stack; thereby cause the data of protecting in data stack to be rewritten, there is the poor shortcoming of data security in the low side micro controller frame form that therefore has above-mentioned data stack.
Fig. 5 is the stack architecture schematic diagram in the middle and high end microcontroller of prior art.As shown in Figure 5, for the middle and high end microcontroller, data stack that adopt hardware configurations are data stack storer independently more.Particularly, read or write the included data stack of control register by setting and read or write control bit, operate reading or writing temporary data or the data of reading of popping of preparing to push on of buffer register; As stack pointer, the address of the current stack top of storage is to push on or to go out stack operation by specific hardware register.In these in the relevant framework of the data stack of high-end microcontroller, because need operate the data storehouse indirectly by reading or writing control register and reading or writing buffer register, push on that to carry out efficient not high with going out stack operation and make.
Summary of the invention
The invention provides a kind of data stack memory circuit and microcontroller, in order to solving in existing microcontroller because need operate the data storehouse indirectly by reading or writing control register and reading or writing buffer register, push on and go out stack operation and carry out the not high defective of efficient and make.
The invention provides a kind of data stack memory circuit, wherein, comprise data stack storer and data stack control circuit; Described data stack storer is connected with the data stack control circuit;
Described data stack storer is connected in data bus;
Described data stack control circuit is connected in control bus;
And the data stack control circuit is used for the push operation signal according to described control bus, the data that have been ready to pop down in described data bus are pressed into the stack top of described data stack storer, perhaps be used for the operation signal of popping according to described control bus, the data that are ready to the to play stack stack top from described data stack storer is ejected to described data bus.
The invention provides a kind of microcontroller, comprise controller, wherein, also comprise the data stack memory circuit;
Described controller is connected in control bus, and described controller is used for by analyzing the operational code of push instruction, to generate the first control signal set and to be sent to described control bus; Perhaps, be used for by analyzing the operational code of stack instruction, to generate the second control signal set and to be sent to described control bus;
Described data stack memory circuit comprises data stack storer and data stack control circuit; Described data stack storer is connected with the data stack control circuit; Described data stack storer is connected in data bus; Described data stack control circuit is connected in described control bus;
And the data stack control circuit is used for the push operation signal according to described the first control signal set, the data that have been ready to pop down in described data bus are pressed into the stack top of described data stack storer, perhaps be used for the operation signal of popping according to described the second control signal set, the data that are ready to the to play stack stack top from described data stack storer is ejected to described data bus.
data stack memory circuit of the present invention and microcontroller, by the included data stack control circuit of data stack memory circuit according to the push operation signal in control bus, the data that have been ready to pop down in data bus are pressed into the stack top of data stack storer, perhaps according to the operation signal of popping in institute's control bus, the data that are ready to play stack are ejected technical scheme to the data bus from the stack top of data stack storer, solved in existing microcontroller because need operate the data storehouse indirectly by reading or writing control register and reading or writing buffer register, push on and go out stack operation and carry out the not high defective of efficient and make, having realized pushing on and having gone out stack operation is achievable purpose by corresponding dependent instruction separately, saved the chip frame form that reads or writes control register and read or write the buffer register complexity, and improved the data storehouse has been pushed on and the execution efficient that goes out stack operation.
Description of drawings
Fig. 1 is the structural representation of data stack memory circuit of the present invention;
Fig. 2 is the structural representation of microcontroller embodiment one of the present invention;
Fig. 3 is the structural representation of microcontroller embodiment two of the present invention;
Fig. 4 is the stack architecture schematic diagram of the low and middle-end microcontroller of prior art;
Fig. 5 is the stack architecture schematic diagram of the middle and high end microcontroller of prior art.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with the accompanying drawing in the present invention, technical scheme of the present invention is described.
Fig. 1 is the structural representation of data stack memory circuit of the present invention.As shown in Figure 1, the data stack memory circuit of the present embodiment comprises data stack storer 101 and data stack control circuit 102, this data stack storer 101 is connected with data stack control circuit 102, wherein, data stack storer 101 is connected in data bus, data stack control circuit 102 is connected in control bus, and data stack control circuit 102 comprises push on control circuit module 1021 and the control circuit module 1022 of popping.Wherein, data stack storer 101 is that special use comes store data, rather than deposits the program address; And data stack storer and programmed protection stack, general-purpose data register heap are separate; operation to data stacked memory 101 need be undertaken by push instruction (can be designated the PUSH instruction in program language) and pull instruction (can be designated the POP instruction in program language), and can not data stacked memory 101 be operated with the common read-write operation of controller.
In the process of push operation, the control circuit module 1021 that pushes in data stack control circuit 102 is according to the push operation signal in control bus, the data that have been ready to pop down in data bus are pressed into the stack top of data stack storer 101, wherein have been ready to the data of required protection in data that the data of pop down can obtain for addressing IO mouth, interrupt operation or the data that address data memory obtains;
In going out the process of stack operation, the control circuit module 1022 of popping in data stack control circuit 102 is according to the operation signal of popping in control bus, and the data that are ready to the to play stack stack top from data stack storer 101 is ejected to data bus.
In actual applications, data stack storer 101 can be an independently storer, it is perhaps an independently part storage space of storer, be perhaps at least two independently combinations of storer, being perhaps at least one independently storer and at least one independently combination of the part storage space of storer, is perhaps at least two independently combinations of part storage space in storer.
Further, the data stack memory circuit of the present embodiment also comprises hardware stack pointer 103, this hardware stack pointer 103 is connected in control bus and data stack storer 101, and hardware stack pointer 103 can add 1 signal according to the hardware stack pointer in described control bus and add voluntarily 1 after the control circuit module 1021 that pushes on has been ready to pop down in data bus according to the push operation signal in control bus data are pressed into the stack top of data stack storer 101; The data that perhaps will be ready to play stack according to the operation signal of popping in control bus in the control circuit module 1022 of popping eject to data bus from the stack top of data stack storer 101, can subtract 1 signal according to the hardware stack pointer in described control bus and subtract voluntarily 1.
Again further, the data stack memory circuit of the present embodiment also comprises overflow indicator register 104, and this overflow indicator register 104 is connected in hardware stack pointer 103, and this overflow indicator register 104 comprises overflow flag position 1041 and underflow flag position 1042; In the push operation process, by comparator circuit, current hardware stack pointer 103 and higher limit are compared to monitor the state of hardware stack pointer 103, add 1 and during the rebound lowest address from location superlatively when this hardware stack pointer 103, overflow flag position 1041 puts 1 automatically, and this higher limit is the superlatively location of data stack storer 101; In the operating process of popping, by comparator circuit, current hardware stack pointer 103 and lower limit are compared to monitor the state of hardware stack pointer 103, when this hardware stack pointer 103 subtracts 1 and rebound superlatively during the location from lowest address, underflow flag position 1042 puts 1 automatically, and this lower limit is the lowest address of data stack storer 101.
the data stack memory circuit of the present embodiment, by the data stack control circuit according to the push operation signal in control bus, the data that have been ready to pop down in data bus are pressed into the stack top of data stack storer, perhaps according to the operation signal of popping in institute's control bus, the data that are ready to play stack are ejected technical scheme to the data bus from the stack top of data stack storer, solved in existing microcontroller because need operate the data storehouse indirectly by reading or writing control register and reading or writing buffer register, push on and go out stack operation and carry out the not high defective of efficient and make, having realized pushing on and having gone out stack operation is achievable purpose by corresponding dependent instruction separately, saved the chip frame form that reads or writes control register and read or write the buffer register complexity, and improved the data storehouse has been pushed on and the execution efficient that goes out stack operation.
Fig. 2 is the structural representation of microcontroller embodiment one of the present invention.As shown in Figure 2, the microcontroller of the present embodiment comprises controller 201 and data stack memory circuit 202, and wherein, this controller 201 is connected in control bus, and controller 201 comprises program storage, order register, command decoder and control logic circuit; Data stack memory circuit 202 comprises data stack storer 101 and data stack control circuit 102, this data stack storer 101 is connected with data stack control circuit 102, and data stack storer 101 is connected in data bus, data stack control circuit 102 is connected in control bus, and data stack control circuit 102 comprises push on control circuit module 1021 and the control circuit module 1022 of popping.Wherein, data stack storer 101 is that special use comes store data, rather than deposits the program address; And data stack storer and programmed protection stack, general-purpose data register heap are separate; operation to data stacked memory 101 need be undertaken by push instruction (can be designated the PUSH instruction in program language) and pull instruction (can be designated the POP instruction in program language), and can not data stacked memory 101 be operated with the common read-write operation of controller 201.
Further, data stack memory circuit 202 also comprises hardware stack pointer 103 and this overflow indicator register 104, wherein hardware stack pointer 103 is connected in control bus and data stack storer 101, this overflow indicator register 104 is connected in hardware stack pointer 103, and overflow indicator register 104 comprises overflow flag position 1041 and underflow flag position 1042;
In the push operation process, the push instruction that the order register of controller 201 reads from program storage (can be designated the PUSH instruction program language), then by command decoder, the included operational code of push instruction in order register is carried out decoding to generate the first control signal set, and sending to relevant modular circuit to reach the purpose of control by control logic circuit by control bus, this first control signal set comprises that at least push operation signal and hardware stack pointer add 1 signal; The control circuit module 1021 that pushes in data stack control circuit 102 is according to this push operation signal, the data that have been ready to pop down in data bus are pressed into the stack top of data stack storer 101, wherein have been ready to the data of required protection in data that the data of pop down can obtain for addressing IO mouth, interrupt operation or the data that address data memory obtains; And, hardware stack pointer 103 is after the control circuit module 1021 that pushes on has been ready to pop down in data bus according to the push operation signal data are pressed into the stack top of data stack storer 101, can add 1 signal according to the hardware stack pointer in described control bus and add voluntarily 1, and point to new stack top; Add 1 action for hardware stack pointer 103 at every turn, all by comparator circuit, current hardware stack pointer 103 and higher limit are compared to monitor the state of hardware stack pointer 103, add 1 and during the rebound lowest address from location superlatively when this hardware stack pointer 103, overflow flag position 1041 puts 1 automatically, and this higher limit is the superlatively location of data stack storer 101.
In the operating process of popping, the pull instruction that the order register of controller 201 reads from program storage (can be designated the POP instruction program language), then by command decoder, the included operational code of pull instruction in order register is carried out decoding to generate the second control signal set, and sending to relevant modular circuit reaching the purpose of control by control logic circuit by control bus, this second control signal set comprises that at least pop operation signal and hardware stack pointer subtract 1 signal; The control circuit module 1022 of popping in data stack control circuit 102 is according to this operation signal of popping, the data that are ready to the to play stack stack top from data stack storer 101 is ejected to data bus, and can control the interlock circuit module by the control signal in the second control signal set and receive this and eject data to data bus; And, hardware stack pointer 103 will be ready to play stack according to the operation signal of popping in the control circuit module 1022 of popping data eject to data bus from the stack top of data stack storer 101, can subtract 1 signal according to the hardware stack pointer in control bus and subtract voluntarily 1, and point to new stack top; Subtract 1 action for hardware stack pointer 103 at every turn, all by comparator circuit, current hardware stack pointer 103 and lower limit are compared to monitor the state of hardware stack pointer 103, when this hardware stack pointer 103 subtracts 1 and rebound superlatively during the location from lowest address, underflow flag position 1042 puts 1 automatically, and this lower limit is the lowest address of data stack storer 101.
In actual applications, data stack storer 101 can be an independently storer, it is perhaps an independently part storage space of storer, be perhaps at least two independently combinations of storer, being perhaps at least one independently storer and at least one independently combination of the part storage space of storer, is perhaps at least two independently combinations of part storage space in storer.
the microcontroller of the present embodiment, by the included data stack control circuit of data stack memory circuit according to the push operation signal in control bus, the data that have been ready to pop down in data bus are pressed into the stack top of data stack storer, perhaps according to the operation signal of popping in institute's control bus, the data that are ready to play stack are ejected technical scheme to the data bus from the stack top of data stack storer, solved in existing microcontroller because need operate the data storehouse indirectly by reading or writing control register and reading or writing buffer register, push on and go out stack operation and carry out the not high defective of efficient and make, having realized pushing on and having gone out stack operation is achievable purpose by corresponding dependent instruction separately, saved the chip frame form that reads or writes control register and read or write the buffer register complexity, and improved the data storehouse has been pushed on and the execution efficient that goes out stack operation.
Fig. 3 is the structural representation of microcontroller embodiment two of the present invention.In conjunction with Fig. 2 and shown in Figure 3, the microcontroller of the present embodiment also comprises address selector 203 and data-carrier store 204 on the basis of above-described embodiment, and wherein, address selector 203 is connected in controller 201, address bus and control bus; Data-carrier store 204 is connected in control bus, data bus and address bus;
Mainly describe in the present embodiment the data of address data memory 204, and these data are pressed into the push operation process of data stack storer 101; And the data that eject in data stack storer 101 are described, be saved to the operating process of popping in data-carrier store 204; Particularly,
in the push operation process, the push instruction that the order register of controller 201 reads from program storage (can be designated the PUSH instruction program language), then by command decoder, the included operational code of push instruction in order register is carried out decoding to generate the first control signal set, and send to relevant modular circuit to reach the purpose of control by control logic circuit by control bus, this the first control signal set comprises the push operation signal, the hardware stack pointer adds 1 signal, the first address decoding operation signal and read data memory signals, and the command decoder of controller 201 first operand that push instruction is included sends to address selector 203, address selector 203 is according to the first address decoding operation signal, and the first operand that controller 201 is sent carries out decoding, to generate the first data memory addresses and to be sent on address bus, data-carrier store 204 will be prepared on the data data writing bus of pop down according to read data memory signals and the first data memory addresses, and the control circuit module 1021 that pushes in data stack control circuit 102 is according to the push operation signal, the data that have been ready to pop down in data bus are pressed into the stack top of data stack storer 101, the data that wherein have been ready to pop down are the data that addressing IO mouth obtains, 103, hardware stack pointer is after the control circuit module 1021 that pushes on has been ready to pop down in data bus according to the push operation signal data are pressed into the stack top of data stack storer 101, can add 1 signal according to the hardware stack pointer in described control bus and add voluntarily 1, and point to new stack top, add 1 action for hardware stack pointer 103 at every turn, all by comparator circuit, current hardware stack pointer 103 and higher limit are compared to monitor the state of hardware stack pointer 103, add 1 and during the rebound lowest address from location superlatively when this hardware stack pointer 103, overflow flag position 1041 puts 1 automatically, and this higher limit is the superlatively location of data stack storer 101.
in the operating process of popping, the pull instruction that the order register of controller 201 reads from program storage (can be designated the POP instruction program language), then by command decoder, the included operational code of pull instruction in order register is carried out decoding to generate the second control signal set, and send to relevant modular circuit to reach the purpose of control by control logic circuit by control bus, this the second control signal set comprises the operation signal of popping, the hardware stack pointer subtracts 1 signal, the second address decoding operation signal and write the data-carrier store signal, and the command decoder of controller 201 second operand that push instruction is included sends to address selector 203, the control circuit module 1022 of popping in data stack control circuit 102 is according to this operation signal of popping, and the data that are ready to the to play stack stack top from data stack storer 101 is ejected to data bus, address selector 203 carries out decoding according to the second address decoding operation signal to the second operand that controller 201 sends, to generate the second data memory addresses and to be sent on address bus, data-carrier store 204 reads according to writing data-carrier store signal and the second data memory addresses the data that eject stack from data bus, 103, hardware stack pointer will be ready to play stack according to the operation signal of popping in the control circuit module 1022 of popping data eject to data bus from the stack top of data stack storer 101, can subtract 1 signal according to the hardware stack pointer and subtract voluntarily 1, and point to new stack top, subtract 1 action for hardware stack pointer 103 at every turn, all by comparator circuit, current hardware stack pointer 103 and lower limit are compared to monitor the state of hardware stack pointer 103, when this hardware stack pointer 103 subtracts 1 and rebound superlatively during the location from lowest address, underflow flag position 1042 puts 1 automatically, and this lower limit is the lowest address of data stack storer 101.
the microcontroller of the present embodiment, by the included data stack control circuit of data stack memory circuit according to the push operation signal in control bus, the data that have been ready to pop down in data bus are pressed into the stack top of data stack storer, perhaps according to the operation signal of popping in institute's control bus, the data that are ready to play stack are ejected technical scheme to the data bus from the stack top of data stack storer, solved in existing microcontroller because need operate the data storehouse indirectly by reading or writing control register and reading or writing buffer register, push on and go out stack operation and carry out the not high defective of efficient and make, having realized pushing on and having gone out stack operation is achievable purpose by corresponding dependent instruction separately, saved the chip frame form that reads or writes control register and read or write the buffer register complexity, and improved the data storehouse has been pushed on and the execution efficient that goes out stack operation.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment, the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (8)
1. a data stack memory circuit, is characterized in that, comprises data stack storer and data stack control circuit; Described data stack storer is connected with the data stack control circuit;
Described data stack storer is connected in data bus, described data stack storer is an independently storer, it is perhaps an independently part storage space of storer, be perhaps at least two independently combinations of storer, being perhaps at least one independently storer and at least one independently combination of the part storage space of storer, is perhaps at least two independently combinations of part storage space in storer;
Described data stack control circuit is connected in control bus, and described data stack control circuit comprises push on control circuit module and the control circuit module of popping;
The described control circuit module that pushes on is used for the push operation signal according to described control bus, the data that have been ready to pop down in described data bus is pressed into the stack top of described data stack storer;
The described control circuit module of popping is used for the operation signal of popping according to described control bus, and the data that are ready to the to play stack stack top from described data stack storer is ejected to described data bus.
2. data stack memory circuit according to claim 1, is characterized in that, also comprises the hardware stack pointer, and described hardware stack pointer is connected in described control bus and described data stack storer;
Described hardware stack pointer adds 1 signal and adds voluntarily 1 according to the hardware stack pointer in described control bus after being pressed into the stack top of described data stack storer for the data that have been ready to pop down at described data bus; Perhaps eject to described data bus in the stack top of the data that are ready to play stack from described data stack storer, subtract 1 signal and subtract voluntarily 1 according to the hardware stack pointer in described control bus.
3. data stack memory circuit according to claim 2, is characterized in that, also comprises the overflow indicator register, and described overflow indicator register is connected in described hardware stack pointer, and described overflow indicator register comprises overflow flag position and underflow flag position.
4. a microcontroller, comprise controller, it is characterized in that, also comprises the data stack memory circuit;
Described controller is connected in control bus, and described controller is used for by analyzing the operational code of push instruction, to generate the first control signal set and to be sent to described control bus; Perhaps, be used for by analyzing the operational code of stack instruction, to generate the second control signal set and to be sent to described control bus;
Described data stack memory circuit comprises data stack storer and data stack control circuit; Described data stack storer is connected with the data stack control circuit;
Described data stack storer is connected in data bus, described data stack storer is an independently storer, it is perhaps an independently part storage space of storer, be perhaps at least two independently combinations of storer, being perhaps at least one independently storer and at least one independently combination of the part storage space of storer, is perhaps at least two independently combinations of part storage space in storer;
Described data stack control circuit is connected in described control bus, and described data stack control circuit comprises push on control circuit module and the control circuit module of popping;
The described control circuit module that pushes on is used for the push operation signal according to described the first control signal set, the data that have been ready to pop down in described data bus is pressed into the stack top of described data stack storer;
The described control circuit module of popping is used for the operation signal of popping according to described the second control signal set, and the data that are ready to the to play stack stack top from described data stack storer is ejected to described data bus.
5. microcontroller according to claim 4, is characterized in that, also comprises address selector, and described address selector is connected in described controller, address bus and described control bus;
Described address selector is used for the first address decoding operation signal according to described the first control signal set, first operand in the push instruction that described controller is sent carries out decoding, to generate the first data memory addresses and to be sent on described address bus;
Perhaps be used for the second address decoding operation signal according to described the second control signal set, the second operand in the pull instruction that described controller is sent is carried out decoding, to generate the second data memory addresses and to be sent on described address bus.
6. microcontroller according to claim 5, is characterized in that, also comprises data-carrier store, and described data-carrier store is connected in described control bus, described data bus and described address bus;
Described data-carrier store is used for read data memory signals and the first data memory addresses according to described the first control signal set, and the data of preparing pop down are write on described data bus;
Perhaps be used for according to described the second control signal set write data-carrier store signal and the second data memory addresses, read in the data that eject stack from described data bus.
7. microcontroller according to claim 4, is characterized in that, also comprises the hardware stack pointer, and described hardware stack pointer is connected in described control bus and described data stack storer;
Described hardware stack pointer adds 1 signal and adds voluntarily 1 according to the hardware stack pointer in described control bus after being pressed into the stack top of described data stack storer for the data that have been ready to pop down at described data bus; Perhaps eject to described data bus in the stack top of the data that are ready to play stack from described data stack storer, subtract 1 signal and subtract voluntarily 1 according to the hardware stack pointer in described control bus.
8. microcontroller according to claim 7, is characterized in that, also comprises the overflow indicator register, and described overflow indicator register is connected in described hardware stack pointer, and described overflow indicator register comprises overflow flag position and underflow flag position.
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| CN 201010123197 CN102193868B (en) | 2010-03-10 | 2010-03-10 | Data stack storage circuit and microcontroller |
| PCT/CN2010/074117 WO2011109970A1 (en) | 2010-03-10 | 2010-06-21 | Data stack memory circuit and microcontroller |
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| WO2011109970A1 (en) | 2011-09-15 |
| CN102193868A (en) | 2011-09-21 |
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