WO2011109970A1

WO2011109970A1 - Data stack memory circuit and microcontroller

Info

Publication number: WO2011109970A1
Application number: PCT/CN2010/074117
Authority: WO
Inventors: 史卫东; 潘松; 岳卫杰
Original assignee: 上海海尔集成电路有限公司
Priority date: 2010-03-10
Filing date: 2010-06-21
Publication date: 2011-09-15
Also published as: CN102193868B; CN102193868A

Abstract

A data stack memory circuit and a microcontroller are provided, the data stack memory circuit comprises a data stack memory and a data stack control circuit; the data stack memory is connected with the data stack control circuit; the data stack memory is connected to a data bus; the data stack control circuit is connected to a control bus; and the data stack control circuit is used to, according to a push operation signal in the control bus, push the data prepared to be pushed in the data bus into the top of the data stack memory, or is used to, according to a pop operation signal in the control bus, pop the data prepared to be popped from the top of the data stack memory to the data bus. This invention realizes the object of implementing the push and pop operations through instructions, and improves the executive efficiency of the push and pop operations for data stack.

Description

Data stack storage circuit and microcontroller

Technical field

The present invention relates to the field of computer technologies, and in particular, to a data stack storage circuit and a microcontroller. Background technique

The stack push and pop operations are a data processing method that is widely used in microcontrollers. The stack mainly includes the program stack and the data stack, wherein the program stack should be saved and restored to the current program address in almost all of the microcontrollers, when the main program jumps or interrupts. Since early low-end microcontrollers had to process relatively little data and the application architecture was relatively simple, the data stack was rarely involved. However, with the wide application of microcontrollers and the complexity of application systems, the complexity of data processing and application structure increases, especially the use of high-level language development environments, and a large number of function variables are often saved and restored; In this case, since the data stack can easily protect and recover a large amount of data, more and more microcontrollers start to apply the data stack, and the data stack operation mode is also improved to improve the preservation and Restore a large number of function variables for efficiency.

4 is a schematic diagram of a stack structure of a prior art low-end microcontroller. As shown in FIG. 4, in the prior art, for the low-end and mid-range microcontrollers, the data stack of the hardware structure is rarely used, and the on-chip general-purpose data memory is mostly used as the hardware foundation, and the data stack is simulated by software. Operation. Specifically, a memory of an address space of the general-purpose data memory is used as a data stack; a general-purpose data memory or a register is used as a stack pointer, and the address of the current top of the stack is stored, and all the push and pop operations are performed through ordinary A memory transfer or arithmetic instruction is completed. In these low In the terminal microcontroller, since the data stack needs to occupy part of the data space of the general data memory, it is difficult to ensure the relative independence of the protected data in the data stack from other data in the general data memory. Specifically, when the related program is executed to call other data of the general data memory, it is possible to misinterpret the contents of the data stack, thereby causing the data protected in the data stack to be overwritten, thus having the low end of the data stack. The form of microcontroller architecture has the disadvantage of poor data security.

FIG. 5 is a schematic diagram of a stack structure in a prior art high-end microcontroller. As shown in Figure 5, for mid- to high-end microcontrollers, the data stack of the hardware structure is used as a separate data stack memory. Specifically, by setting a data stack read or write control bit included in the read or write control register, the read or write buffer register is temporarily operated on the data to be pushed onto the stack or the data read out of the stack; by a specific hardware register As a stack pointer, store the address of the current top of the stack for push or pop operations. In the data stack-related architecture of these mid- to high-end microcontrollers, stacking and popping operations are inefficient because of the need to indirectly manipulate the data stack through read or write control registers and read or write buffer registers. Summary of the invention

The present invention provides a data stack storage circuit and a microcontroller for solving the problem of the existing microcontroller by indirectly indirectly operating the data stack through a read or write control register and a read or write buffer register. Defects that are not efficient with pop-up operations.

The present invention provides a data stack storage circuit including a data stack memory and a data stack control circuit; the data stack memory and the data stack control circuit are connected;

The data stack memory is coupled to the data bus;

The data stack control circuit is connected to the control bus; And the data stack control circuit is configured to press the data of the data bus that has been ready to be pushed onto the top of the stack of the data stack memory according to the push operation signal in the control bus, or for controlling according to the control A pop operation signal in the bus ejects data ready for the stack from the top of the data stack memory to the data bus.

The present invention provides a microcontroller, including a controller, further comprising a data stack storage circuit; the controller is connected to a control bus, and the controller is configured to generate a first by analyzing an operation code of the push instruction Controlling the signal set and transmitting to the control bus; or for analyzing the opcode of the pop instruction to generate a second set of control signals and transmitting to the control bus; the data stack storage circuit includes a data stack memory and a data stack control circuit; the data stack memory and the data stack control circuit are connected; the data stack memory is connected to the data bus; the data stack control circuit is connected to the control bus;

And the data stack control circuit is configured to press the data of the data bus that has been ready to be pushed onto the top of the stack of the data stack memory according to the push operation signal in the first control signal set, or for The pop operation signal in the second control signal set pops the data ready for the stack from the top of the data stack memory to the data bus.

The data stack storage circuit and the microcontroller of the present invention, by the data stack control circuit included in the data stack storage circuit, press the data ready for stacking in the data bus into the data stack memory according to the push operation signal in the control bus. The top of the stack, or according to the pop operation signal in the controlled bus, the technical solution that pops the data of the ready stack from the top of the stack of the data stack memory to the data bus, solves the need in the existing microcontroller The indirect operation of the data stack by reading or writing the control register and the read or write buffer register, so that the stacking and popping operations are not efficient, and the stacking and popping operations are respectively implemented through respective correlations. Means For the purpose of completion, the complicated chip architecture of the read or write control register and the read or write buffer register is omitted, and the execution efficiency of stacking and popping the data stack is improved. DRAWINGS

1 is a schematic structural diagram of a data stack storage circuit of the present invention;

2 is a schematic structural diagram of Embodiment 1 of a microcontroller according to the present invention;

3 is a schematic structural diagram of Embodiment 2 of a microcontroller according to the present invention;

4 is a schematic diagram of a stack structure of a prior art low-end microcontroller;

FIG. 5 is a schematic diagram of a stack structure of a prior art high-end microcontroller. detailed description

In order to make the objects, technical solutions and advantages of the present invention more clear, the technical solutions of the present invention will be described below in conjunction with the drawings in the present invention.

FIG. 1 is a schematic structural diagram of a data stack storage circuit of the present invention. As shown in FIG. 1, the data stack storage circuit of this embodiment includes a data stack memory 101 and a data stack control circuit 102. The data stack memory 101 is connected to a data stack control circuit 102, wherein the data stack memory 101 is connected to the data bus. The data stack control circuit 102 is coupled to the control bus, and the data stack control circuit 102 includes a push control circuit module 1021 and a pop control circuit module 1022. The data stack memory 101 is dedicated to store data, instead of storing the program address; and the data stack memory and the program protection stack and the general data register file are independent of each other, and the operation of the data stack memory 101 needs to pass the push instruction ( Can be identified as a PUSH instruction in the programming language) and a pop instruction (identified as a POP instruction in the programming language) The data stack memory 101 is operated without the normal read and write operations of the controller. During the push operation, the push control circuit module 1021 in the data stack control circuit 102 pushes the data ready for stacking in the data bus into the stack of the data stack memory 101 according to the push operation signal in the control bus. Top, where the data ready to be pushed can be the data obtained by addressing 10 ports, the data to be protected in the interrupt operation, or the data obtained by addressing the data memory; during the pop operation, the data stack control The pop control circuit module 1022 in the circuit 102 pops the data ready for the stack from the top of the stack of the data stack memory 101 into the data bus based on the pop operation signal in the control bus.

In practical applications, the data stack memory 101 can be a separate memory, or a partial memory space of a separate memory, or a combination of at least two independent memories, or at least one independent memory and at least one independent A combination of partial storage spaces of memory, or a combination of partial storage spaces in at least two separate memories.

Further, the data stack storage circuit of this embodiment further includes a hardware stack pointer 103 connected to the control bus and the data stack memory 101, and the hardware stack pointer 103 is in the push control circuit module 1021 according to the control bus. After the push operation signal pushes the data ready for stacking in the data bus into the top of the stack of the data stack memory 101, it may add 1 by itself according to the hardware stack pointer in the control bus; or in the pop control After the circuit module 1022 pops the data of the ready stack from the top of the stack of the data stack memory 101 to the data bus according to the pop operation signal in the control bus, the circuit stack pointer can be decremented by 1 according to the hardware stack pointer in the control bus. Minus 1.

Still further, the data stack storage circuit of this embodiment further includes an overflow flag register 104, which is connected to the hardware stack pointer 103, and the overflow flag register 104 packet The overflow flag bit 1041 and the underflow flag bit 1042 are included; during the push operation, the current hardware stack pointer 103 is compared with the upper limit value by a comparison circuit to monitor the state of the hardware stack pointer 103 when the hardware stack pointer When the 103 is incremented from the highest address and jumps back to the lowest address, the overflow flag 1041 is automatically set to 1, and the upper limit is the highest address of the data stack memory 101; during the pop operation, the current hardware is compared by the comparison circuit. The stack pointer 103 is compared with the lower limit value to monitor the state of the hardware stack pointer 103. When the hardware stack pointer 103 is decremented from the lowest address by one and jumps back to the highest address, the underflow flag bit 1042 is automatically set to 1, and the lower limit value is automatically set. Is the lowest address of the data stack memory 101.

The data stack storage circuit of the embodiment, by the data stack control circuit, presses the data ready for stacking in the data bus into the top of the stack of the data stack memory according to the push operation signal in the control bus, or according to the controlled bus The pop-up operation signal, the technical solution for popping the data of the ready-to-stack data from the top of the stack of the data stack memory to the data bus, solves the problem that the existing microcontroller needs to pass the read or write control register and read or write. The buffer register indirectly operates on the data stack, so that the stacking and popping operations are not efficient, and the push and pop operations are completed by the corresponding corresponding instructions, which saves the need. Read or write control registers and read or write buffer registers in a complex chip architecture form, and improve the efficiency of the stack and pop operations of the data stack.

2 is a schematic structural view of Embodiment 1 of the cymbal controller of the present invention. As shown in FIG. 2, the microcontroller of this embodiment includes a controller 201 and a data stack storage circuit 202, wherein the controller 201 is connected to a control bus, and the controller 201 includes a program memory, an instruction register, and an instruction decoder. And the control logic circuit; the data stack storage circuit 202 includes a data stack memory 101 and a data stack control circuit 102, the data stack memory 101 and the data stack control circuit 102 are connected, and the data stack memory 101 is connected to the data bus, the data stack control circuit 102 is coupled to the control bus, and the data stack control circuit 102 includes a push control circuit module 1021 and a pop control circuit Module 1022. The data stack memory 101 is dedicated to store data, instead of storing the program address; and the data stack memory and the program protection stack and the general data register file are independent of each other, and the operation of the data stack memory 101 needs to pass the push instruction ( The program language can be identified as a PUSH instruction and the pop instruction (which can be identified as a POP instruction in the programming language), and the data stack memory 101 cannot be operated with normal read and write operations of the controller 201.

Further, the data stack storage circuit 202 further includes a hardware stack pointer 103 and the overflow flag register 104, wherein the hardware stack pointer 103 is connected to the control bus and the data stack memory 101, and the overflow flag register 104 is connected to the hardware stack pointer 103 and overflows. The flag register 104 includes an overflow flag bit 1041 and an underflow flag bit 1042;

During the push operation, the instruction register of the controller 201 reads the push instruction (which can be identified as a PUSH instruction in the programming language) from the program memory, and then includes the push instruction included in the instruction register by the instruction decoder. The opcode is decoded to generate a first set of control signals, and is sent by the control logic to the associated module circuit via the control bus for control purposes. The first set of control signals includes at least a push operation signal and a hardware stack pointer plus 1 signal; the push control circuit module 1021 in the data stack control circuit 102 pushes the data ready for stacking in the data bus into the top of the stack of the data stack memory 101 according to the push operation signal, wherein the stack is ready to be pushed The data may be data obtained by addressing 10 ports, data to be protected in the interrupt operation, or data obtained by addressing the data memory; and, the hardware stack pointer 103 is pushed in the stack control circuit module 1021 according to the push operation signal After the data in the data bus ready to be pushed onto the top of the stack of the data stack memory 101, The hardware stack pointer plus 1 signal in the control bus adds 1 to itself and points to the new top of the stack. For each action of the hardware stack pointer 103, the current hardware stack pointer 103 and the upper limit are compared by the comparison circuit. Compare to monitor the hardware stack pointer 103 State, when the hardware stack pointer 103 is incremented from the highest address and jumps back to the lowest address, the overflow flag bit 1041 is automatically set to 1, and the upper limit value is the highest address of the data stack memory 101.

During the pop operation, the instruction register of the controller 201 reads the pop instruction from the program memory (which can be identified as a POP instruction in the programming language), and then includes the pop-up instruction in the instruction register by the instruction decoder. The opcode is decoded to generate a second set of control signals, and is sent by the control logic to the associated module circuit via the control bus for control purposes. The second set of control signals includes at least a pop operation signal and a hardware stack pointer minus 1 signal; the pop control circuit module 1022 in the data stack control circuit 102 pops the data of the ready stack from the top of the stack of the data stack memory 101 into the data bus according to the pop operation signal, and can be controlled by the second The control signal control related circuit module in the signal set receives the data popped up to the data bus; and, the hardware stack pointer 103, at the pop control circuit module 1022, prepares the data of the ready stack from the data stack memory 101 according to the pop operation signal. After the top of the stack pops up to the data bus, it can be based on the hard in the control bus. The stack pointer minus 1 signal is decremented by 1 and points to the new top of the stack. For each action of the hardware stack pointer 103 minus 1, the current hardware stack pointer 103 is compared to the lower limit by the comparison circuit to monitor the hardware stack. The state of the pointer 103, when the hardware stack pointer 103 is decremented by one from the lowest address and jumps back to the highest address, the underflow flag 1042 is automatically set to 1, and the lower limit is the lowest address of the data stack memory 101.

The microcontroller of this embodiment is controlled by a data stack included in the data stack storage circuit The circuit presses the data ready for stacking in the data bus into the top of the stack of the data stack memory according to the push operation signal in the control bus, or according to the pop operation signal in the controlled bus, the ready stack is prepared. The technical solution of data being ejected from the top of the data stack memory to the data bus solves the problem that the existing microcontroller needs to operate the data stack indirectly through the read or write control register and the read or write buffer register. The disadvantages of inefficient stacking and popping operations are realized by the stacking and popping operations through the corresponding corresponding instructions, eliminating the need for read or write control registers and read or write buffer registers. The chip architecture form, and improve the efficiency of the stack and pop operations of the data stack.

FIG. 3 is a schematic structural diagram of Embodiment 2 of a microcontroller according to the present invention. As shown in FIG. 2 and FIG. 3, the microcontroller of this embodiment further includes an address selector 203 and a data memory 204 based on the above embodiment, wherein the address selector 203 is connected to the controller 201, the address bus, and the control. a data memory 204 is coupled to the control bus, the data bus, and the address bus;

In the present embodiment, the data of the address data memory 204 is mainly described, and the data is pushed into the stack operation of the data stack memory 101; and the data popped up in the data stack memory 101 is stored in the data memory 204. Pop-up operation process; specifically,

During the push operation, the instruction register of the controller 201 reads the push instruction (which can be identified as a PUSH instruction in the programming language) from the program memory, and then includes the push instruction included in the instruction register by the instruction decoder. The opcode is decoded to generate a first set of control signals, and is sent by the control logic to the associated module circuit via the control bus for control purposes. The first set of control signals includes a push operation signal, a hardware stack pointer plus one. a signal, a first address decode operation signal, and a read data memory signal, and the instruction decoder of the controller 201 transmits the first operand included in the push instruction to the address selector 203; the address selector 203 is based on the first address Decoding The operation signal decodes the first operand sent by the controller 201 to generate a first data memory address and sends it to the address bus; the data memory 204 is ready to press according to the read data memory signal and the first data memory address. The data of the stack is written on the data bus; and the push control circuit module 1021 in the data stack control circuit 102 pushes the data ready for stacking in the data bus into the top of the stack of the data stack memory 101 according to the push operation signal. The data that has been prepared to be pushed is the data obtained by addressing 10 ports; the hardware stack pointer 103 pushes the data of the data bus that is ready to be pushed onto the data stack according to the push operation signal in the push control circuit module 1021. After the top of the memory 101 is stacked, it can be incremented by 1 according to the hardware stack pointer in the control bus, and points to the new top of the stack; for each increment of the hardware stack pointer 103, the comparison circuit will The current hardware stack pointer 103 is compared to the upper limit value to monitor the state of the hardware stack pointer 103 when the hardware stack pointer 103 is the most An address by adding 1 to the lowest address jump back, automatic overflow flag bit 1041 is set, the upper limit value and the highest address of the data stack memory 101.

During the pop operation, the instruction register of the controller 201 reads the pop instruction from the program memory (which can be identified as a POP instruction in the programming language), and then includes the pop-up instruction in the instruction register by the instruction decoder. The opcode is decoded to generate a second set of control signals, and is sent by the control logic circuit to the associated module circuit through the control bus for control purposes. The second set of control signals includes a pop operation signal, and the hardware stack pointer is decremented by one. a signal, a second address decode operation signal, and a write data memory signal, and the instruction decoder of the controller 201 sends the second operand included in the push instruction to the address selector 203; the output in the data stack control circuit 102 The stack control circuit module 1022 pops the data of the ready stack from the top of the stack of the data stack memory 101 into the data bus according to the pop operation signal; the address selector 203 decodes the operation signal according to the second address, and controls the controller The second operand sent by 201 is decoded to generate a second data memory The address is sent to the address bus; the data memory 204 reads the data of the popped stack from the data bus according to the write data memory signal and the second data memory address; the hardware stack pointer 103 is popped according to the popup control circuit module 1022. After the operation signal pops the data of the ready stack from the top of the stack of the data stack memory 101 to the data bus, it can be decremented by 1 according to the hardware stack pointer minus 1 signal, and points to the new stack top; for each of the hardware stack pointers 103 The action of subtracting 1 times compares the current hardware stack pointer 103 with the lower limit value by the comparison circuit to monitor the state of the hardware stack pointer 103. When the hardware stack pointer 103 is decremented from the lowest address by 1 and jumps back to the highest address, The underflow flag bit 1042 is automatically set to 1, and the lower limit value is the lowest address of the data stack memory 101.

In the microcontroller of the embodiment, the data stack control circuit included in the data stack storage circuit presses the data ready for stacking in the data bus into the top of the stack of the data stack memory according to the push operation signal in the control bus. Or according to the pop operation signal in the controlled bus, the technical solution that pops the data of the ready stack from the top of the stack of the data stack memory to the data bus solves the problem that the existing microcontroller needs to pass the read or write. The control register and the read or write buffer register indirectly operate on the data stack, so that the push and pop operations are not efficient, and the push and pop operations are completed by the respective corresponding instructions. The purpose is to eliminate the complicated chip architecture of reading or writing control registers and reading or writing buffer registers, and improve the efficiency of performing stacking and popping operations on the data stack.

It should be noted that the above embodiments are only for explaining the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: The technical solutions described in the foregoing embodiments are modified, or some of the technical features are equivalently replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

Rights request

A data stack storage circuit, comprising: a data stack memory and a data stack control circuit; the data stack memory and the data stack control circuit are connected; the data stack memory is connected to the data bus;

The data stack control circuit is connected to the control bus;

And the data stack control circuit is configured to press the data of the data bus that has been ready to be pushed onto the top of the stack of the data stack memory according to the push operation signal in the control bus, or for controlling according to the control A pop operation signal in the bus ejects data ready for the stack from the top of the data stack memory to the data bus.

2. The data stack storage circuit according to claim 1, wherein the data stack memory is a separate memory, or is a partial memory of a separate memory, or a combination of at least two independent memories. Or a combination of at least one independent memory and a partial storage space of at least one independent memory, or a combination of partial storage spaces in at least two independent memories.

3. The data stack storage circuit according to claim 1, wherein the data stack control circuit comprises a push control circuit module and a pop control circuit module;

The push control circuit module is configured to press data ready for stacking in the data bus into a top of the stack of the data stack memory according to a push operation signal in the control bus; The circuit module is configured to pop the data of the prepared stack from the top of the stack of the data stack memory to the data bus according to the pop operation signal in the control bus.

4. The data stack storage circuit of claim 1, further comprising a hardware stack pointer, the hardware stack pointer being coupled to the control bus and the data stack memory; The hardware stack pointer is used to add 1 according to the hardware stack pointer plus 1 signal in the control bus after the data ready for stacking in the data bus is pushed onto the top of the stack of the data stack memory. Or, after the data ready to be bounced is popped from the top of the data stack memory to the data bus, the data is decremented by one according to the hardware stack pointer minus one signal in the control bus.

5. The data stack storage circuit of claim 4, further comprising an overflow flag register, the overflow flag register being coupled to the hardware stack pointer, and the overflow flag register including an overflow flag bit and a lower Overflow flag.

6. A microcontroller, comprising: a controller, further comprising: a data stack storage circuit; the controller is coupled to the control bus, and the controller is configured to analyze the operation code of the push instruction to generate a a control signal set and sent to the control bus; or, for analyzing an opcode of the pop instruction to generate a second control signal set and transmitting to the control bus; the data stack storage circuit including a data stack memory And a data stack control circuit; the data stack memory and the data stack control circuit are connected; the data stack memory is connected to the data bus; the data stack control circuit is connected to the control bus;

7. The microcontroller according to claim 6, further comprising an address selector, said address selector being connected to said controller, said address bus and said control bus; said address selector Decoding according to the first address in the first set of control signals An operation signal, decoding a first operand in the push instruction sent by the controller to generate a first data memory address and transmitting the address to the address bus;

Or for decoding, according to the second address decoding operation signal in the second control signal set, a second operand in the pop instruction sent by the controller to generate a second data memory address and Sent to the address bus.

8. The microcontroller of claim 7, further comprising a data memory coupled to the control bus, the data bus, and the address bus; the data memory being configured to Reading data memory signals and first data memory addresses in the first control signal set, writing data to be pushed onto the data bus; or for writing data memory according to the second control signal set The signal and the second data memory address read data from the popped stack from the data bus.

The microcontroller according to claim 6, wherein the data stack control circuit comprises a push control circuit module and a pop control circuit module;

The push control circuit module is configured to press data ready for stacking in the data bus into a top of the stack of the data stack memory according to a push operation signal in the first control signal set;

The pop-up control circuit module is configured to pop the data of the ready-to-bounce stack from the top of the stack of the data stack memory to the data bus according to the pop-up operation signal in the second set of control signals.

10. The microcontroller of claim 6, further comprising a hardware stack pointer, the hardware stack pointer being coupled to the control bus and the data stack memory;

The hardware stack pointer is used to push data that is ready to be pushed in the data bus After the top of the data stack memory is stacked, 1 is added according to the hardware stack pointer in the control bus plus 1 signal; or the data of the ready stack is popped from the top of the data stack memory to the After the data bus, it is decremented by one according to the hardware stack pointer minus 1 signal in the control bus.

11. The microcontroller of claim 10, further comprising an overflow flag register, the overflow flag register being coupled to the hardware stack pointer, and the overflow flag register including an overflow flag bit and an underflow Sign bit.

12. The microcontroller according to claim 6, wherein the data stack memory is a separate memory, or is a partial memory space of a separate memory, or a combination of at least two independent memories. Either a combination of at least one independent memory and at least one independent memory, or a combination of at least two separate memory locations.