CN109885466B - Simulation method, system and medium for processor C8000 - Google Patents
Simulation method, system and medium for processor C8000 Download PDFInfo
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Abstract
The invention provides a simulation method, a system and a medium of a processor C8000, comprising the following steps: a mechanism simulation step: simulating the operation mechanism of the C8000 processor; register and memory simulation step: a register and a memory of the analog C8000 processor; and a device-on-chip simulation step: an on-chip device simulating C8000. The invention provides a chip-level simulation strategy, which solves the problem that the operation simulation of firmware cannot be basically completed by the simulation of a single processor module. The invention also greatly improves the simulation speed of the processor through the policy improvement of the MMU.
Description
Technical Field
The present invention relates to, in particular, to a method, system, and medium for simulating processor C8000. In particular to a simulation method facing a domestic autonomous controllable processor C8000.
Background
More of the current processor chip simulation still stays in the simulation of the functions of the processor, but the chip technology of the invention can completely realize the functions of the whole chip, can directly load the firmware binary file, and provides sufficient support for the subsequent higher-level simulation.
In addition, the original time processing mode and MMU processing mode greatly improve the simulation efficiency, avoid the time constraint to the maximum extent and concentrate on the verification of the firmware logic.
Patent document CN103207831B (application number: 201210009703.1) discloses a processor chip emulator, which includes an emulation chip, a clock source, a synchronization module and an emulation module; the simulation chip comprises a clock processing module and a processor core; the clock processing module receives an external clock signal generated by a clock source, performs frequency division or frequency multiplication on the external clock signal, and outputs the same working clock signal subjected to frequency division or frequency multiplication to the processor core and the synchronization module; the processor core generates various internal signals based on the working clock signal and outputs signals for the simulation module to track and interact with the simulation module to the simulation module through the interactive signal line group; the synchronization module generates a simulation clock signal after synchronizing the working clock signal; and the simulation module tracks the internal signal of the simulation chip on the interactive signal line group based on the simulation clock signal and outputs an interactive and replacing signal to the processor core.
Disclosure of Invention
In view of the defects in the prior art, the present invention provides a simulation method, system and medium for processor C8000.
The simulation method of the processor C8000 provided by the invention comprises the following steps:
a mechanism simulation step: simulating the operation mechanism of the C8000 processor;
register and memory simulation step: a register and a memory of the analog C8000 processor;
and a device-on-chip simulation step: an on-chip device simulating C8000.
Preferably, the mechanism simulating step comprises any one or more of the following steps:
an instruction translation step: dynamically translating the compiled machine code into an instruction set of a host platform;
time control step: when executing an instruction of a host platform corresponding to the C8000 instruction, the time count is increased by one, an event buffer area is checked, and whether an event needing to be processed exists in the event buffer area is judged: if the instruction exists, interrupting the execution flow of the instruction, processing the event needing to be processed and outputting time count; otherwise, continuing to execute the instruction and outputting time count;
memory management step: the correspondence between the virtual address and the actual address is realized by adopting a HASH algorithm;
and (3) operation simulation step: performing a simulation of operational control of a processor, the simulation of operational control comprising: any one or any multiple of fetch, decode, execute, write back operations.
Preferably, the register and memory emulation step comprises:
a register simulation step: setting a register simulation space on a host machine, realizing reading and writing of a register in a shadow register mode, and judging whether the change of the current register influences the execution of the next execution: if yes, synchronizing the simulation space of the register with the shadow register; otherwise, the register simulation space and the shadow register are not synchronized;
a memory simulation step: simulating the memory, and judging whether the host is 32 bits or 64 bits: if the data is 32 bits, the host accesses the 32-bit space backwards; if the bit number is 64, the host does not access 32 bit space backwards when accessing data.
Preferably, the device-on-chip simulating step includes:
functional simulation: performing a simulation of a basic functional module, the simulation of the basic functional module comprising: any one or more of an interrupt handler, an interrupt timer, and an interrupt watchdog;
a communication simulation step: performing simulation of a peripheral communication function module, the simulation of the peripheral communication function module including: performing a full simulation of any one or more of the peripheral devices QADC, DMA, EPORT, I2C, SCI, SPI, PIT, the full simulation comprising: the simulation of the register, the memory simulation and the internal logic simulation of each communication function module realize the access interface of the memory space and the register of each module, and then realize the logic caused by each access to complete the simulation.
A simulation system for processor C8000 according to the present invention provides a pair, comprising:
a mechanism simulation module: simulating the operation mechanism of the C8000 processor;
register and memory emulation module: a register and a memory of the analog C8000 processor;
the device-on-chip simulation module: an on-chip device simulating C8000.
Preferably, the mechanism simulation module comprises any one or more of the following:
the instruction translation module: dynamically translating the compiled machine code into an instruction set of a host platform;
a time control module: when executing an instruction of a host platform corresponding to the C8000 instruction, the time count is increased by one, an event buffer area is checked, and whether an event needing to be processed exists in the event buffer area is judged: if the instruction exists, interrupting the execution flow of the instruction and processing the event needing to be processed; otherwise, continuing to execute the instruction;
a memory management module: the correspondence between the virtual address and the actual address is realized by adopting a HASH algorithm;
the operation simulation module: performing a simulation of operational control of a processor, the simulation of operational control comprising: any one or any multiple of fetch, decode, execute, write back operations.
Preferably, the register and memory emulation module comprises:
a register simulation module: setting a register simulation space on a host machine, realizing reading and writing of a register in a shadow register mode, and judging whether the change of the current register influences the execution of the next execution: if yes, synchronizing the simulation space of the register with the shadow register; otherwise, the register simulation space and the shadow register are not synchronized;
a memory simulation module: simulating the memory, and judging whether the host is 32 bits or 64 bits: if the data is 32 bits, the host accesses the 32-bit space backwards; if the bit number is 64, the host does not access 32 bit space backwards when accessing data.
Preferably, the device-on-chip simulation module includes:
a function simulation module: performing a simulation of a basic functional module, the simulation of the basic functional module comprising: any one or more of an interrupt handler, an interrupt timer, and an interrupt watchdog;
a communication simulation module: performing a simulation of a communication function module, the simulation of the communication function module comprising: performing a full simulation of any one or more of peripheral devices QADC, DMA, EPORT, I2C, SCI, SPI, PIT, the full simulation including: the simulation of the register, the memory simulation and the internal logic simulation of each communication function module realize the access interface of the memory space and the register of each module, and then realize the logic caused by each access to complete the simulation.
According to the present invention, there is provided a computer readable storage medium storing a computer program, which when executed by a processor, implements the steps of the simulation method of the processor C8000 as described in any of the above.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention provides a chip-level simulation strategy, which solves the problem that the operation simulation of firmware cannot be basically completed by pure processor module simulation.
2. The invention has more convenient control on simulation, and can realize convenient start-stop, debugging, fault injection and the like.
3. The invention greatly improves the simulation speed of the processor by the policy improvement of the MMU.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
The simulation method of the processor C8000 provided by the invention comprises the following steps:
a mechanism simulation step: simulating the operation mechanism of the C8000 processor;
register and memory simulation step: simulating registers and memories of a C8000 processor;
and a device-on-chip simulation step: an on-chip device simulating C8000.
In particular, the mechanism simulating step comprises any one or more of the following steps:
an instruction translation step: dynamically translating the compiled machine code into an instruction set of a host platform;
time control step: when executing an instruction of a host platform corresponding to the C8000 instruction, the time count is increased by one, an event buffer area is checked, and whether an event needing to be processed exists in the event buffer area is judged: if the instruction exists, interrupting the execution flow of the instruction, processing the event needing to be processed and outputting time count; otherwise, continuing to execute the instruction and outputting time count;
memory management step: the correspondence between the virtual address and the actual address is realized by adopting a HASH algorithm;
and (3) operation simulation step: performing a simulation of operational control of a processor, the simulation of operational control comprising: any one or any multiple of fetch, decode, execute, write back operations.
Specifically, the register and memory simulation step includes:
a register simulation step: setting a register simulation space on a host machine, realizing reading and writing of a register in a shadow register mode, and judging whether the change of the current register influences the execution of the next execution: if yes, synchronizing the simulation space of the register with the shadow register; otherwise, the register simulation space and the shadow register are not synchronized;
a memory simulation step: simulating the memory, and judging whether the host is 32 bits or 64 bits: if the data is 32 bits, the host accesses the 32-bit space backwards more when accessing the data; if the bit is 64, the host does not access 32-bit space backwards when accessing data.
Specifically, the on-chip device simulation step includes:
functional simulation: performing a simulation of a basic functional module, the simulation of the basic functional module comprising: any one or more of an interrupt handler, an interrupt timer, and an interrupt watchdog;
a communication simulation step: performing simulation of a peripheral communication function module, the simulation of the peripheral communication function module including: performing a full simulation of any one or more of the peripheral devices QADC, DMA, EPORT, I2C, SCI, SPI, PIT, the full simulation comprising: the simulation of the register, the memory simulation and the internal logic simulation of each communication function module realize the access interface of the memory space and the register of each module, and then realize the logic caused by each access to complete the simulation.
The simulation system of the processor C8000 provided by the invention can be realized by the step flow of the simulation method of the processor C8000 provided by the invention. Those skilled in the art can understand the simulation method of the processor C8000 as a preferred example of the simulation system of the processor C8000.
A simulation system for processor C8000 according to the present invention provides a pair, comprising:
a mechanism simulation module: simulating the operation mechanism of the C8000 processor;
register and memory emulation module: a register and a memory of the analog C8000 processor;
the device-on-chip simulation module: an on-chip device simulating C8000.
In particular, the mechanism simulation module comprises any one or any plurality of the following modules:
the instruction translation module: dynamically translating the compiled machine code into an instruction set of a host platform;
a time control module: when executing an instruction of a host platform corresponding to the C8000 instruction, the time count is increased by one, an event buffer area is checked, and whether an event needing to be processed exists in the event buffer area is judged: if the instruction exists, interrupting the execution flow of the instruction and processing the event needing to be processed; otherwise, continuing to execute the instruction;
a memory management module: the correspondence between the virtual address and the actual address is realized by adopting a HASH algorithm;
the operation simulation module: performing a simulation of operational control of a processor, the simulation of operational control comprising: any one or any multiple of fetch, decode, execute, write back operations.
Specifically, the register and memory emulation module includes:
a register simulation module: setting a register simulation space on a host machine, realizing reading and writing of a register in a shadow register mode, and judging whether the change of the current register influences the execution of the next execution: if yes, synchronizing the simulation space of the register with the shadow register; otherwise, the register simulation space and the shadow register are not synchronized;
a memory simulation module: simulating the memory, and judging whether the host is 32 bits or 64 bits: if the data is 32 bits, the host accesses the 32-bit space backwards; if the bit is 64, the host does not access 32-bit space backwards when accessing data.
Specifically, the on-chip device simulation module includes:
a function simulation module: performing a simulation of a basic functional module, the simulation of the basic functional module comprising: any one or more of an interrupt handler, an interrupt timer, and an interrupt watchdog;
a communication simulation module: performing a simulation of a communication function module, the simulation of the communication function module comprising: performing a full simulation of any one or more of peripheral devices QADC, DMA, EPORT, I2C, SCI, SPI, PIT, the full simulation including: the simulation of the register, the memory simulation and the internal logic simulation of each communication function module realize the access interface of the storage space and the register of each module, and then realize the logic caused by each access to complete the simulation.
According to the present invention, there is provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the simulation method of the processor C8000 as described in any of the above.
The present invention will be described more specifically below with reference to preferred examples.
Example 1:
the method comprises the following steps:
step 1: simulating the operation mechanism of the C8000 processor;
step 2: simulation of the C8000 processor register and memory;
and step 3: simulation of a device on a C8000 chip;
wherein, step 1 includes the following functional module:
module 1.1: translating the instruction set, namely dynamically translating the compiled machine code into an instruction of a host platform;
module 1.2: time control, which adopts an independent time control module, and the simulation time slice and the physical time slice do not strictly correspond; when executing an instruction of the host platform corresponding to the C8000 instruction, the time count is increased by one; the method comprises the steps that an event mode is created to realize the control of interruption and periodic behaviors, the event mode is realized through an event buffer area, an execution thread checks the event buffer area after executing an instruction to see whether an event needing to be processed exists or not, if the event exists, the execution flow of the instruction is interrupted, the event is processed, and otherwise, the instruction is continuously executed.
Module 1.3: in memory management, the address bus is 36 bits, so that the C8000 has a complex MMU control function, and according to the characteristics of the MMU, a HASH algorithm is adopted to realize the correspondence between the virtual address and the actual address, thereby realizing the internal reading speed with the complexity of O (1).
Module 1.4: the operation control module is used for simulating the operation control of the processor: including the steps of fetching, decoding, executing, writing back, etc.
The step 2 comprises the following steps:
step 2.1: the simulation of the processor register, open up a space on the host computer and is used for the simulation of the register, because the reading and writing of the register are very frequent; the fast reading and writing of the host computer is realized by adopting a shadow register mode, a space opened on the host computer and the shadow register are synchronized at necessary time, the register cannot be synchronized when the change of the current register does not influence the execution of the next instruction, otherwise, the register is required to be synchronized.
Step 2.2: the simulation of the memory, according to the mechanism of C8000, we need to provide two accesses of 32 bits and 64 bits, in order to avoid the problem that the host 32 bit host accesses 64 bits of data slowly, we adopt the mode of automatically accessing 32 bits of space backwards more, and avoid the problem that 64 bits of data is slow in the process of transferring.
The step 3 comprises the following steps:
step 3.1: simulation of a C8000 basic function module, including an interrupt controller, a timer, a watchdog and the like;
step 3.2: simulation of peripheral communication functional modules of C8000, including complete simulation of peripheral equipment such as QADC, DMA, EPORT, I2C, SCI, SPI, PIT, etc., including register simulation, memory simulation and internal logic simulation of each functional module; the method comprises the steps of firstly realizing the access interfaces of the storage space and the register of each module, and then realizing the logic caused by each access, thereby achieving the effect of simulation.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations and positional relationships that are merely used to facilitate the description of the present application and to simplify the description, but do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be considered as limiting the present application.
Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and individual modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps into logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (9)
1. A simulation method of a processor C8000 is characterized by comprising the following steps:
a mechanism simulation step: simulating the operation mechanism of the C8000 processor;
register and memory simulation step: a register and a memory of the analog C8000 processor;
and a device-on-chip simulation step: simulating a C8000 on-chip device;
time control step: when executing an instruction of a host platform corresponding to the C8000 instruction, adding one to the time count, checking an event buffer area, and judging whether an event needing to be processed exists in the event buffer area: if the event exists, interrupting the execution flow of the instruction, processing the event needing to be processed and outputting time count; otherwise, continuing to execute the instruction and outputting a time count;
the register and memory emulation steps include:
a register simulation step: setting a register simulation space on a host machine, realizing reading and writing of a register by adopting a shadow register mode, and judging whether the change of the current register influences the execution of the next execution: if yes, synchronizing the simulation space of the register with the shadow register; otherwise, the register simulation space and the shadow register are not synchronized.
2. The method according to claim 1, wherein the mechanism simulation step comprises any one or more of the following steps:
an instruction translation step: dynamically translating the compiled machine code into an instruction set of a host platform;
a memory management step: the correspondence between the virtual address and the actual address is realized by adopting a HASH algorithm;
and (3) operation simulation step: performing a simulation of operational control of a processor, the simulation of operational control comprising: any one or any multiple of fetch, decode, execute, write back operations.
3. The method of emulation of processor C8000 of claim 1, wherein said register and memory emulation steps comprise:
a memory simulation step: simulating the memory, and judging whether the host is 32 bits or 64 bits: if the data is 32 bits, the host accesses the 32-bit space backwards; if the bit number is 64, the host does not access 32 bit space backwards when accessing data.
4. The method of simulating of processor C8000 of claim 1, wherein said device-on-a-chip simulation step comprises:
functional simulation: performing a simulation of a basic functional module, the simulation of the basic functional module comprising: any one or more of an interrupt handler, an interrupt timer, and an interrupt watchdog;
a communication simulation step: performing simulation of a peripheral communication function module, the simulation of the peripheral communication function module including: performing a full simulation of any one or any plurality of peripheral devices QADC, DMA, EPORT, I2C, SCI, SPI, PIT, the full simulation comprising: the simulation of the register, the memory simulation and the internal logic simulation of each communication function module realize the access interface of the memory space and the register of each module, and then realize the logic caused by each access to complete the simulation.
5. A simulation system for a processor C8000, comprising:
a mechanism simulation module: simulating the operation mechanism of the C8000 processor;
register and memory emulation module: a register and a memory of the analog C8000 processor;
the device-on-chip simulation module: simulating a C8000 on-chip device;
a time control module: when executing an instruction of a host platform corresponding to the C8000 instruction, the time count is increased by one, an event buffer area is checked, and whether an event needing to be processed exists in the event buffer area is judged: if the event exists, interrupting the execution flow of the instruction and processing the event needing to be processed; otherwise, continuing to execute the instruction;
the register and memory emulation module comprises:
a register simulation module: setting a register simulation space on a host machine, realizing reading and writing of a register by adopting a shadow register mode, and judging whether the change of the current register influences the execution of the next execution: if yes, synchronizing the simulation space of the register with the shadow register; otherwise, the register emulation space and the shadow register are not synchronized.
6. The emulation system of processor C8000 of claim 5, wherein the mechanism simulation module comprises any one or more of the following:
the instruction translation module: dynamically translating the compiled machine code into an instruction set of a host platform;
a memory management module: the correspondence between the virtual address and the actual address is realized by adopting a HASH algorithm;
the operation simulation module: performing a simulation of operational control of a processor, the simulation of operational control comprising: any one or any multiple of fetch, decode, execute, write back operations.
7. The emulation system of processor C8000 of claim 5, wherein the register and memory emulation module comprises:
a memory simulation module: simulating the memory, and judging whether the host is 32 bits or 64 bits: if the data is 32 bits, the host accesses the 32-bit space backwards; if the bit number is 64, the host does not access 32 bit space backwards when accessing data.
8. The emulation system of processor C8000 of claim 5, wherein the on-chip device emulation module comprises:
a function simulation module: performing a simulation of a basic functional module, the simulation of the basic functional module comprising: any one or more of an interrupt handler, an interrupt timer, and an interrupt watchdog;
a communication simulation module: performing a simulation of a communication function module, the simulation of the communication function module comprising: performing a full simulation of any one or more of the peripherals QADC, DMA, EPORT, I2C, SCI, SPI, PIT, the full simulation comprising: the simulation of the register, the memory simulation and the internal logic simulation of each communication function module realize the access interface of the memory space and the register of each module, and then realize the logic caused by each access to complete the simulation.
9. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the simulation method of the processor C8000 of any of claims 1 to 4.
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| CN101425020A (en) * | 2007-10-31 | 2009-05-06 | 国际商业机器公司 | Method and device for accelerating MMU emulation and total system emulator |
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