CN109885466A - Emulation mode, system and the medium of processor C8000 - Google Patents
Emulation mode, system and the medium of processor C8000 Download PDFInfo
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Abstract
The present invention provides emulation mode, system and the media of a kind of processor C8000, comprising: mechanism simulation step: the operating mechanism of simulation C8000 processor；Register and memory simulation steps: the register and memory of simulation C8000 processor；On piece equipment simulating step: the on piece equipment of C8000 is simulated.The present invention provides the Simulation Strategy of chip-scale, solves the problems, such as that simple processor module emulation is unable to complete the running simulation of firmware substantially.The present invention also by the stragetic innovation of MMU, greatly improves the simulation velocity of processor.
Description
Technical field
The present invention relates to, and in particular, to emulation mode, system and the medium of processor C8000.In particular, it is related to one
Emulation mode of the kind towards domestic autonomous controllable processor C8000.
Background technique
Current processor chips emulation, more still rests in the emulation of processor function itself, and of the invention
Chip technology can completely realize the function of entire chip, firmware binary file can be loaded directly into operation, after being
The emulation of continuous higher level provides sufficient support.
In addition the time-triggered protocol mode and MMU processing mode created greatly improve the efficiency of emulation, and maximum
Degree avoid temporal constraint, be absorbed in the verifying with firmware logic.
Patent document CN103207831B (application number: 201210009703.1) discloses a kind of processor chips emulation
Device, including emulation chip, clock source, synchronization module and emulation module；It include clock processing module and processor in emulation chip
Core；Clock processing module receives the external timing signal that clock source generates, and carries out frequency dividing or frequency multiplication to the external timing signal,
Operating clock signals after exporting identical divided or process of frequency multiplication to processor core and synchronization module；Processor core is based on
Operating clock signals generate various internal signals, and are exported by interactive signal line group to emulation module and tracked for emulation module
And the signal interacted with emulation module；Synchronization module generates simulation clock signal after synchronizing to operating clock signals；It is imitative
True module tracks the emulation chip internal signal in interactive signal line group based on the simulation clock signal, to processor
Core output interaction and replacement signal.
Summary of the invention
For the defects in the prior art, the object of the present invention is to provide the emulation mode of processor C8000 a kind of, be
System and medium.
The emulation mode of the processor C8000 provided according to the present invention a kind of, comprising:
Mechanism simulation step: the operating mechanism of simulation C8000 processor；
Register and memory simulation steps: the register and memory of simulation C8000 processor；
On piece equipment simulating step: the on piece equipment of C8000 is simulated.
Preferably, the mechanism simulation step any one of includes the following steps or appoints multinomial:
Instruction translation step: compiled machine code is subjected to dynamic translation, translates into the instruction set of host's machine platform；
Time rate-determining steps: one C8000 of every execution instructs the instruction of corresponding host's machine platform, and time counting adds one,
It checks event buffer, judges in event buffer with the presence or absence of event to be treated: if it exists, then interrupting holding for instruction
Row process handles event to be treated, exports time counting；Otherwise, then instruction is continued to execute, time counting is exported；
Memory management step: the correspondence of its virtual address and actual address is realized using HASH algorithm；
Running simulation step: to processor carry out operation control simulation, it is described operation control simulation include: extract,
Any one of decoding, execution, written-back operation are appointed a variety of.
Preferably, the register and memory simulation steps include:
Register analog step: register analog space is set on host, is realized by the way of shadow register
Register reads and writees, and judges the execution of an execution under the influence of the change whether of actual registers: if so, will post
It is synchronous with shadow register that storage simulates space；Otherwise, then register analog space is not synchronized with shadow register；
Memory simulation steps: simulating memory, judges that host is 32 or 64: if 32, then
It is backward to access 32 bit spaces when host accesses data more；If 64, then when host access data, not more access backward
32 bit spaces.
Preferably, the on piece equipment simulating step includes:
Functional simulation step: carrying out the emulation of basic function module, and the emulation of the basic function module includes: at interruption
It manages any one of device, Abort Timer timer, interruption house dog watchdog or appoints a variety of；
Communication simulation step: the emulation of periphery communication function module, the simulation package of the periphery communication function module are carried out
It includes: to any one of peripheral equipment QADC, DMA, EPORT, I2C, SCI, SPI, PIT or appointing a variety of carry out full simulations,
The full simulation includes: the register analog of each communication function module, memory simulation and internal logic simulation, is realized each
Then the memory space of a module and the access interface of register realize the logic that access is caused every time, complete simulation.
The analogue system of a kind of processor C8000 of offer pair according to the present invention, comprising:
Mechanism simulation module: the operating mechanism of simulation C8000 processor；
Register and memory analog module: the register and memory of simulation C8000 processor；
On piece equipment simulating module: the on piece equipment of C8000 is simulated.
Preferably, the mechanism simulation module any one of comprises the following modules or appoints multinomial:
Instruction translation module: compiled machine code is subjected to dynamic translation, translates into the instruction set of host's machine platform；
Time control module: one C8000 of every execution instructs the instruction of corresponding host's machine platform, and time counting adds one,
It checks event buffer, judges in event buffer with the presence or absence of event to be treated: if it exists, then interrupting holding for instruction
Row process handles event to be treated；Otherwise, then instruction is continued to execute；
Memory management module: the correspondence of its virtual address and actual address is realized using HASH algorithm；
Running simulation module: to processor carry out operation control simulation, it is described operation control simulation include: extract,
Any one of decoding, execution, written-back operation are appointed a variety of.
Preferably, the register and memory analog module includes:
Register analog module: register analog space is set on host, is realized by the way of shadow register
Register reads and writees, and judges the execution of an execution under the influence of the change whether of actual registers: if so, will post
It is synchronous with shadow register that storage simulates space；Otherwise, then register analog space is not synchronized with shadow register；
Memory analog module: simulating memory, judges that host is 32 or 64: if 32, then
It is backward to access 32 bit spaces when host accesses data more；If 64, then when host access data, not more access backward
32 bit spaces.
Preferably, the on piece equipment simulating module includes:
Functional simulation module: carrying out the emulation of basic function module, and the emulation of the basic function module includes: at interruption
It manages any one of device, Abort Timer timer, interruption house dog watchdog or appoints a variety of；
Communication simulation module: the emulation of communication function module is carried out, the emulation of the communication function module includes: to periphery
Any one of equipment QADC, DMA, EPORT, I2C, SCI, SPI, PIT appoint a variety of carry out full simulations, the complete mould
Quasi- includes: register analog, memory simulation and the internal logic simulation of each communication function module, realizes depositing for modules
The access interface in space and register is stored up, the logic that access is caused every time is then realized, completes simulation.
A kind of computer readable storage medium for being stored with computer program provided according to the present invention, the computer journey
The step of emulation mode of processor C8000 described in any of the above embodiments is realized when sequence is executed by processor.
Compared with prior art, the present invention have it is following the utility model has the advantages that
1, the present invention provides the Simulation Strategy of chip-scale, solves simple processor module emulation and is unable to complete substantially
The problem of running simulation of firmware.
2, the present invention is more convenient to the control of emulation, and convenient and fast start and stop may be implemented, and debugs, direct fault location etc..
3, the present invention greatly improves the simulation velocity of processor by the stragetic innovation of MMU.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the common skill of this field
For art personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to this
The protection scope of invention.
The emulation mode of the processor C8000 provided according to the present invention a kind of, comprising:
Mechanism simulation step: the operating mechanism of simulation C8000 processor；
Register and memory simulation steps: the register and memory of simulation C8000 processor；
On piece equipment simulating step: the on piece equipment of C8000 is simulated.
Specifically, the mechanism simulation step any one of includes the following steps or appoints multinomial:
Instruction translation step: compiled machine code is subjected to dynamic translation, translates into the instruction set of host's machine platform；
Time rate-determining steps: one C8000 of every execution instructs the instruction of corresponding host's machine platform, and time counting adds one,
It checks event buffer, judges in event buffer with the presence or absence of event to be treated: if it exists, then interrupting holding for instruction
Row process handles event to be treated, exports time counting；Otherwise, then instruction is continued to execute, time counting is exported；
Memory management step: the correspondence of its virtual address and actual address is realized using HASH algorithm；
Running simulation step: to processor carry out operation control simulation, it is described operation control simulation include: extract,
Any one of decoding, execution, written-back operation are appointed a variety of.
Specifically, the register and memory simulation steps include:
Register analog step: register analog space is set on host, is realized by the way of shadow register
Register reads and writees, and judges the execution of an execution under the influence of the change whether of actual registers: if so, will post
It is synchronous with shadow register that storage simulates space；Otherwise, then register analog space is not synchronized with shadow register；
Memory simulation steps: simulating memory, judges that host is 32 or 64: if 32, then
It is backward to access 32 bit spaces when host accesses data more；If 64, then when host access data, not more access backward
32 bit spaces.
Specifically, the on piece equipment simulating step includes:
Functional simulation step: carrying out the emulation of basic function module, and the emulation of the basic function module includes: at interruption
It manages any one of device, Abort Timer timer, interruption house dog watchdog or appoints a variety of；
Communication simulation step: the emulation of periphery communication function module, the simulation package of the periphery communication function module are carried out
It includes: to any one of peripheral equipment QADC, DMA, EPORT, I2C, SCI, SPI, PIT or appointing a variety of carry out full simulations,
The full simulation includes: the register analog of each communication function module, memory simulation and internal logic simulation, is realized each
Then the memory space of a module and the access interface of register realize the logic that access is caused every time, complete simulation.
The analogue system of processor C8000 provided by the invention, the processor C8000's that can be given through the invention is imitative
The step process of true method is realized.The emulation mode of the processor C8000 can be interpreted as institute by those skilled in the art
State a preference of the analogue system of processor C8000.
The analogue system of a kind of processor C8000 of offer pair according to the present invention, comprising:
Mechanism simulation module: the operating mechanism of simulation C8000 processor；
Register and memory analog module: the register and memory of simulation C8000 processor；
On piece equipment simulating module: the on piece equipment of C8000 is simulated.
Specifically, the mechanism simulation module any one of comprises the following modules or appoints multinomial:
Instruction translation module: compiled machine code is subjected to dynamic translation, translates into the instruction set of host's machine platform；
Time control module: one C8000 of every execution instructs the instruction of corresponding host's machine platform, and time counting adds one,
It checks event buffer, judges in event buffer with the presence or absence of event to be treated: if it exists, then interrupting holding for instruction
Row process handles event to be treated；Otherwise, then instruction is continued to execute；
Memory management module: the correspondence of its virtual address and actual address is realized using HASH algorithm；
Running simulation module: to processor carry out operation control simulation, it is described operation control simulation include: extract,
Any one of decoding, execution, written-back operation are appointed a variety of.
Specifically, the register and memory analog module includes:
Register analog module: register analog space is set on host, is realized by the way of shadow register
Register reads and writees, and judges the execution of an execution under the influence of the change whether of actual registers: if so, will post
It is synchronous with shadow register that storage simulates space；Otherwise, then register analog space is not synchronized with shadow register；
Memory analog module: simulating memory, judges that host is 32 or 64: if 32, then
It is backward to access 32 bit spaces when host accesses data more；If 64, then when host access data, not more access backward
32 bit spaces.
Specifically, the on piece equipment simulating module includes:
Functional simulation module: carrying out the emulation of basic function module, and the emulation of the basic function module includes: at interruption
It manages any one of device, Abort Timer timer, interruption house dog watchdog or appoints a variety of；
Communication simulation module: the emulation of communication function module is carried out, the emulation of the communication function module includes: to periphery
Any one of equipment QADC, DMA, EPORT, I2C, SCI, SPI, PIT appoint a variety of carry out full simulations, the complete mould
Quasi- includes: register analog, memory simulation and the internal logic simulation of each communication function module, realizes depositing for modules
The access interface in space and register is stored up, the logic that access is caused every time is then realized, completes simulation.
A kind of computer readable storage medium for being stored with computer program provided according to the present invention, the computer journey
The step of emulation mode of processor C8000 described in any of the above embodiments is realized when sequence is executed by processor.
Below by preference, the present invention is more specifically illustrated.
Embodiment 1:
This method includes the following steps:
The simulation of step 1:C8000 processor operating mechanism；
The simulation of step 2:C8000 processor register and memory；
The simulation of step 3:C8000 on piece equipment；
Wherein, step 1 includes following functional module:
Module 1.1: compiled machine code is carried out dynamic translation, translates into host's machine platform by the translation of instruction set
Instruction；
Module 1.2: time control, using independent time control module, simulation time piece and physical time piece are not done sternly
Lattice are corresponding；One C8000 of every execution instructs the instruction of corresponding host's machine platform, and time counting adds one；Create event schema
Realize interruption and the control of cyclic behaviour, event schema is to realize that execution thread is every by an event buffer
Executed one instruction after will check event buffer, see with the presence or absence of event to be treated, if it does, just beat
The execution process that severed finger enables, place to go director's part, conversely, continuing to execute instruction.
Module 1.3: memory management, since its address bus is 36, so there is C8000 complicated MMU to control function
Can, according to the characteristics of MMU we the correspondence of its virtual address and actual address realized using HASH algorithm, to realize multiple
Miscellaneous degree is the inside reading speed of O (1).
Module 1.4: the simulation of processor operation control: operation control module including extraction, decoding, is executed, is write back
Step.
Step 2 includes the following steps:
Step 2.1: simulation of the block space for register is opened up in the simulation of processor register on host, by
In reading and writing very frequently for register；We take the mode of shadow register to realize that it quickly reads and write
Enter, again synchronizes the block space and shadow register opened up on host on necessary opportunity, actual registers
When changing the execution for having no effect on next instruction, register will not be synchronized, on the contrary then have to synchronize.
Step 2.2: the simulation of memory, according to the mechanism of C8000, it would be desirable to provide 32 and 64 two kinds of visits
It asks, in order to avoid the host of place 32 is accessing the slow problem of 64 data, we are using 32 bit spaces of automatic more access backward
Mode avoids the problem slow in transmittance process in 64 data.
Step 3 includes the following steps:
The emulation of step 3.1:C8000 basic function module, including interrupt control unit, timer, watchdog etc.；
The emulation of the periphery step 3.2:C8000 communication function module, including QADC, DMA, EPORT, I2C, SCI, SPI,
The full simulation of the peripheral equipments such as PIT, the register analog including each functional module, memory simulation and internal logic mould
It is quasi-；The memory space of modules and the access interface of register are realized first, and what then each access of realization was caused patrols
Volume, to achieve the effect that simulation.
In the description of the present application, it is to be understood that term " on ", "front", "rear", "left", "right", " is erected at "lower"
Directly ", the orientation or positional relationship of the instructions such as "horizontal", "top", "bottom", "inner", "outside" is merely for convenience of description the application
It is described with simplifying, rather than the device or element of indication or suggestion meaning must have a particular orientation, with specific orientation structure
It makes and operates, therefore should not be understood as the limitation to the application.
One skilled in the art will appreciate that in addition to realizing system provided by the invention in a manner of pure computer readable program code
It, completely can be by the way that method and step be carried out programming in logic come so that provided by the invention other than system, device and its modules
System, device and its modules are with logic gate, switch, specific integrated circuit, programmable logic controller (PLC) and embedded
The form of microcontroller etc. realizes identical program.So system provided by the invention, device and its modules can be by
It is considered a kind of hardware component, and the module for realizing various programs for including in it can also be considered as in hardware component
Structure；It can also will be considered as realizing the module of various functions either the software program of implementation method can be again
Structure in hardware component.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow
Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase
Mutually combination.
Claims (9)
1. a kind of emulation mode of processor C8000 characterized by comprising
Mechanism simulation step: the operating mechanism of simulation C8000 processor；
Register and memory simulation steps: the register and memory of simulation C8000 processor；
On piece equipment simulating step: the on piece equipment of C8000 is simulated.
2. the emulation mode of processor C8000 according to claim 1, which is characterized in that the mechanism simulation step packet
It includes any one of following steps or appoints multinomial:
Instruction translation step: compiled machine code is subjected to dynamic translation, translates into the instruction set of host's machine platform；
Time rate-determining steps: one C8000 of every execution instructs the instruction of corresponding host's machine platform, and time counting adds one, checks
Event buffer judges in event buffer with the presence or absence of event to be treated: if it exists, then interrupting the execution stream of instruction
Journey handles event to be treated, exports time counting；Otherwise, then instruction is continued to execute, time counting is exported；
Memory management step: the correspondence of its virtual address and actual address is realized using HASH algorithm；
Running simulation step: to processor carry out operation control simulation, it is described operation control simulation include: extraction, decoding,
Any one of execution, written-back operation are appointed a variety of.
3. the emulation mode of processor C8000 according to claim 1, which is characterized in that the register and memory
Simulation steps include:
Register analog step: register analog space is set on host, deposit is realized by the way of shadow register
Device reads and writees, and judges the execution of an execution under the influence of the change whether of actual registers: if so, by register mould
Quasi- space is synchronous with shadow register；Otherwise, then register analog space is not synchronized with shadow register；
Memory simulation steps: simulating memory, judges that host is 32 or 64: if 32, then host
It is backward to access 32 bit spaces when machine accesses data more；If 64, then when host access data, not more access 32 backward
Space.
4. the emulation mode of processor C8000 according to claim 1, which is characterized in that the on piece equipment simulating step
Suddenly include:
Functional simulation step: carrying out the emulation of basic function module, and the emulation of the basic function module includes: interrupt processing
Any one of device, Abort Timer timer, interruption house dog watchdog appoint a variety of；
Communication simulation step: the emulation of periphery communication function module is carried out, the emulation of the periphery communication function module includes: pair
Any one of peripheral equipment QADC, DMA, EPORT, I2C, SCI, SPI, PIT appoint a variety of carry out full simulations, described complete
Simulation includes: the register analog of each communication function module, memory simulation and internal logic simulation, realizes depositing for modules
The access interface in space and register is stored up, the logic that access is caused every time is then realized, completes simulation.
5. a kind of analogue system of processor C8000 characterized by comprising
Mechanism simulation module: the operating mechanism of simulation C8000 processor；
Register and memory analog module: the register and memory of simulation C8000 processor；
On piece equipment simulating module: the on piece equipment of C8000 is simulated.
6. the analogue system of processor C8000 according to claim 5, which is characterized in that the mechanism simulation module packet
It includes with any one of lower module or appoints multinomial:
Instruction translation module: compiled machine code is subjected to dynamic translation, translates into the instruction set of host's machine platform；
Time control module: one C8000 of every execution instructs the instruction of corresponding host's machine platform, and time counting adds one, checks
Event buffer judges in event buffer with the presence or absence of event to be treated: if it exists, then interrupting the execution stream of instruction
Journey handles event to be treated；Otherwise, then instruction is continued to execute；
Memory management module: the correspondence of its virtual address and actual address is realized using HASH algorithm；
Running simulation module: to processor carry out operation control simulation, it is described operation control simulation include: extraction, decoding,
Any one of execution, written-back operation are appointed a variety of.
7. the analogue system of processor C8000 according to claim 5, which is characterized in that the register and memory
Analog module includes:
Register analog module: register analog space is set on host, deposit is realized by the way of shadow register
Device reads and writees, and judges the execution of an execution under the influence of the change whether of actual registers: if so, by register mould
Quasi- space is synchronous with shadow register；Otherwise, then register analog space is not synchronized with shadow register；
Memory analog module: simulating memory, judges that host is 32 or 64: if 32, then host
It is backward to access 32 bit spaces when machine accesses data more；If 64, then when host access data, not more access 32 backward
Space.
8. the analogue system of processor C8000 according to claim 5, which is characterized in that the on piece equipment simulating mould
Block includes:
Functional simulation module: carrying out the emulation of basic function module, and the emulation of the basic function module includes: interrupt processing
Any one of device, Abort Timer timer, interruption house dog watchdog appoint a variety of；
Communication simulation module: the emulation of communication function module is carried out, the emulation of the communication function module includes: to peripheral equipment
Any one of QADC, DMA, EPORT, I2C, SCI, SPI, PIT appoint a variety of carry out full simulations, the full simulation packet
Include: the memory space of modules is realized in register analog, memory simulation and the internal logic simulation of each communication function module
With the access interface of register, then realizes the logic that access is caused every time, complete simulation.
9. a kind of computer readable storage medium for being stored with computer program, which is characterized in that the computer program is located
The step of reason device realizes the emulation mode of processor C8000 described in any one of Claims 1-4 when executing.
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| CN116108782A (en) * | 2023-04-14 | 2023-05-12 | 此芯科技(上海)有限公司 | MCU peripheral control register behavior simulation method and related device |
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