CN102184947A - High-voltage semiconductor structure and preparation method thereof - Google Patents
High-voltage semiconductor structure and preparation method thereof Download PDFInfo
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- CN102184947A CN102184947A CN2011100617883A CN201110061788A CN102184947A CN 102184947 A CN102184947 A CN 102184947A CN 2011100617883 A CN2011100617883 A CN 2011100617883A CN 201110061788 A CN201110061788 A CN 201110061788A CN 102184947 A CN102184947 A CN 102184947A
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Abstract
The invention discloses a high-voltage semiconductor structure and a preparation method thereof. The high-voltage semiconductor structure comprises a semiconductor substrate, a dual-layer slope medium layer and metal field plate structures, wherein the dual-layer slope medium layer is arranged on the surface of the semiconductor substrate; and the metal field plate structures are arranged on the surfaces of the semiconductor substrate and the dual-layer slope medium layer. The top layer of the dual-layer slope medium layer is made from a high-dielectric constant dielectric material, so dense electric field lines at the outer boundary of field plates can be reduced, the peak value of the electric-field strength on the surface of a lower semiconductor is reduced, and the voltage endurance capability of the semiconductor structure is improved.
Description
Technical field
The present invention relates to the high-voltage semi-conductor device field, relate in particular to a kind of laterally or the terminal structure of longitudinal high-pressure semiconductor device and preparation method thereof.
Background technology
Along with the continuous research and development of people to the power semiconductor module, turn-off thyristor (Gate Turn-Off Thyristor has appearred on the market, GTO), double diffusion metal-oxide semiconductor fieldeffect transistor (Double-diffused MOSFET, DMOS), insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, multiple power device such as IGBT), its performance is become better and better, and uses also more and more widely.The sales volume of power integrated circuit presents and significantly increases progressively trend year by year, has been penetrated into the numerous areas of industry and consumption market.The performance index of a power device mainly can be passed judgment on from a plurality of angles such as puncture voltage, maximum current, maximum power, conducting resistance, area, speed.At the requirement of different performance index, can select suitable power device.
In order to improve the puncture voltage of device, people generally adopt terminal technology commonly used such as field plate or field limiting ring, perhaps can increase the radius of curvature of PN junction corner by enlarging junction depth, to reduce peak value electric field intensity, perhaps adopt above-mentioned certain several method simultaneously.If adopt the field plate structure that is connected in semiconductor surface, for P type substrate, N
+The semiconductor structure that type is drawn, after introducing field plate, field plate and p type island region surface are coupled, and a part of power line ends at the p type island region surface from field plate, and depletion region is advanced in body.This be equivalent to the transverse p/n junction surface introduced with original P type one side depletion region in the electrical opposite additional charge of space electric charge, the direction of an electric field that the space electric charge causes in the direction of an electric field that is caused by this additional charge and the former depletion region is opposite, thereby reduce the electric field that finishes the surface, improved puncture voltage.But the semiconductor substrate surface below the field plate external boundary is because can there be a spike electric field in the electric field that additional charge causes stack.
Bear big voltage as far as possible for the semiconductor depletion region that makes the field plate below, this regional electric field strength is maintained near the critical electric field.A kind of structure that satisfies above-mentioned requirements is that dielectric layer is done aslope, forms slope metal field plate.General, by form the perishable layer of one deck on the dielectric layer surface, after window is opened in photoetching, utilize the selection ratio of etchant solution, promptly corrode the speed of the speed of top dielectric layer greater than corrosion lower floor, form slope dielectric layer structure, but concrete referenced patent number is CN1181562C, the Chinese patent of CN101752208A.In addition, also can utilize gray-level light lithography (Gray-tone Lithography), form curved surface slope dielectric layer structure, specifically can be with reference to U.S. Pat 2004/0129993A1.Yet the spike electric field of field plate external boundary below still exists.If can cut down this spike, make that the distribution of electric field strength is more even, then can further improve voltage endurance capability.
On the other hand, along with the application of high-k (high-κ) dielectric material in semiconductor applications in recent years is extensive further, people are also more and more to the research of this class material, such as the hafnium oxide that adopts in the gate medium of MOS device, zirconium dioxide etc.In order when etching is as the hafnium oxide of gate medium or zirconium dioxide, to reduce loss to the silicon dioxide of isolated area, must seek a kind of method that higher etching selection ratio is arranged, for example just mentioned the solution that adopts certain proportioning, hafnium oxide or zirconium dioxide are selected than reaching more than 2.5 the wet etching of silicon dioxide at U.S. Pat 2004/0067657A1.
Summary of the invention
The objective of the invention is to propose a kind of peak value size that can relax the intensive electric field line in field plate external boundary place, reduce lower semiconductor surface field intensity, improve the high-voltage semi-conductor structure with slope field plate of the voltage endurance capability of semiconductor structure.
For achieving the above object, the invention provides a kind of high-voltage semi-conductor structure, comprise: Semiconductor substrate is arranged at the double-deck slope dielectric layer of described semiconductor substrate surface, and is arranged at the slope metal field plate structure on described Semiconductor substrate and dielectric layer surface, described double-deck slope; Described double-deck slope dielectric layer comprises the bottom dielectric layer and is positioned at top layer dielectric layer on the bottom dielectric layer, and described top layer dielectric layer is the high dielectric constant material, and the dielectric constant of described top layer dielectric layer is greater than the dielectric constant of bottom dielectric layer.
Further, the material of described bottom dielectric layer is a silicon dioxide.
Further, the material of described top layer dielectric layer is hafnium oxide or zirconium dioxide.
Further, the gradient of described bottom dielectric layer ramp portion is less than the gradient of top layer dielectric layer ramp portion.
The present invention also provides a kind of method that is used to prepare above-mentioned high-voltage semi-conductor structure, comprises the steps:
The Semiconductor substrate of first conduction type is provided, forms the two-layered medium material layer on its surface;
Utilize photoetching process to define the zone of drawing on the described Semiconductor substrate;
The described two-layered medium material of wet etching to expose described semiconductor surface of drawing the zone, and makes the two-layered medium material layer form double-deck slope dielectric layer, and described double-deck slope dielectric layer comprises the bottom dielectric layer and is positioned at top layer dielectric layer on the bottom dielectric layer;
Ion injects the impurity of second conduction type in the described zone of drawing, and carries out annealing process;
Form slope metal field plate structure in described Semiconductor substrate and described double-deck slope dielectric layer body structure surface.
Further, the material of described bottom dielectric layer is a silicon dioxide.
Further, the material of described top layer dielectric layer is hafnium oxide or zirconium dioxide.
Further, in the described two-layered medium material of wet etching step, the etch rate of described bottom dielectric layer is less than the etch rate of its top layer dielectric layer.
Further, described slope metal field plate structure employing evaporation or sputtering method form.
In sum, the preferred a kind of technical scheme of the present invention, in the described two-layered medium material of wet etching, the speed of etching bottom dielectric material is greater than the speed of etching top layer dielectric material.Compare with prior art, the high-k top layer dielectric layer of high-voltage semi-conductor structure of the present invention can relax the intensive electric field line in field plate external boundary place, reduces the peak value size of lower semiconductor surface field intensity, improves the voltage endurance capability of semiconductor structure.In addition, the high-k top layer dielectric layer with ramp structure has continued the bottom slope to a certain extent, has equaled to increase the width on slope, and better having played increases withstand voltage effect.
Description of drawings
Fig. 1 is the preparation method's of one embodiment of the invention mesohigh semiconductor structure the structural representation of each processing step to Fig. 4.
Fig. 5 is the preparation method's of one embodiment of the invention mesohigh semiconductor structure a concise and to the point schematic flow sheet.
Fig. 6 is the semiconductor surface distribution map of the electric field of one embodiment of the invention mesohigh semiconductor structure and traditional slope field plate structure.
Embodiment
For making content of the present invention clear more understandable,, content of the present invention is described further below in conjunction with Figure of description.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Fig. 4 is the generalized section of high-voltage semi-conductor structure of the present invention, please refer to Fig. 4, the invention provides a kind of high-voltage semi-conductor structure comprises: Semiconductor substrate 1, be arranged at the double-deck slope dielectric layer on described Semiconductor substrate 1 surface, and be arranged at the slope metal field plate structure 5 on described Semiconductor substrate 1 and dielectric layer surface, described double-deck slope; Described double-deck slope dielectric layer comprises bottom dielectric layer 2 and is positioned at top layer dielectric layer 3 on the bottom dielectric layer 2 that the dielectric constant of described top layer dielectric layer 3 is greater than the dielectric constant of its bottom dielectric layer 2.Further, the material of described bottom dielectric layer 2 is a silicon dioxide.Described top layer dielectric layer 3 is the high dielectric constant material.For example, the material of described top layer dielectric layer 3 is hafnium oxide or zirconium dioxide.
In the present embodiment, the gradient of described bottom dielectric layer 2 ramp portion is less than the gradient of top layer dielectric layer 3 ramp portion.
Fig. 5 is the preparation method's of one embodiment of the invention mesohigh semiconductor structure a concise and to the point schematic flow sheet.Describe the prepared process of high-voltage semi-conductor structure of the present invention in detail below in conjunction with Fig. 1～Fig. 4 and Fig. 5.Wherein in the present embodiment, be the P type with first conduction type, second conduction type is an example for the N type, the preparation method of described high-voltage semi-conductor structure may further comprise the steps:
S01: the Semiconductor substrate of first conduction type is provided, forms the two-layered medium material layer on its surface; As shown in Figure 1, in the present embodiment, described first conduction type is the P type, and described Semiconductor substrate 1 can be semi-conducting materials such as silicon, germanium, germanium silicon; Form the bottom dielectric layer 2 of two-layered medium material layer earlier on P type semiconductor substrate 1 surface, described bottom dielectric layer 2 can adopt thermal oxidation method or chemical vapor deposited method to form.Wherein preferable, described Semiconductor substrate 1 is silicon materials, the material of described bottom dielectric layer 2 is a silicon dioxide, described silicon dioxide adopts the method for thermal oxidation to form, bottom dielectric layer 2 quality that this method obtains are good, more help increasing and other dielectric materials between the difference of corrosion rate, obtain the slope of proper width; Then, at described bottom dielectric layer 2 surface deposition top layer dielectric layers 3, described top layer dielectric layer 3 is the high dielectric constant material, and is concrete, and described high dielectric constant material can be hafnium oxide or zirconium dioxide.
S02: utilize photoetching process to define the zone of drawing on the described Semiconductor substrate; As shown in Figure 2, utilize the photoetching process definition to draw zone 10, smear photoresist 4 in described two-layered medium material surface, and utilize the mask plate of predetermined pattern that photoresist is exposed 4, and photoresist developed, thereby expose the two-layered medium material layer of drawing zone 10, keep remaining photoresist 4.
S03: the described two-layered medium material layer of wet etching to expose described semiconductor substrate surface of drawing the zone, and makes the two-layered medium material layer form double-deck slope dielectric layer; As shown in Figure 3, utilize described top layer dielectric layer 3 of wet etching and described bottom dielectric layer 2.Because wet etching is an isotropic, so in etching process, draw the zone 10 in the two-layered medium material layer be etched, also can be etched near the side two-layered medium material layer of drawing zone 10 simultaneously, in the present embodiment, bottom dielectric layer 2 is a silicon dioxide, when top layer dielectric layer 3 is the hafnium oxide of high dielectric constant material or zirconium dioxide, wet etching solution to the corrosion rate of hafnium oxide or zirconium dioxide greater than corrosion rate to silicon dioxide, thereby form double-deck slope dielectric layer structure as shown in Figure 3, thereby the gradient on bottom dielectric layer 2 slopes is less than the gradient on top layer dielectric layer 3 slopes.
S04: ion injects the impurity of second conduction type in the described zone of drawing, and carries out annealing process; As shown in Figure 4, in the present embodiment, described second conduction type is the N type, then remove photoresist 4 after, be that mask carries out that ion injects and annealing with described double-deck slope dielectric layer, wherein the ion of Zhu Ruing is phosphonium ion or arsenic ion, thereby forms N in substrate
+The type district.
S05: form slope metal field plate structure 5 in described Semiconductor substrate 1 and described double-deck slope dielectric layer body structure surface.Slope metal field plate structure 5 can adopt evaporation or sputtering method to form, and is wherein preferable, adopts sputtering method deposition layer of metal, and utilizes photoetching, etching technics that metal is carried out etching, the final slope metal field plate structure 5 that forms as shown in Figure 4.
Compare with prior art, the high-k top layer dielectric layer of high-voltage semi-conductor structure of the present invention can relax the intensive electric field line in field plate external boundary place, reduces the peak value size of lower semiconductor surface field intensity, improves the voltage endurance capability of semiconductor structure; In addition, have the slope that the high-k top layer dielectric layer of ramp structure has continued the bottom dielectric layer to a certain extent, equaled to increase the width on slope, better having played increases withstand voltage effect.Fig. 6 is the semiconductor surface distribution map of the electric field of one embodiment of the invention mesohigh semiconductor structure and traditional slope field plate structure.As shown in Figure 6, curve 11 is the semiconductor surface Electric Field Distribution of traditional slope field plate structure, and the semiconductor surface Electric Field Distribution that adopts high-voltage semi-conductor structure of the present invention is a curve 12.As can see from Figure 6, high-voltage semi-conductor structure of the present invention is compared with the semiconductor surface Electric Field Distribution of traditional slope field plate structure, and the spike electric field strength at field plate external boundary place significantly decreases, thereby can effectively improve puncture voltage.
In fact, in the above-described embodiments, hafnium oxide or zirconium dioxide have played multiple effectiveness: at first, in the processing step of preparation high-voltage semi-conductor structure of the present invention, hafnium oxide or zirconium dioxide serve as perishable layer, corrosion rate is greater than the silicon dioxide of bottom, thereby it is less to form the gradient, the bottom slope dielectric layer that width is bigger; Secondly, hafnium oxide or zirconium dioxide itself are exactly one deck slope dielectric layer, can be considered a kind of continuity of bottom layer silicon dioxide slope dielectric layer, although width is less relatively, also can improve Electric Field Distribution to a certain extent; Once more, also be the most important, because hafnium oxide or zirconium dioxide are the insulating medium layers of high-k, its dielectric constant is higher than 3.9 of silicon dioxide far away greater than 20.The existence of dielectric layer of high dielectric constant, make the field plate border strengthen near the coupling of semiconductor surface outside the field plate area of coverage, prevented that electric field line from concentrating on the field plate boundary, reduced the electric field strength of boundary, strengthened the voltage endurance capability of high-voltage semi-conductor structure of the present invention.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the present invention is not limited at the specific embodiment described in the specification.Have in the technical field under any and know the knowledgeable usually, without departing from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (9)
1. a high-voltage semi-conductor structure is characterized in that, comprising: Semiconductor substrate is arranged at the double-deck slope dielectric layer of described semiconductor substrate surface, and is arranged at the slope metal field plate structure on described Semiconductor substrate and dielectric layer surface, described double-deck slope; Described double-deck slope dielectric layer comprises the bottom dielectric layer and is positioned at top layer dielectric layer on the bottom dielectric layer, and described top layer dielectric layer is the high dielectric constant material, and the dielectric constant of described top layer dielectric layer is greater than the dielectric constant of bottom dielectric layer.
2. high-voltage semi-conductor structure as claimed in claim 1 is characterized in that, the material of described bottom dielectric layer is a silicon dioxide.
3. high-voltage semi-conductor structure as claimed in claim 1 is characterized in that, the material of described top layer dielectric layer is hafnium oxide or zirconium dioxide.
4. high-voltage semi-conductor structure as claimed in claim 1 is characterized in that, the gradient of described bottom dielectric layer ramp portion is less than the gradient of top layer dielectric layer ramp portion.
5. a method that is used to prepare high-voltage semi-conductor structure as claimed in claim 1 is characterized in that, comprises the steps:
The Semiconductor substrate of first conduction type is provided, forms the two-layered medium material layer on its surface;
Utilize photoetching process to define the zone of drawing on the described Semiconductor substrate;
The described two-layered medium material of wet etching to expose described semiconductor surface of drawing the zone, and makes the two-layered medium material layer form double-deck slope dielectric layer, and described double-deck slope dielectric layer comprises the bottom dielectric layer and is positioned at top layer dielectric layer on the bottom dielectric layer;
Ion injects the impurity of second conduction type in the described zone of drawing, and carries out annealing process;
Form slope metal field plate structure in described Semiconductor substrate and described double-deck slope dielectric layer body structure surface.
6. high-voltage semi-conductor structure as claimed in claim 5 is characterized in that, the material of described bottom dielectric layer is a silicon dioxide.
7. high-voltage semi-conductor structure as claimed in claim 5 is characterized in that, the material of described top layer dielectric layer is hafnium oxide or zirconium dioxide.
8. the method for preparing the high-voltage semi-conductor structure as claimed in claim 5 is characterized in that, in the described two-layered medium material of wet etching step, the etch rate of described bottom dielectric layer is less than the etch rate of top layer dielectric layer.
9. the method for preparing the high-voltage semi-conductor structure as claimed in claim 5 is characterized in that, described slope metal field plate structure adopts evaporation or sputtering method to form.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165450A (en) * | 2011-12-09 | 2013-06-19 | 上海华虹Nec电子有限公司 | Manufacturing method of terminal ring |
| CN104094408A (en) * | 2011-12-06 | 2014-10-08 | Hrl实验室有限责任公司 | High current high voltage GaN field effect transistors and method of fabricating same |
| CN104576345A (en) * | 2013-10-29 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Preparation method of slope field plate structure in power device |
| CN104094408B (en) * | 2011-12-06 | 2016-11-30 | Hrl实验室有限责任公司 | High current high voltage GaN field-effect transistor and manufacture method thereof |
| US9812532B1 (en) | 2015-08-28 | 2017-11-07 | Hrl Laboratories, Llc | III-nitride P-channel transistor |
| CN107910379A (en) * | 2017-11-22 | 2018-04-13 | 北京燕东微电子有限公司 | A kind of SiC junction barrel Schottky diode and preparation method thereof |
| CN107968126A (en) * | 2017-11-22 | 2018-04-27 | 北京燕东微电子有限公司 | A kind of SiC Schottky diode and preparation method thereof |
| US10276712B2 (en) | 2014-05-29 | 2019-04-30 | Hrl Laboratories, Llc | III-nitride field-effect transistor with dual gates |
| US10692984B2 (en) | 2015-11-19 | 2020-06-23 | Hrl Laboratories, Llc | III-nitride field-effect transistor with dual gates |
| CN113314405A (en) * | 2021-05-26 | 2021-08-27 | 四川上特科技有限公司 | Method for manufacturing semiconductor power device slope field plate |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104094408A (en) * | 2011-12-06 | 2014-10-08 | Hrl实验室有限责任公司 | High current high voltage GaN field effect transistors and method of fabricating same |
| CN104094408B (en) * | 2011-12-06 | 2016-11-30 | Hrl实验室有限责任公司 | High current high voltage GaN field-effect transistor and manufacture method thereof |
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| US10276712B2 (en) | 2014-05-29 | 2019-04-30 | Hrl Laboratories, Llc | III-nitride field-effect transistor with dual gates |
| US9812532B1 (en) | 2015-08-28 | 2017-11-07 | Hrl Laboratories, Llc | III-nitride P-channel transistor |
| US10692984B2 (en) | 2015-11-19 | 2020-06-23 | Hrl Laboratories, Llc | III-nitride field-effect transistor with dual gates |
| CN107910379A (en) * | 2017-11-22 | 2018-04-13 | 北京燕东微电子有限公司 | A kind of SiC junction barrel Schottky diode and preparation method thereof |
| CN107968126A (en) * | 2017-11-22 | 2018-04-27 | 北京燕东微电子有限公司 | A kind of SiC Schottky diode and preparation method thereof |
| CN113314405A (en) * | 2021-05-26 | 2021-08-27 | 四川上特科技有限公司 | Method for manufacturing semiconductor power device slope field plate |
| CN113314405B (en) * | 2021-05-26 | 2022-07-26 | 四川上特科技有限公司 | Method for manufacturing semiconductor power device slope field plate |
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Application publication date: 20110914 |