CN113314405B - Method for manufacturing semiconductor power device slope field plate - Google Patents
Method for manufacturing semiconductor power device slope field plate Download PDFInfo
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- CN113314405B CN113314405B CN202110579844.6A CN202110579844A CN113314405B CN 113314405 B CN113314405 B CN 113314405B CN 202110579844 A CN202110579844 A CN 202110579844A CN 113314405 B CN113314405 B CN 113314405B
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000001259 photo etching Methods 0.000 claims abstract description 42
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052804 chromium Inorganic materials 0.000 claims abstract description 35
- 239000011651 chromium Substances 0.000 claims abstract description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- 238000001465 metallisation Methods 0.000 claims abstract description 5
- 238000001020 plasma etching Methods 0.000 claims abstract description 4
- 238000002834 transmittance Methods 0.000 claims description 16
- 238000000206 photolithography Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 5
- CLOMYZFHNHFSIQ-UHFFFAOYSA-N clonixin Chemical compound CC1=C(Cl)C=CC=C1NC1=NC=CC=C1C(O)=O CLOMYZFHNHFSIQ-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention discloses a method for manufacturing a semiconductor power device slope field plate, which comprises the steps of firstly, designing two gray scale photoetching plates corresponding to a slope region, then arranging uniform grids with the size smaller than photoetching resolution in the gray scale region of each photoetching plate, and opening holes in each grid on a chromium layer to manufacture a gray scale photoetching plate; and then, exposing the photoresist twice by taking the two gray scale photomasks as a mask, developing to generate a slope photoresist, performing plasma dry etching by taking the slope photoresist as the mask, and finally performing metal deposition and reactive ion etching to obtain the slope field plate. The method provided by the invention simplifies the process steps, reduces the process difficulty and cost, realizes the manufacture of the slope field plate by using fewer process steps and cost, and increases the selection of the range and the gradient of the slope field plate by double exposure compared with one-time exposure. The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and is used for manufacturing a slope field plate.
Description
Technical Field
The invention belongs to the technical field of semiconductor processes, relates to a junction terminal preparation method for improving the withstand voltage of a semiconductor power device, and particularly relates to a manufacturing method of a semiconductor power device slope field plate.
Background
In the technical field of semiconductor device preparation, a field plate is one of the commonly used methods in the junction termination technology, and the field plate is mainly used for increasing the curvature radius of a curvature junction and preventing a surface electric field from being too concentrated by changing the surface potential distribution of a device, so that the withstand voltage of the device is improved.
A conventional field plate is a biased field plate as shown in fig. 1a, which is formed by the contact metal of the N + pole extending over the N + P junction, and thus has the same potential as the N + pole. The field plate, the lower oxide layer and the silicon substrate form an MOS structure. When a reverse bias voltage is applied to the N + P junction, the surface of the silicon substrate of the field plate MOS structure is depleted, so that the area of a depletion region is expanded, the curvature radius of the depletion region is increased, and the withstand voltage is improved. After the offset field plate is adopted, the electric field of the silicon substrate under the field plate is reduced and distributed uniformly, but the electric lines at the edge of the field plate are concentrated to form a high peak electric field, which easily causes the breakdown at the edge of the field plate.
According to simulation results, it is found that the transverse electric field of the field plate is approximately exponentially attenuated along with the end point of the off-field plate, and in order to overcome the defect of breakdown caused by electric field concentration at the edge of the bias field plate, a slope field plate as shown in fig. 1b is proposed. As the field plate extends leftwards, the thickness of the oxide layer is gradually increased, so that a high electric field peak value cannot be formed at the edge of the slope field plate, and the edge breakdown of the field plate is avoided. The proposal of the slope field plate concept can effectively reduce the peak electric field of the PN junction in theory and can also avoid edge breakdown caused by the concentration of the electric field at the edge of the field plate, but the realization of the process is very difficult.
At present, a multi-step field plate shown in fig. 1c is generally adopted to simulate an oblique field plate effect, but the multi-step field plate needs more layout and metallization steps, and the process complexity and the process cost are increased. FIG. 2 is a schematic diagram of a gray scale lithography principle in the prior art.
Disclosure of Invention
The invention aims to provide a method for manufacturing a slope field plate of a semiconductor power device, which is based on gray scale photoetching plate design, converts a slope into light transmittance change of two gray scale photoetching plates, simplifies process steps, reduces process difficulty and cost, realizes the manufacture of the slope field plate by using fewer process steps and cost, and increases the range and gradient selection of the slope field plate compared with one-time exposure and double exposure.
In order to achieve the purpose, the invention adopts the following technical scheme:
a manufacturing method of a semiconductor power device slope field plate is carried out according to the following steps:
first, make the gray scale photolithography mask
First, a first gray scale photolithography plate is manufactured
Dividing a region corresponding to the slope field plate on a first photoetching plate into n grids with uniform areas of S, and then opening a chromium layer at the center of each grid to obtain a first gray photoetching plate;
for the mth grid on the first gray scale photoetching plate, the area of the openings of the chromium layer is S m Light transmittance of a thereof 1m =S m /S；
Second Gray level photolithography
Dividing a region corresponding to the slope field plate on a second photoetching plate into n grids with uniform areas of S, and then opening a hole in the center of each grid to obtain a second gray photoetching plate;
for the mth grid on the second gray scale reticle, the area of the openings of the chromium layer is T m Light transmittance of a thereof 2m =T m /S；
N is more than or equal to 1, and m belongs to [1, n ];
two and two exposures
Firstly, taking a first gray scale photoetching plate as a mask to carry out first exposure on photoresist on a semiconductor device substrate with a surface growing dielectric layer;
during the first exposure, the exposure dose of the mth grid is d 1m ；
Then, the second gray scale reticle is used as a mask pairExposing the photoresist after the first exposure for the second time with exposure dose d 2m Then developing to obtain the slope photoresist;
during the second exposure, the exposure dose of the m-th grid is d 2m ；
Step one and step two satisfy D m = d 1m *S m /S+d 2m *T m S, wherein D m The total exposure amount of the photoresist area corresponding to the mth grid;
third, plasma dry etching
Performing plasma dry etching on the dielectric layer by taking the slope photoresist as a mask to enable the etching ratio of the dielectric layer to the slope photoresist to be 1:1, and obtaining a slope-shaped dielectric layer;
fourthly, manufacturing the slope field plate
SiO in a slope shape 2 And performing metal deposition and reactive ion etching to obtain the slope field plate.
As a limitation, the slope field plate is a slope field plate with a one-dimensional transverse structure;
in the first step, n grids are square grids with side length of A, and S = A 2 ；
In the mth grid, the chromium layer is provided with a side length of B m Square hole of (S) m =B m 2 ；
In the second step, in the mth grid, the chromium layer is provided with a side length of C m Square hole of (1), T m =C m 2 。
As a second limitation, the slope field plate is a slope field plate with a one-dimensional transverse structure;
in the first step, n grids are square grids with side length of A, and S = A 2 ；
In the mth grid, the chromium layer is provided with k square holes with the side length of e, and S m =k*e 2 Wherein k is more than or equal to 1;
in the second step, in the mth grid, the chromium layer is provided with j square holes with the side length of e, T m =j*e 2 In which，j≥1。
As a third limitation: the slope field plate is of an arc runway-shaped structure;
in the first step, n arc-shaped grid stripes with uniformly changed radius delta R are divided along the direction of slope change,
in the mth grid, the chromium layer is subjected to radius variation delta r at the center of the grid 1m A circular arc-shaped opening of 1m =△r 1m /△R；
In the second step, in the mth grid, the chromium layer is subjected to radius variation delta r at the center of the grid 2m A circular arc-shaped opening of 2m =△r 2m /△R。
Due to the adoption of the technical scheme, compared with the prior art, the invention has the technical progress that:
(1) the slope is converted into the light transmittance change of two gray scale photomasks by converting the slope into the reserved thickness after development and then converting the slope into the light transmittance change of the two gray scale photomasks according to the relation between the reserved thickness and the exposure intensity; making corresponding openings of the chromium layer of the photoetching plate through the change of the calculated light transmittance, wherein the light transmittance is the ratio of the light transmittance area in the grid to the grid area; the photoetching plate is used for photoetching flow, so that the process steps are simplified, the process difficulty and the cost are reduced, and the slope field plate is manufactured by using fewer process steps and less cost;
(2) compared with one-time exposure, the double-exposure method increases the selection of the range and the gradient of the slope field plate;
(3) the process of the invention is compatible with the existing process.
The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and is used for manufacturing a slope field plate.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
In the drawings:
fig. 1a is a schematic diagram of a general bias field plate structure in the prior art;
FIG. 1b is a schematic diagram of a ramp field plate structure according to the prior art;
FIG. 1c is a schematic diagram of a stepped field plate structure in the prior art according to the present invention;
FIG. 2 is a schematic diagram of a gray scale photolithography technique according to the prior art;
FIG. 3a is a schematic view of an opening in the gray scale region of a reticle in embodiment 1 of the present invention;
FIG. 3b is a schematic view of an opening in the gray scale region of a reticle in embodiment 2 of the present invention;
FIG. 4 is a schematic view of an opening in the gray scale region of a reticle according to embodiment 3 of the present invention;
FIG. 5 is a partial process flow diagram of example 1 of the present invention;
FIG. 6 is a graph comparing single exposure and double exposure for the same total dose in example 4 of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only for illustrating and explaining the present invention and are not to be considered as limiting the present invention.
Embodiment 1a method for manufacturing a semiconductor power device ramp field plate
The slope field plate in the embodiment is a slope field plate with a one-dimensional transverse structure.
This example was carried out in the following sequence of steps:
first, make the gray scale photolithography mask
In the step, two gray scale photoetching plates need to be manufactured; for convenience of description, the embodiment is described by taking the reticle shown in fig. 3 as an example;
making the first gray scale photoetching plate
Dividing a region corresponding to the slope field plate on a first photoetching plate into n uniform square grids with the side length of A, and then opening a hole in the center of each grid to obtain a first gray photoetching plate, wherein the area of each grid is S = A 2 ；
As in fig. 3a, for the mth grid on the first gray scale reticle,the chromium layer has an opening side length of B m Square hole of chromium layer with an open area of S m =B m 2 Light transmittance of a thereof 1m =S m /S；
Second Gray photolithography
The second photoetching plate is the same as the first photoetching plate;
firstly, according to the same method as the first step, dividing a region corresponding to a slope field plate on a second photoetching plate into n uniform square grids with the side length of A, then opening a hole in the center of each grid for a chromium layer to prepare a second gray photoetching plate, wherein the area of each grid is S = A 2 ；
For the mth grid on the second gray scale photoetching plate, the side length of the chromium layer is set to be C m Square hole of chromium layer with an opening area of T m =C m 2 Light transmittance of a thereof 2m =T m /S；
In the first step and the second step, n is more than or equal to 1, and m belongs to [1, n ];
two and two exposures
As shown in FIG. 5, first, SiO grown on the surface of the semiconductor device is masked with a first gray-scale reticle 2 Exposing the photoresist on the dielectric layer for the first time;
during the first exposure, the exposure dose of the m-th grid is d 1m ；
Then, taking a second gray scale photoetching plate as a mask to carry out second exposure on the photoresist after the first exposure, and then developing to obtain a slope photoresist;
during the second exposure, the exposure dose of the m-th grid is d 2m ；
Step one and step two satisfy D m = d 1m *S m /S+d 2m *T m S, wherein D m The total exposure amount of the photoresist area corresponding to the mth grid;
third, plasma dry etching
Using slope photoresist as mask to SiO 2 The dielectric layer is etched by plasma dry method to make SiO 2 Dielectric layer and slope photoresistThe etching ratio of (2) is 1:1, and the SiO with the slope shape is obtained 2 A dielectric layer;
fourthly, manufacturing the slope field plate
SiO in the shape of a slope 2 And carrying out metal deposition and reactive ion etching on the dielectric layer to obtain the slope field plate.
In this embodiment, the side length a of the grid divided on the first reticle and the second reticle is smaller than the resolution of the lithography machine, for example, for an ultraviolet i-line lithography machine, the resolution is higher than 380nm, and the side length a of the square grid needs to be smaller than 380 nm.
For realizing a slope field plate, a photoetching plate with linear gray change is required to be obtained, and for a one-dimensional transverse slope field plate, the realization method comprises the following steps: and obtaining corresponding minimum and maximum light transmittance according to the range of the linear relation between the exposure depth and the dosage of the received ultraviolet light and the maximum thickness and the minimum thickness reserved after the positive photoresist is developed.
Embodiment 2 method for manufacturing semiconductor power device slope field plate
The slope field plate in the embodiment is a slope field plate with a one-dimensional transverse structure.
The process flow of the present example is substantially the same as that of example 1, except that: in the embodiment 1, each grid is provided with a square hole; in this embodiment, the change in light transmittance is changed to the change in the number of light-transmissive open areas inside the grid.
The steps of fabricating the first gray scale reticle and the second gray scale reticle in this embodiment are as follows:
in the step, two gray scale photolithography plates are required to be manufactured; for convenience of description, the embodiment is described by taking the reticle of fig. 3b as an example;
a1, making the first gray scale photoetching plate
Firstly, a region corresponding to a slope field plate on a first photoetching plate is divided into n uniform square grids with the side length of A, and S = A 2 ；
Then, opening a hole in the chromium layer at the center of each grid to obtain a first gray scale photoetching plate;
taking the m-th grid as an example, the chromium layer is provided with k square holes with the side length of e，S m =k*e 2 Wherein k is more than or equal to 1;
a2, making a second gray scale plate
Firstly, a region corresponding to the slope field plate on the second photoetching plate is divided into n uniform square grids with the side length of A, and S = A 2 ；
Then, opening a hole in the chromium layer at the center of each grid to prepare a second gray scale plate;
taking the m-th grid as an example, the chromium layer is provided with j square holes with the side length of e, T m =j*e 2 Wherein j is more than or equal to 1.
In the steps A1 and A2, n is more than or equal to 1, and m belongs to [1, n ].
Embodiment 3 method for manufacturing semiconductor power device slope field plate
The process flow of the embodiment is substantially the same as that of the embodiment 1, except that the slope field plate of the embodiment is a slope field plate with an arc runway-shaped structure; the way in which the chromium layer is perforated is also different.
The steps of fabricating the first gray scale reticle and the second gray scale reticle in this embodiment are as follows:
in the step, two gray scale photolithography plates are required to be manufactured; for convenience of description, the embodiment is described by taking the reticle shown in fig. 4 as an example;
b1, making a first gray scale reticle
Firstly, dividing n circular-arc stripe grids with uniformly changed deltaR radius along the direction of slope change on a first photoetching plate;
then, opening a hole in the chromium layer at the center of each grid to obtain a first gray scale photoetching plate;
taking the m-th grid as an example, the chromium layer is subjected to the radius variation delta r at the center of the grid 1m Circular arc-shaped opening of (2), it is apparent that the light transmittance is a 1m =△r 1m /△R；
B2, making a second gray scale plate
Firstly, on a second photoetching plate; dividing n circular arc grid stripes with uniformly changed radius delta R along the direction of slope change in the same way as the step B1;
then, opening a hole in the chromium layer at the center of each grid to prepare a second gray scale plate;
taking the m-th grid as an example, the chromium layer is subjected to the radius change quantity Deltar at the center of the grid 2m Has a circular arc-shaped opening, and has a light transmittance of a 2m =△r 2m /△R。
In steps B1 and B2, n is more than or equal to 1, and m belongs to [1, n ].
As to embodiments 1 to 3, fig. 3 and fig. 4 only show schematic diagrams of manufacturing the first gray scale reticle, and it can be seen from the text description that, in fact, for a specific embodiment, the method of dividing the grid when manufacturing the second gray scale reticle is completely the same as the method of dividing the grid when manufacturing the first gray scale reticle, but in order to meet the requirement of the total exposure dose of the first gray scale reticle and the second gray scale reticle, the area of the opening of the chrome layer in a specific grid is different, and the size of the grid is smaller than the photolithography resolution.
Example 4 Single and double Exposure comparison for equal Total dose
Double exposure means that after a wafer is coated with photoresist, two exposures are performed on the same photoresist using different reticles. Although double exposure uses multiple adjacent exposures, each step being applied to the unexposed photoresist, it is also feasible to superimpose two partial exposures to produce a gray scale level that cannot be achieved with one exposure. As shown in fig. 6, for a single exposure and a double exposure with the same total dose, at a certain exposure dose, even if a double exposure is used, the division of the total dose into two amounts has no effect on the final exposure depth.
The exposure dose is the product of the intensity of light I and the exposure time t, the double exposure dose d de Defined as the sum of the individual doses per exposure, so the total exposure dose can be written as d de =I 1 t 1 +I 2 t 2 And the exposure depth and dose are d de The depth of one exposure is the same. Because the photoresist formed after one exposure and development is limited in length slope of the non-uniform part of the photoresist thickness under a certain processing precision, the double exposure method provided in embodiments 1-4 can be used to increaseThe range thereof.
Claims (4)
1. A method for manufacturing a semiconductor power device slope field plate is characterized by comprising the following steps:
first, make the gray scale photolithography mask
First, a first gray scale photolithography plate is manufactured
Dividing a region corresponding to the slope field plate on a first photoetching plate into n grids with uniform areas of S, and then opening a chromium layer at the center of each grid to obtain a first gray photoetching plate;
for the mth grid on the first gray scale photoetching plate, the area of the openings of the chromium layer is S m Transmittance of a thereof 1m =S m /S；
Second Gray level photolithography
Dividing a region corresponding to the slope field plate on a second photoetching plate into n grids with uniform areas of S, and then opening a chromium layer at the center of each grid to obtain a second gray photoetching plate;
for the mth grid on the second gray scale reticle, the area of the openings of the chromium layer is T m Light transmittance of a thereof 2m =T m /S；
N is more than or equal to 1, and m belongs to [1, n ];
the side length or the size of the grids divided on the first photoetching plate and the second photoetching plate is smaller than the resolution of the photoetching machine;
two and two exposures
Firstly, taking a first gray scale photoetching plate as a mask to carry out first exposure on photoresist on a semiconductor device substrate with a surface growth dielectric layer;
during the first exposure, the exposure dose of the m-th grid is d 1m ；
Then, taking the second gray scale reticle as a mask to carry out the second exposure on the photoresist after the first exposure, wherein the exposure dose is d 2m Then developing to obtain the slope photoresist;
during the second exposure, the exposure dose of the m-th grid is d 2m ；
Step one and stepStep two satisfies D m = d 1m *S m /S+d 2m *T m S, wherein D m The total exposure amount of the photoresist area corresponding to the mth grid is calculated;
third, plasma dry etching
Performing plasma dry etching on the dielectric layer by taking the slope photoresist as a mask to enable the etching ratio of the dielectric layer to the slope photoresist to be 1:1, and obtaining a slope-shaped dielectric layer;
fourthly, manufacturing a slope field plate
And carrying out metal deposition and reactive ion etching on the slope-shaped dielectric layer to obtain the slope field plate.
2. The method for manufacturing the semiconductor power device ramp field plate according to claim 1, wherein the ramp field plate is a one-dimensional lateral structure ramp field plate;
in the first step, n grids are square grids with side length of A, and S = A 2 ；
In the mth grid, the chromium layer is provided with a side length of B m Square hole of (S) m =B m 2 ；
In the mth grid, the chromium layer is provided with a side length of C m Square hole of (a), T m =C m 2 。
3. The method of claim 1, wherein the sloped field plate is a one-dimensional lateral structure;
in the first step, the n grids are square grids with the side length of A, and S = A 2 ；
In the mth grid, the chromium layer is provided with k square holes with the side length of e, and S m =k*e 2 Wherein k is more than or equal to 1;
in the mth grid, the chromium layer is provided with j square holes with the side length of e and T m =j*e 2 Wherein j is more than or equal to 1.
4. The method for manufacturing the semiconductor power device ramp field plate according to claim 1, wherein: the slope field plate is a slope field plate with an arc runway-shaped structure;
in the first step, n arc grid stripes with uniformly changed deltaR radius are divided along the direction of slope change,
in the mth grid, the chromium layer is subjected to radius variation delta r at the center of the grid 1m Circular arc-shaped opening of (a) 1m =△r 1m /△R；
Step two, in the mth grid, the chromium layer is subjected to radius variation delta r at the center of the grid 2m Circular arc-shaped opening of (a) 2m =△r 2m /△R。
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0237844A1 (en) * | 1986-03-18 | 1987-09-23 | BBC Brown Boveri AG | Process for manufacturing a passivation layer for the semiconductor technique, and use of this layer |
| CN101752208A (en) * | 2008-12-03 | 2010-06-23 | 上海芯能电子科技有限公司 | Semiconductor high-voltage terminal structure and production method thereof |
| CN102184947A (en) * | 2011-03-15 | 2011-09-14 | 上海集成电路研发中心有限公司 | High-voltage semiconductor structure and preparation method thereof |
| CN103022097A (en) * | 2012-12-28 | 2013-04-03 | 上海集成电路研发中心有限公司 | Grooved gate power device and manufacturing method thereof |
| US8980759B1 (en) * | 2014-05-22 | 2015-03-17 | Hrl Laboratories, Llc | Method of fabricating slanted field-plate GaN heterojunction field-effect transistor |
| CN104576345A (en) * | 2013-10-29 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Preparation method of slope field plate structure in power device |
| WO2016033977A1 (en) * | 2014-09-01 | 2016-03-10 | 苏州捷芯威半导体有限公司 | Inclined field plate power device and method for fabricating the inclined field plate power device |
| JP2018129537A (en) * | 2018-04-16 | 2018-08-16 | 三菱電機株式会社 | Semiconductor device and method of manufacturing the same |
| CN209055800U (en) * | 2018-11-21 | 2019-07-02 | 北京燕东微电子有限公司 | A kind of lithography mask version and SiC junction termination structures |
| CN111463266A (en) * | 2020-04-13 | 2020-07-28 | 河北工业大学 | Inverted trapezoidal gate MOSFET device structure with inclined sidewall field plate |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005276914A (en) * | 2004-03-23 | 2005-10-06 | Seiko Epson Corp | Semiconductor device and method of manufacturing same |
| KR100649867B1 (en) * | 2005-12-14 | 2006-11-27 | 동부일렉트로닉스 주식회사 | High voltage semiconductor device and method of fabricating the same |
| US8390000B2 (en) * | 2009-08-28 | 2013-03-05 | Transphorm Inc. | Semiconductor devices with field plates |
| CN105164811B (en) * | 2013-02-15 | 2018-08-31 | 创世舫电子有限公司 | Electrode of semiconductor devices and forming method thereof |
| US9142626B1 (en) * | 2013-04-23 | 2015-09-22 | Hrl Laboratories, Llc | Stepped field plate wide bandgap field-effect transistor and method |
| US10276669B2 (en) * | 2017-01-19 | 2019-04-30 | Infineon Technologies Austria Ag | Sloped field plate and contact structures for semiconductor devices and methods of manufacturing thereof |
| CN207381407U (en) * | 2017-11-22 | 2018-05-18 | 北京燕东微电子有限公司 | A kind of SiC Schottky diode |
| CN107968126A (en) * | 2017-11-22 | 2018-04-27 | 北京燕东微电子有限公司 | A kind of SiC Schottky diode and preparation method thereof |
-
2021
- 2021-05-26 CN CN202110579844.6A patent/CN113314405B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0237844A1 (en) * | 1986-03-18 | 1987-09-23 | BBC Brown Boveri AG | Process for manufacturing a passivation layer for the semiconductor technique, and use of this layer |
| CN101752208A (en) * | 2008-12-03 | 2010-06-23 | 上海芯能电子科技有限公司 | Semiconductor high-voltage terminal structure and production method thereof |
| CN102184947A (en) * | 2011-03-15 | 2011-09-14 | 上海集成电路研发中心有限公司 | High-voltage semiconductor structure and preparation method thereof |
| CN103022097A (en) * | 2012-12-28 | 2013-04-03 | 上海集成电路研发中心有限公司 | Grooved gate power device and manufacturing method thereof |
| CN104576345A (en) * | 2013-10-29 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Preparation method of slope field plate structure in power device |
| US8980759B1 (en) * | 2014-05-22 | 2015-03-17 | Hrl Laboratories, Llc | Method of fabricating slanted field-plate GaN heterojunction field-effect transistor |
| WO2016033977A1 (en) * | 2014-09-01 | 2016-03-10 | 苏州捷芯威半导体有限公司 | Inclined field plate power device and method for fabricating the inclined field plate power device |
| JP2018129537A (en) * | 2018-04-16 | 2018-08-16 | 三菱電機株式会社 | Semiconductor device and method of manufacturing the same |
| CN209055800U (en) * | 2018-11-21 | 2019-07-02 | 北京燕东微电子有限公司 | A kind of lithography mask version and SiC junction termination structures |
| CN111463266A (en) * | 2020-04-13 | 2020-07-28 | 河北工业大学 | Inverted trapezoidal gate MOSFET device structure with inclined sidewall field plate |
Non-Patent Citations (1)
| Title |
|---|
| 高压VDMOS场板终端技术的研究;吴正元等;《华中理工大学学报》;19990430(第04期);正文全文 * |
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