JP2005276914A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the breakdown voltage between the source and drain of a semiconductor device while suppressing the increase of the on-resistance. <P>SOLUTION: The electric field applied to an offset drain layer 5 from a field plate 10 is gradually reduced from a drain layer 8 to a gate electrode 4 by forming an interlayer dielectric 9 having steps 9a, 9b, and 9c on the offset drain layer 5, and a field plate 12 on the offset drain layer 5 through the interlayer dielectric 9 having the steps 9a, 9b, and 9c. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable for application to a MOSFET (Metal Oxide Field Effective Transistor) in which a field plate is provided on an offset drain.

A transistor used in a transmission / reception circuit of a mobile communication terminal device is required to have a large current and a high breakdown voltage without increasing the on-resistance. In order to realize such a ranger, for example, Patent Document 1 discloses a MOSFET in which a field plate is provided on an offset drain.
In this MOSFET, a field plate provided on the offset drain is connected to the gate electrode, and an electric field can be generated in the offset drain by applying a voltage to the field plate through the gate electrode when the gate is turned on. Then, by reducing the electric field generated in the offset drain by the electric field generated from the field plate, the breakdown voltage between the source and the drain can be improved.

For example, Patent Document 2 discloses a method of providing a GOLD (Gate Overlapped Drain) on the offset drain in order to relax the surface electric field of the offset drain.
In this MOSFET, the gate electrode is extended to the drain side so as to cover the offset drain. Then, by reducing the electric field generated in the offset drain by the electric field generated from the gate electrode, the source / drain breakdown voltage can be improved.
JP-A-5-259456

  However, in the conventional MOSFET, when a voltage is applied to the field plate when the gate is turned on, an electric field perpendicular to the drain electric field is generated in the offset drain. For this reason, carriers that run through the offset drain feel an attractive force in a direction perpendicular to the drain and are pressed against the silicon surface. Accordingly, when a field plate is provided on the offset drain, the breakdown voltage between the source and the drain can be improved, but there is a problem that the on-resistance increases.

  Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve the breakdown voltage between the source and the drain while suppressing an increase in on-resistance.

In order to solve the above-described problem, according to a semiconductor device of one embodiment of the present invention, in a semiconductor device in which a field effect transistor having an offset drain is formed, a field plate is inclined on the offset drain. It is arranged.
Thereby, it becomes possible to gradually weaken the electric field perpendicular to the drain electric field, and it is possible to gradually weaken the attractive force that presses the carriers against the silicon surface. For this reason, it is possible to gradually reduce the attractive force in the direction perpendicular to the drain perceived by carriers while relaxing the electric field generated in the offset drain by the electric field generated from the field plate, while suppressing an increase in on-resistance, It is possible to improve the breakdown voltage between the source / drain.

In addition, according to the semiconductor device of one embodiment of the present invention, the distance between the field plate and the offset drain is the smallest on the region with the lowest breakdown voltage of the offset drain.
As a result, it is possible to efficiently apply the electric field generated from the field plate to a region where electric field relaxation is most necessary, and to weaken the vertical electric field applied to the region where electric field relaxation is not necessary. . Therefore, it is possible to gradually weaken the attractive force that presses carriers against the silicon surface without impairing the effectiveness of electric field relaxation, and it is possible to improve the breakdown voltage between the source and drain while suppressing an increase in on-resistance. Become.

Further, according to the semiconductor device of one embodiment of the present invention, the field plate is arranged so that a distance between the field plate and the offset drain gradually decreases from the gate electrode to the drain of the field effect transistor. It is characterized by being inclined.
As a result, the electric field in the vicinity of the drain can be efficiently relaxed, and the vertical electric field in the vicinity of the gate electrode can be weakened. As a result, it is possible to increase the vertical electric field applied to the region where the electric field needs to be relaxed, and to weaken the vertical electric field applied to the region where the electric field does not need to be reduced. It is possible to improve the breakdown voltage between the source and the drain while suppressing the increase.

Further, according to the semiconductor device of one embodiment of the present invention, the field plate is arranged so that a distance between the field plate and the offset drain gradually increases from the gate electrode to the drain of the field effect transistor. It is characterized by being inclined.
Thereby, the electric field in the vicinity of the gate electrode can be efficiently relaxed, and the vertical electric field in the vicinity of the drain can be weakened. As a result, it is possible to increase the vertical electric field applied to the region where the electric field needs to be relaxed, and to weaken the vertical electric field applied to the region where the electric field does not need to be reduced. It is possible to improve the breakdown voltage between the source and the drain while suppressing the increase.

In addition, according to the semiconductor device of one embodiment of the present invention, the field effect transistor is formed over an SOI substrate.
As a result, element isolation of the field effect transistor can be easily performed, latch-up can be prevented, and the source / drain junction capacitance can be reduced. It is possible to increase the speed.

  In addition, according to the semiconductor device of one embodiment of the present invention, the gate electrode formed over the semiconductor, the source layer provided on the semiconductor and disposed on one side of the gate electrode, and the semiconductor device An offset drain layer disposed on the other side of the gate electrode, a drain layer connected to the offset drain layer at a predetermined distance from the gate electrode, and an inclined surface disposed on the offset drain layer And a field plate formed on the inclined surface, and a wiring layer connecting the field plate and the gate electrode.

As a result, the field plate can be inclined and disposed on the offset drain layer. For this reason, an electric field generated from the field plate can be efficiently applied to a region where the electric field needs to be relaxed, and the breakdown voltage between the source and the drain can be improved while suppressing an increase in on-resistance. .
In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming a gate electrode on the semiconductor layer, and an ion-implantation into the semiconductor layer to selectively offset the drain layer in the semiconductor layer Forming a source / drain layer in the semiconductor layer by selectively implanting ions into the semiconductor layer, and forming an interlayer insulating film on the semiconductor layer on which the source / drain layer is formed. Forming an inclined surface disposed on the offset drain layer by etching the interlayer insulating film, and disposing the inclined surface of the interlayer insulating film on the inclined surface of the interlayer insulating film. Forming a field plate; and forming a wiring layer that connects the field plate and the gate electrode.

  As a result, by disposing the field plate on the interlayer insulating film, the field plate can be inclined and disposed on the offset drain layer. For this reason, an electric field generated from the field plate can be efficiently applied to a region where the electric field needs to be relaxed, and the breakdown voltage between the source and the drain can be improved while suppressing an increase in on-resistance. .

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the inclined surface disposed on the offset drain layer in the interlayer insulating film includes opening a resist pattern covering the interlayer insulating film. The half-etching of the interlayer insulating film is repeated while reducing the width of the portion.
As a result, it is possible to form an inclined surface in the interlayer insulating film by repeating the photolithography technique and the etching technique that are generally used in the semiconductor manufacturing process, and the field plate is arranged to be inclined on the offset drain layer. It becomes possible.

The method for manufacturing a semiconductor device according to one aspect of the present invention further includes a step of forming an etch stop layer on the inclined surface disposed on the offset drain layer.
As a result, overetching of the interlayer insulating film when the field plate is embedded in the interlayer insulating film can be prevented, and the field plate can be stably formed in the interlayer insulating film.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
1 to 3 are sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
In FIG. 1A, a semiconductor layer 2 is formed on the BOX layer 1. As the material of the semiconductor layer 2, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe or the like can be used. As the BOX layer 1, for example, SiO ₂ An insulating layer such as SION or Si ₃ N ₄ or a buried insulating film can be used. In addition, as the semiconductor substrate in which the semiconductor layer 2 is formed on the BOX layer 1, for example, an SOI substrate can be used. As the SOI substrate, a SIMOX (Separation by Implanted Oxgen) substrate, a bonded substrate, or a laser annealed substrate can be used. Etc. can be used. Further, as the BOX layer 1, an insulating substrate such as sapphire, glass or ceramic may be used. The semiconductor layer 2 may be a single crystal semiconductor layer, a polycrystalline semiconductor layer, or an amorphous semiconductor layer.

  A gate electrode 4 is formed on the semiconductor layer 2 via a gate insulating film 3, and sidewalls 6 a and 6 b are formed on the side walls of the gate electrode 4. A source layer 7 is formed on one side with respect to the gate electrode 4. An offset drain layer 5 is formed on the other side of the gate electrode 4, and a drain layer 8 is formed so as to be separated from the gate electrode 4 by a predetermined distance.

Then, as shown in FIG. 1B, an interlayer insulating film 9 is deposited on the entire surface by a method such as CVD. For example, a silicon oxide film can be used as the interlayer insulating film 9.
Next, as shown in FIG. 1C, a resist pattern R1 provided with an opening H1 exposing the surface of the interlayer insulating film 9 on the offset drain 5 is formed by using a photolithography technique.

Next, as shown in FIG. 1D, a step 9a is formed in the interlayer insulating film 9 by half-etching the interlayer insulating film 9 using the resist pattern R1 as a mask. As a half etching method for the interlayer insulating film 9, wet etching using hydrofluoric acid as an etchant can be used.
Next, as shown in FIG. 1E, after removing the resist pattern R1, an opening H2 for exposing the surface of the interlayer insulating film 9 on the offset drain 5 is provided by using a photolithography technique. A resist pattern R2 is formed. The width of the opening H2 provided in the resist pattern R2 can be narrower than the width of the opening H1 provided in the resist pattern R1.

Next, as shown in FIG. 2A, by using the resist pattern R2 as a mask, the interlayer insulating film 9 is half-etched to form a step 9b disposed inside the step 9a in the interlayer insulating film 9. .
Next, as shown in FIG. 2B, after removing the resist pattern R2, an opening H3 for exposing the surface of the interlayer insulating film 9 on the offset drain 5 was provided by using a photolithography technique. A resist pattern R3 is formed. The width of the opening H3 provided in the resist pattern R3 can be made narrower than the width of the opening H2 provided in the resist pattern R2.

Next, as shown in FIG. 2C, the interlayer insulating film 9 is half-etched using the resist pattern R3 as a mask to form a step 9c disposed inside the step 9b in the interlayer insulating film 9. .
Next, as shown in FIG. 2D, after removing the resist pattern R3, the surface of the interlayer insulating film 9 on which the steps 9a, 9b, 9c are formed is washed with dilute hydrofluoric acid, whereby the interlayer insulating film 9 is smoothed.

  Next, as shown in FIG. 2E, an etch stop film 10 is formed on the interlayer insulating film 9 in which the steps 9a, 9b, 9c are formed by a method such as CVD. Then, the etch stop film 10 is patterned by using the photolithography technique and the etching technique, thereby forming the etch stop film 10 in the interlayer insulating film 9 on the offset drain 5. For example, a silicon nitride film can be used as the etch stop film 10.

Next, as shown in FIG. 3A, an interlayer insulating film 11 is deposited on the entire surface of the interlayer insulating film 9 on which the etch stop film 10 is formed by a method such as CVD.
Next, as shown in FIG. 3B, the interlayer insulating film 11 is patterned by using a photolithography technique and an etching technique to remove the interlayer insulating film 11 on the etch stop film 10, and the etch stop film 10. Openings 11 a are formed in the upper interlayer insulating film 11.

  Next, as shown in FIG. 3C, a polycrystalline silicon layer is formed on the interlayer insulating film 11 in which the opening 11a is formed by a method such as CVD. Then, the field plate 12 is formed on the etch stop film 10 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique. As a material for the field plate 12, a metal such as Al or Cu may be used in addition to the polycrystalline silicon layer.

  Next, as shown in FIG. 3D, the interlayer insulating film 13 is embedded in the opening 11a formed in the interlayer insulating film 11 by a method such as CVD. Then, using the photolithography technique and the etching technique, openings for exposing the surfaces of the field plate 12 and the gate electrode 4 are formed in the interlayer insulating films 9, 11, and 13. Then, a metal film such as Al is formed on the entire surface by a method such as sputtering, and the metal film is patterned using a photolithography technique and an etching technique, thereby forming a wiring layer 14 for connecting the field plate 12 and the gate electrode 4. Form.

  Here, by disposing the field plate 12 on the interlayer insulating film 9 in which the steps 9a, 9b, and 9c are formed, the electric field perpendicular to the drain electric field can be gradually weakened. The attractive force that presses the carrier against the surface can be gradually weakened. For this reason, it is possible to reduce the attractive force in the direction perpendicular to the surface of the drain 8 felt by the carrier while relaxing the electric field generated in the offset drain 5 by the electric field generated from the field plate 12, thereby suppressing an increase in on-resistance. However, the breakdown voltage between the source / drain layers 7 and 8 can be improved.

In the above-described embodiment, the method of forming and etching the resist patterns R1, R2, and R3 three times has been described. However, the resist pattern formation and etching are not limited to three times. And etching may be performed twice each, or four times or more each.
FIG. 4 is a sectional view showing a schematic configuration of a semiconductor device according to the second embodiment of the present invention.

  In FIG. 4, a semiconductor layer 22 is formed on the BOX layer 21. A gate electrode 24 is formed on the semiconductor layer 22 via a gate insulating film 23, and side walls 26 a and 26 b are formed on the side walls of the gate electrode 24. A source layer 27 is formed on one side with respect to the gate electrode 24. An offset drain layer 25 is formed on the other side of the gate electrode 24, and a drain layer 28 is formed so as to be separated from the gate electrode 24 by a predetermined distance.

  The field plate 32 is inclined and embedded in the interlayer insulating film 29 so that the distance between the field plate 32 and the offset drain 25 gradually increases from the gate electrode 24 toward the drain layer 28. An etch stop film 30 can be disposed under the field plate 32. A wiring layer 34 that connects the field plate 32 and the gate electrode 24 is formed on the interlayer insulating film 29.

Thereby, the electric field in the vicinity of the gate electrode 24 can be efficiently relaxed, the electric field in the vertical direction in the vicinity of the drain layer 28 can be weakened, and the increase in the on-resistance can be suppressed while suppressing the increase in the source / The breakdown voltage between the drain layers 27 and 28 can be improved.
FIG. 5 is a sectional view showing a schematic configuration of a semiconductor device according to the third embodiment of the present invention.
In FIG. 5, a semiconductor layer 42 is formed on the BOX layer 41. A gate electrode 44 is formed on the semiconductor layer 42 via a gate insulating film 43, and side walls 46 a and 46 b are formed on the side walls of the gate electrode 44. A source layer 47 is formed on one side with respect to the gate electrode 44. An offset drain layer 45 is formed on the other side of the gate electrode 44, and a drain layer 48 is formed so as to be separated from the gate electrode 44 by a predetermined distance.

  The field plate 42 is bent and embedded in the interlayer insulating film 49 so that the distance between the field plate 52 and the offset drain 45 gradually increases from the gate electrode 44 and the drain layer 48 toward the middle thereof. . An etch stop film 50 can be disposed under the field plate 52. A wiring layer 54 that connects the field plate 52 and the gate electrode 44 is formed on the interlayer insulating film 49.

  Thereby, the electric field in the vicinity of the gate electrode 24 and the drain layer 28 can be efficiently relaxed, and the vertical electric field between the gate electrode 24 and the drain layer 28 can be weakened. As a result, it is possible to increase the vertical electric field applied to the region where the electric field needs to be relaxed, and to weaken the vertical electric field applied to the region where the electric field does not need to be reduced. It is possible to improve the breakdown voltage between the source / drain layers 48 and 48 while suppressing the increase.

  In the above-described embodiment, the field effect transistor formed on the SOI substrate has been described as an example. However, other than the field effect transistor formed on the SOI substrate, for example, the field effect transistor is formed on a bulk semiconductor. The present invention may be applied to a field effect transistor or a TFT (Thin Film Transistor).

Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows schematic structure of the semiconductor device which concerns on 2nd Embodiment of this invention. Sectional drawing which shows schematic structure of the semiconductor device which concerns on 3rd Embodiment of this invention.

Explanation of symbols

  1, 21, 41 BOX layer, 2, 22, 42 Semiconductor layer, 3, 23, 43 Gate insulating film, 4, 24, 44 Gate electrode, 5, 25, 45 Offset drain layer, 6a, 6b, 26a, 26b, 46a, 46b Side wall, 7, 27, 47 Source layer, 8, 28, 48 Drain layer, 9, 11, 13, 29, 49 Interlayer insulating film, 9a, 9b, 9c Step, 10, 30, 50 Etch stop film , 12, 32, 52 Field plate, 14, 34, 54 Wiring layer, R1, R2, R3 Resist pattern, H1, H2, H3, 11a Opening

Claims (9)

In a semiconductor device in which a field effect transistor having an offset drain is formed,
A semiconductor device, wherein a field plate is disposed on the offset drain so as to be inclined.   2. The semiconductor device according to claim 1, wherein a distance between the field plate and the offset drain is smallest on a region with the lowest breakdown voltage of the offset drain.   2. The semiconductor according to claim 1, wherein the field plate is inclined so that the distance between the field plate and the offset drain gradually decreases from the gate electrode to the drain of the field effect transistor. apparatus.   2. The semiconductor according to claim 1, wherein the field plate is inclined so that a distance between the field plate and the offset drain gradually increases from the gate electrode to the drain of the field effect transistor. apparatus.   The semiconductor device according to claim 1, wherein the field effect transistor is formed on an SOI substrate. A gate electrode formed on the semiconductor;
A source layer provided on the semiconductor and disposed on one side of the gate electrode;
An offset drain layer provided on the semiconductor and disposed on the other side of the gate electrode;
A drain layer connected to the offset drain layer at a predetermined interval from the gate electrode;
An interlayer insulating film having an inclined surface disposed on the offset drain layer;
A field plate formed on the inclined surface;
A semiconductor device comprising: a wiring layer connecting the field plate and the gate electrode. Forming a gate electrode on the semiconductor layer;
Forming an offset drain layer in the semiconductor layer by selectively implanting ions into the semiconductor layer;
Forming a source / drain layer in the semiconductor layer by selectively implanting ions into the semiconductor layer;
Forming an interlayer insulating film on the semiconductor layer on which the source / drain layers are formed;
Forming an inclined surface disposed on the offset drain layer in the interlayer insulating film by etching the interlayer insulating film;
Forming a field plate disposed on the inclined surface of the interlayer insulating film;
Forming a wiring layer connecting the field plate and the gate electrode. A method of manufacturing a semiconductor device, comprising: Forming an inclined surface disposed on the offset drain layer in the interlayer insulating film,
8. The method of manufacturing a semiconductor device according to claim 7, wherein half-etching of the interlayer insulating film is repeated while reducing the width of the opening of the resist pattern covering the interlayer insulating film.   9. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming an etch stop layer on an inclined surface disposed on the offset drain layer.

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