CN102184909A - Pin structure for connecting chips - Google Patents

Pin structure for connecting chips Download PDF

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Publication number
CN102184909A
CN102184909A CN 201110084650 CN201110084650A CN102184909A CN 102184909 A CN102184909 A CN 102184909A CN 201110084650 CN201110084650 CN 201110084650 CN 201110084650 A CN201110084650 A CN 201110084650A CN 102184909 A CN102184909 A CN 102184909A
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CN
China
Prior art keywords
row
chip
substrate
pins
leg structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN 201110084650
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Chinese (zh)
Inventor
游乔焜
刘勇智
罗素
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AU Optronics Corp
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AU Optronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AU Optronics Corp filed Critical AU Optronics Corp
Priority to CN 201110084650 priority Critical patent/CN102184909A/en
Publication of CN102184909A publication Critical patent/CN102184909A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Combinations Of Printed Boards (AREA)

Abstract

The invention provides a pin structure for connecting chips, comprising a substrate, four rows of pins and a plurality of conducting wires, wherein the four rows of pins are located on one surface of the substrate, the pins of each row are approximately arranged in parallel, and a first interval is reserved between every two adjacent rows of pins; the pins of each row are respectively provided with a plurality of metal bumps arranged in parallel, a second space is reserved between every two adjacent metal bumps, and the second space is approximately twice the width of the metal bump. The metal bumps of every two adjacent rows of pins are mutually staggered. The conducting wires are arranged in parallel, and each conducting wire is connected with a metal bump. By using the pin structure for connecting chips, the width and gap between adjacent metal bumps of each row can be increased to overcome the short-circuit problem caused by over-narrow gaps on the premise of ensuring that the number of pins and a press fit area are not changed,.

Description

A kind of being applicable to connects the chip leg structure
Technical field
The present invention relates to a kind of chip leg structure, relate in particular to the connection chip leg structure that a kind of employing anisotropy conducting film (ACF) carries out combination on glass (COG) structure packing technique.
Background technology
Common flat display apparatus for example in LCD (LCD) or the plasma display (PDP), all adopts semiconductor subassemblies such as integrated circuit (IC) chip, in order to the demonstration of control chart picture at present.In the structure dress of integrated circuit (IC) chip, combination on glass (Chip OnGlass) assembling structure is a kind of mode commonly used at present, and its structure is that the direct structure of drive IC is loaded on the insulated substrate of flat display apparatus.
Current integrated circuit (IC) industry development is rapid unusually, and technological progress is maked rapid progress, and integrated circuit (IC) also develops towards light, thin direction.Along with drive integrated circult (Driver IC) chip is done littler and littler, but can there be error in the electronic pads on the metal coupling of connection integrated circuit (IC) chip leg structure and the insulated substrate of flat display apparatus when contraposition, require metal coupling that certain width is arranged, could guarantee metal coupling and electronic pads normally, so can only dwindle the spacing between the metal coupling on the IC chip.
But, when adopting anisotropy conducting film (ACF) that chip and LCD (LCD) etc. are carried out on glass combination the (Chip On Glass), the conducting particles that is contained in the anisotropy conducting film (ACF) might not be taken a walk evenly, may be higher in some regional conducting particles density, because the gap between the metal coupling on the chip is less, therefore in such cases, conducting particles (ACF particle) produces gathering at the gap location of metal coupling, can cause the short circuit phenomenon of IC pin thus, and then influence the transmission of control signal.
In view of this, how designing a kind of novel connection chip leg structure, increase the gap between the metal coupling, to improve the short circuit problem that causes because of the gap is too small, is the problem that those skilled in the art need solution badly.
Summary of the invention
At connecting the defective that exists in the chip leg structure in the prior art, the invention provides a kind of being applicable to and connect the chip leg structure.
According to the present invention, provide a kind of being applicable to connect the chip leg structure, comprise substrate, four row's pin and many call wires.Four row's pins are positioned on the surface of substrate, and each row's pin is arranged in parallel approximately and each row has one first spacing between pin.Each row pin have a plurality of metal couplings respectively, and each row pin a plurality of metal couplings be arranged in parallel and in twos between second spacing is arranged, second spacing doubles the metal coupling width approximately.The metal coupling of per two row's pins is staggered each other.Many call wires are arranged in parallel approximately and each call wire connects a metal coupling respectively.
Preferably, substrate is a bendable circuit substrate.
Preferably, the material of metal coupling is one of them or a combination in any of gold, silver, palladium, copper, tin, nickel, tin lead.
Preferably, connect a chip leg structure and an insulated substrate and form an assembling structure.
Preferably, connect the chip leg structure and more comprise a plurality of electronic padses, be formed on the insulated substrate position corresponding to metal coupling.
Preferably, insulated substrate is a face glass.
Preferably, substrate and face glass are by the pressing of anisotropy conducting film.
Adopt connection chip leg structure of the present invention, can under the regional constant situation of pressing, increase the quantity of metal coupling, and increase the gap between the metal coupling, to improve the short circuit phenomenon that causes because of the gap is too small.
Description of drawings
The reader will become apparent various aspects of the present invention after the reference accompanying drawing has been read the specific embodiment of the present invention.Wherein,
Fig. 1 shows the structural representation that connects the chip leg structure in the prior art;
Fig. 2 shows according to the present invention, connects the structural representation of chip leg structure;
Embodiment
With reference to the accompanying drawings, the specific embodiment of the present invention is described in further detail.
Fig. 1 shows the structural representation that connects the leg structure of chip in the prior art.With reference to Fig. 1, connect chip leg structure 10 and comprise: substrate 110, two row's pin and many leads 131.Wherein, two row's pins are positioned on the surface of substrate 110, and each row's pin 120 is arranged in parallel approximately, and each 120 of pin of row has one first spacing d1.In addition, each row pin 120 have a plurality of metal couplings 121 respectively, each row pin 120 a plurality of metal couplings 121 be arranged in parallel and in twos between the second spacing d2 is arranged, the second spacing d2 doubles the width of metal coupling 121 approximately.The metal coupling 121 of per two row's pins 120 is staggered each other.The first spacing d1 among Fig. 1 is less, when adopting anisotropy conducting film (ACF) to carry out pressing to connecting chip leg structure 10, the conducting particles density that the regional anisotropy conducting film that has contains is higher, can produce polymerization, so the phenomenon that can be short-circuited, influence the transmission of signal.
Fig. 2 shows according to the present invention, connects the structural representation of chip leg structure.With reference to Fig. 2, connect chip leg structure 20 and comprise: substrate 210, four row's pin (not indicating) and many call wires 231.As shown in the figure, in the present embodiment, substrate 210 is bendable circuit substrates.Four row's pins are positioned on the surface of substrate 210, and each row's pin 220 is arranged in parallel approximately, and each 220 of pin of row has one first spacing d1.In addition, each row pin 220 have a plurality of metal couplings 221 respectively, each row pin 220 a plurality of metal couplings 221 be arranged in parallel and in twos between the second spacing d2 is arranged, the second spacing d2 doubles the width of metal coupling 221 approximately.The metal coupling 221 of per two row's pins 220 is staggered each other.Shortened the length of metal coupling, guarantee under the constant situation in pressing district, increase metal coupling to four row, therefore, do not changing under the pin count purpose situation, increased the spacing between adjacent two metal couplings in every row's metal coupling greatly, can avoid narrow and small because of the gap when pressing like this, the conducting particles in the anisotropy conducting film is assembled the short circuit problem that causes.
Continuation is with reference to Fig. 2, and many call wires 231 are arranged in parallel approximately, and each call wire 231 connects a metal coupling 221 respectively.As previously mentioned, the metal coupling 221 of per two row's pins 220 is staggered each other, can be convenient to metal coupling 221 places and draw call wire 231, avoids call wire 231 and metal coupling 221 to be in contact with one another and causes short circuit.In the present embodiment, the material of metal coupling is a gold, and among other embodiment, the material of metal coupling can be one of them or combination in any of silver, palladium, copper, tin, nickel, tin lead.In a further embodiment, can adopt the anisotropy conducting film will connect chip leg structure 20 and an insulated substrate and carry out pressing to form assembling structure, insulated substrate has a plurality of electronic padses corresponding to the position of metal coupling 221, and insulated substrate can be a liquid crystal panel.
As can be seen from the above embodiments, employing the invention has the advantages that, shortened the length of metal coupling in the integrated circuit, like this can be under the big or small constant situation in pressing district, increase row's number of metal coupling, therefore keeping making that the gap between the metal coupling increases greatly under the constant situation of number of pins, can change the short circuit problem that causes because of the gap is too small fully.
Above, describe the specific embodiment of the present invention with reference to the accompanying drawings.But those skilled in the art can understand, and under situation without departing from the spirit and scope of the present invention, can also do various changes and replacement to the specific embodiment of the present invention.These changes and replacement all drop in claims restricted portion of the present invention.

Claims (7)

1. one kind is applicable to that chip connects leg structure, it is characterized in that, comprising: substrate, four row's pins.
Substrate;
Four row's pins are positioned on described substrate one surface, and described each row's pin is arranged in parallel approximately, and have one first spacing between described each row's pin.Described each row pin have a plurality of metal couplings respectively, and described each row pin described a plurality of metal couplings be arranged in parallel and in twos between second spacing is arranged, described second spacing doubles the metal coupling width approximately.The described metal coupling of described per two row's pins is staggered each other; And
Many call wires are arranged in parallel approximately and each described call wire connects a described metal coupling respectively.
2. the chip that is applicable to as claimed in claim 1 connects leg structure, it is characterized in that described substrate is a bendable circuit substrate.
3. the chip that is applicable to as claimed in claim 1 connects leg structure, it is characterized in that, the material of described metal coupling is one of them or a combination in any of gold, silver, palladium, copper, tin, nickel, tin lead.
4. the chip that is applicable to as claimed in claim 1 connects leg structure, it is characterized in that, forms an assembling structure with an insulated substrate.
5. the chip that is applicable to as claimed in claim 4 connects leg structure, it is characterized in that, more comprises a plurality of electronic padses, is formed on the described insulated substrate position corresponding to described metal coupling.
6. the chip that is applicable to as claimed in claim 4 connects leg structure, it is characterized in that described insulated substrate is a face glass.
7. the chip that is applicable to as claimed in claim 4 connects leg structure, it is characterized in that described substrate and described face glass are by the pressing of anisotropy conducting film.
CN 201110084650 2011-04-01 2011-04-01 Pin structure for connecting chips Pending CN102184909A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201110084650 CN102184909A (en) 2011-04-01 2011-04-01 Pin structure for connecting chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201110084650 CN102184909A (en) 2011-04-01 2011-04-01 Pin structure for connecting chips

Publications (1)

Publication Number Publication Date
CN102184909A true CN102184909A (en) 2011-09-14

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201110084650 Pending CN102184909A (en) 2011-04-01 2011-04-01 Pin structure for connecting chips

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CN (1) CN102184909A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094737A (en) * 2011-11-05 2013-05-08 宝宸(厦门)光学科技有限公司 Pin structure and pin connecting structure
CN111913602A (en) * 2019-05-08 2020-11-10 敦泰电子有限公司 Display touch control driving chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094737A (en) * 2011-11-05 2013-05-08 宝宸(厦门)光学科技有限公司 Pin structure and pin connecting structure
CN111913602A (en) * 2019-05-08 2020-11-10 敦泰电子有限公司 Display touch control driving chip
CN111913602B (en) * 2019-05-08 2023-08-15 敦泰电子有限公司 Display touch control driving chip

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Application publication date: 20110914