CN102176498B - Manufacturing method of LED chip - Google Patents
Manufacturing method of LED chip Download PDFInfo
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- CN102176498B CN102176498B CN 201110069891 CN201110069891A CN102176498B CN 102176498 B CN102176498 B CN 102176498B CN 201110069891 CN201110069891 CN 201110069891 CN 201110069891 A CN201110069891 A CN 201110069891A CN 102176498 B CN102176498 B CN 102176498B
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Abstract
The invention discloses a manufacturing method of an LED chip, wherein a procedure of removing one part of an epitaxial layer comprises the following steps of: forming a first mask film layer on the epitaxial layer, wherein the first mask film layer comprises a plurality of mask film layer units isolated from one another, and a first clearance with a predetermined size is arranged among the mask film layer units; removing a second semiconductor layer, a lighting layer and one part of a first semiconductor layer from a region where the first clearance is located to form a groove; eliminating the first mask film layer; repeating the steps for N times to remove parts of the epitaxial layer and a buffer layer until reaching a substrate, reserving an Nth clearance with predetermined size among the mask film layer units, wherein the width of the Nth clearance is greater than that of a (N-1)th clearance; forming an isolating groove with N steps, wherein N is not smaller than 2. By applying the technical scheme of the invention, the isolating groove has smaller depth and greater width as well as a certain inclination degree, thereby being beneficial to the coverage of an insulating material and the adhesion of metal connection wires, and solving the problem of breakage probably caused when the metal connection wires cross a deeper groove.
Description
Technical field
The present invention relates to the manufacture method of light-emitting device array, in particular to a kind of manufacture method of led chip.
Background technology
With respect to high-power chip, the middle low power chip has good light efficiency and heat dispersion and higher reliability owing to adopt small current driving, uses very extensive in illumination and floor light field.In order to obtain enough brightness and illumination, just need abundant LED lamp pearl is welded on substrate or the printed circuit board (PCB) by series-parallel mode, namely first encapsulation is rear integrated.Array high-voltage alternating led chip has a plurality of LED structure cells (sub-chip), and is to satisfy specific electrical demands, namely first integrated according to the suitable serial or parallel connection of demand, rear encapsulation.
Good conductive ability in view of N-type GaN, obtain discrete device, then the N-type GaN between each structure cell must be removed and form the electric isolation groove, then between isolation channel and structure cell, form insulating barrier with each structure cell of electric insulation, form electricity at insulating barrier at last and connect.Realize above-mentioned purpose, under the prior art condition, at first need the N-type GaN that communicates with each other partially-etched until Sapphire Substrate formation electrical isolation groove does not damage P type GaN and transparency electrode on the luminous zone simultaneously.
Existing technological means, can realize the formation of isolation channel by the ICP etching, but need to be with the GaN etching until Sapphire Substrate, etching depth just need to reach (5-7 μ m) more than 5 microns, when carrying out the ICP etching, very high requirement has just been proposed masking layer like this, can adopt the modes such as evaporation to form the metal shadowing layers such as nickel, gold on the conventional art, carry out the ICP etching behind the lithography stripping.The forming process of considering masking layer is numerous and diverse, and the heat of long-time plasma bombardment device surface generation and the damage that brings to device, so that there are many drawbacks in this method in normal production technology.
In addition, the metal interconnection wire that forms by modes such as electron beam evaporation or chemical gildings ruptured when crossing over dark isolation channel easily, especially comparatively vertical sidewall, thus have influence on led chip connection to each other.General solution is adopt to electroplate, change the means such as plating increase electric connection line thickness with fill up isolation channel cause can be complete cover on the sidewall.Too high electric connection line may cause coming off easily in follow-up attenuate cutting, has also increased production cost simultaneously, and complex procedures, reliability also can't ensure.
And for example wafer photoelectricity is 200810169439.1 in the patent No.＜makes the method for light emitting array〉in described and can utilize insulating barrier growth rate on its horizontal direction when forming to seal isolation channel greater than this characteristic of vertical direction growth rate, prerequisite is the twice that the width of isolation channel is not more than thickness of insulating layer.According to understanding in its Figure of description, according to institute's restriction of above-mentioned " flakiness ratio ", then necessarily requiring can only be to form very narrow isolation channel, and perhaps extremely thick insulating barrier just might satisfy the restriction requirement of " flakiness ratio ".Narrow isolation channel has proposed huge challenge to photoetching process, ICP lithographic technique and macking technique thereof, and the film that relies on the micron order thickness that the methods such as vapour deposition, evaporation, sputter form is also often consuming time and be difficult to control, even set up time groove, the reliability of its technical enforcement difficulty and final products is not suitable for mass production yet.
Summary of the invention
The present invention aims to provide a kind of manufacture method of led chip, plasma bombards device surface and the heat that produces brings damage to device for a long time when forming isolation channel to solve the following technical problem that exists in the prior art: ICP, and masking layer is required high, generally need the metal shadowing layers such as nickel, gold, the forming process of this masking layer is numerous and diverse; And metal interconnection wire ruptures when crossing over the isolation channel more deeply, especially have vertical sidewall comparatively easily, has influence on the led chip technical problems such as connection to each other.
The manufacture method of led chip provided by the invention may further comprise the steps: step S10, substrate is provided, and form resilient coating on substrate; Step S20 forms epitaxial loayer on resilient coating, specifically may further comprise the steps: step S21, form the first semiconductor layer on resilient coating, and step S22 forms luminescent layer on the first semiconductor layer, and step S23, forms the second semiconductor layer on luminescent layer; Step S30 removes part epitaxial loayer and resilient coating to substrate, forms isolation channel, and isolation channel is divided into a plurality of sub-chips with chip; And step S40, installing electrodes and finish interelectrode electrical connection on epitaxial loayer; Wherein, step S30 removes the part epitaxial loayer and may further comprise the steps: step S31, form the first mask layer at epitaxial loayer, and the first mask layer comprises a plurality of spaced mask layers unit, leaves the first gap of pre-sizing between each mask layer unit; Step S32 removes the second semiconductor layer of region, the first gap, and luminescent layer and part the first semiconductor layer are to form groove; Step S33 removes the first mask layer; Repeating step S30N time removes the part epitaxial loayer to substrate, wherein among the step S31, leaves the N gap of pre-sizing between each mask layer unit, and the width in N gap forms the isolation channel with N step, N 〉=2 greater than the width in N-1 gap.
Preferably, N equals 3.
Further, the width of reserving the first gap among the step S31 between each unit of the first mask layer is 5～15 μ m.
Further, among the step S32, remove the second semiconductor layer, the degree of depth of luminescent layer and part the first semiconductor layer is 2～3 μ m.
Further, mask layer is by SiO
2, chromium, nickel or photoresist make.
Further, mask layer is made by photoresist.
Further, remove the second mask layer after, form transparency conducting layer at the second semiconductor layer, on isolation channel and the sidewall of transparency conducting layer edge, the second semiconductor layer, luminescent layer and the first semiconductor layer form electric insulation layer.
Further, electric insulation layer is reserved with the through hole that passes through for the electric connection line of finishing electrical connection.
Further, installing electrodes and finish interelectrode electrical connection and specifically may further comprise the steps on epitaxial loayer: form the first electrode at the first semiconductor layer; Form the second electrode at the second semiconductor layer; And finish the electrical connection between the first electrode and the second electrode between each unit.
Use technical scheme of the present invention, adopt the method for step-etching, cooperate photoresist as masking material, technique is relatively simple, realize easily, and the step isolation channel that forms possesses the more shallow degree of depth, larger width, certain angle of inclination, be conducive to the covering of insulating material, adhering to of metal connecting line, solved the breakage problem that may cause when metal interconnection wire is crossed over darker groove.
Description of drawings
Figure of description is used to provide a further understanding of the present invention, consists of a part of the present invention, and illustrative examples of the present invention and explanation thereof are used for explaining the present invention, do not consist of improper restriction of the present invention.In the accompanying drawings:
Fig. 1 to Fig. 6 shows the manufacture method schematic diagram of led chip of the present invention; And
Fig. 7 shows the structural representation of two sub-chips of series LED.
Embodiment
Need to prove that in the situation of not conflicting, embodiment and the feature among the embodiment among the present invention can make up mutually.Describe below with reference to the accompanying drawings and in conjunction with the embodiments the present invention in detail.
The manufacture method of led chip provided by the invention may further comprise the steps:
As shown in Figure 1, provide substrate 10; Wherein substrate 10 is sapphire materials.Form resilient coating 20 at substrate 10, resilient coating 20 is made by plain gallium nitride simple substance.Form epitaxial loayer 30 on resilient coating 20, specifically may further comprise the steps: form the first semiconductor layer 31 on resilient coating 20, form luminescent layer 32 on the first semiconductor layer 31, and form the second semiconductor layer 33 on luminescent layer 32.Comprising a plurality of spaced mask layers unit through epitaxial loayer 30 formation the first mask layer 41, the first mask layers 41 after the surface clean, leave the first gap of pre-sizing between each mask layer unit.Need according to concrete design, the width of reserving the first gap between the first mask layer 41 each unit is made as 5～15 μ m.Wherein, the material of mask layer can be SiO
2, chromium, nickel, photoresist or other mask materials, preferably, with photoresist as mask material.On the one hand, because photoresist itself also can be used as the masking material of ICP etching, easily processing is easily removed, and yield is high; On the other hand, use other materials such as silica, need to utilize photoresist to do the transfer of a figure, wet etching namely, the present invention directly adopts photoresist convenient as mask material; Again on the one hand, the present invention is intended to solve the metal wire breakage problem that too deeply causes owing to isolation channel, and photoresist is easy to do in echelon, it is the acclive inclined-plane of tool, like this through after the ICP etching, be easy to the sidewall of isolation channel is done ramp-like rather than vertical, so just more be conducive to adhering to and being connected of metal wire.
As shown in Figure 1, 2, through the second semiconductor layer 33, luminescent layer 21, part the first semiconductor layer 31 that ICP removes region, the first gap, at first groove of the epitaxial loayer 30 formation degree of depth at 2-3 μ m, remove the first mask layer 41.
As shown in Figure 3, form at epitaxial loayer 30, form the second masking layer 42, the size restrictions of this second mask layer 42 is in the profile scope of the first mask layer 41 shown in Figure 1, and to inside contract 5-15 μ m be good at the edge.
Shown in Fig. 3,4, ICP etching for the second time, the degree of depth is 2-3 μ m, forms the second groove, this moment the first groove by further downwards etching reach the degree of depth of 4-6 μ m, form ladder between the first groove and the second groove, comprise the first groove in the second groove.Then, remove the second mask layer 42.
As shown in Figure 5, form at epitaxial loayer 30, form the 3rd mask layer 43, so that first, second groove and part the second semiconductor layer are exposed, namely the 3rd mask layer 43 edges inside contract 5-15 μ m than the second mask layer 42 after the techniques such as process photoetching, chemical etching.
Shown in Fig. 5,6, ICP etching for the third time, the degree of depth is 1.2-1.8 μ m, forms the 3rd groove, this moment, groove was etched to Sapphire Substrate, realized the electrical isolation of chip chamber.The first groove, the second groove and the 3rd groove three form the isolation channel with certain angle of inclination step; Remove the 3rd mask layer 43.
As shown in Figure 7, form transparency conducting layer 54 at the second semiconductor layer 33, on the isolation channel, transparency conducting layer edge 54 and the first semiconductor layer 31, luminescent layer 32, the second semiconductor layer 33 sidewalls form electric insulation layer 60, electric insulation layer 60 thickness 5000-10000 dusts.Electric insulation layer 60 is reserved with the through hole that passes through for the electric connection line of finishing electrical connection.Form the first electrode 51 at the first semiconductor layer 31; Form the second electrode 52 at the second semiconductor layer 33; Finish the electrical connection between the first electrode and the second electrode between each unit.
Further, form electrode and electric connection line by chemical vapour deposition technique, physical vaporous deposition, electron beam evaporation plating method, change plating or electro-plating method.
The isolation channel that adopts method provided by the invention to form has the more shallow degree of depth, larger width, certain angle of inclination, is conducive to adhering to of insulating barrier, and can guarantee that metal wire crosses over unlikely fracture; The present invention adopts the method for step-etching, cooperates photoresist as masking material, and technique is simple, and the device damage that can effectively avoid the long-time physical chemistry etching of chip to bring; Adopt thinner metal material to form electrical cable, saved cost; The insulating barrier that the present invention does not need to form large thickness covers table top and sidewall, also can obtain good insulation effect and unlikely short circuit; Adopt technical scheme of the present invention, can reduce production costs on the whole, improve the operability of technique and the reliability of product.
Embodiment one
Sapphire substrate is provided, forms resilient coating on substrate; Form epitaxial loayer at resilient coating, specifically may further comprise the steps: form the first semiconductor layer on resilient coating, form luminescent layer on the first semiconductor layer, and form the second semiconductor layer on luminescent layer.Forming the first mask layer through the epitaxial loayer after the surface clean, is 10 μ m according to design with the width of reserving the first gap between each unit of the first mask layer.Wherein, the material of mask layer can be photoresist.
Process ICP removes the second semiconductor layer, luminescent layer, part first semiconductor layer of the first interstitial site, forms the degree of depth on the epitaxial loayer at the first groove of 2 μ m, removes the first mask layer.
Form at epitaxial loayer, form the second masking layer, the size restrictions of this second mask layer is in the profile scope of the first mask layer, and the edge inside contracts 5 μ m.
ICP etching for the second time, the degree of depth is 2 μ m, forms the second groove, this moment the first groove by further downwards etching reach the degree of depth of 4 μ m, form ladder between the first groove and the second groove, comprise the first groove in the second groove.Then, remove the second mask layer.
Form at epitaxial loayer, form the 3rd mask layer, so that first, second isolation channel and part the second semiconductor layer are exposed, the 3rd mask layer edge inside contracts 5 μ m than the second mask layer after the techniques such as process photoetching, chemical etching.
ICP etching for the third time, the degree of depth is 1.2 μ m, forms the 3rd groove, this moment, groove was etched to Sapphire Substrate, realized the electrical isolation of chip chamber.The first groove, the second groove and the 3rd groove three form the isolation channel with certain angle of inclination step; Remove the 3rd mask layer.
Form transparency conducting layer at the second semiconductor layer, on the isolation channel, transparency conducting layer edge and the first semiconductor layer, luminescent layer, the second semiconductor layer sidewall form electric insulation layer, electric insulation layer thickness 5000 dusts.Electric insulation layer is reserved with the through hole that passes through for the electric connection line of finishing electrical connection.Form the first electrode at the first semiconductor layer; Form the second electrode at the second semiconductor layer; Finish the electrical connection between the first electrode and the second electrode between each unit.Form electrode and electric connection line by chemical vapour deposition technique.
Embodiment two
Sapphire substrate is provided; Form resilient coating at substrate, form epitaxial loayer at resilient coating, specifically may further comprise the steps: form the first semiconductor layer on resilient coating, form luminescent layer on the first semiconductor layer, and form the second semiconductor layer on luminescent layer.All the other methods of operation are with embodiment one, difference is, the width in the first gap is 15 μ m, forms the first groove of the degree of depth 3 μ m on the epitaxial loayer, and the second mask layer edge inside contracts 15 μ m than the first mask layer, ICP etching for the second time, the degree of depth is 3 μ m, and the 3rd mask layer edge inside contracts 15 μ m, for the third time ICP etching than the second mask layer, the degree of depth is 1.5 μ m, and electric insulation layer thickness is 8000 dusts.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. the manufacture method of a led chip may further comprise the steps:
Step S10 provides substrate, forms resilient coating on described substrate;
Step S20 forms epitaxial loayer on described resilient coating, specifically may further comprise the steps:
Step S21 forms the first semiconductor layer on described resilient coating,
Step S22 forms luminescent layer on described the first semiconductor layer, and
Step S23 forms the second semiconductor layer on described luminescent layer;
Step S30 removes the described epitaxial loayer of part and resilient coating to described substrate, forms isolation channel, and described isolation channel is divided into a plurality of sub-chips with described chip; And
Step S40, installing electrodes and finish interelectrode electrical connection on described epitaxial loayer;
It is characterized in that described step S30 removes the described epitaxial loayer of part and may further comprise the steps:
Step S31 forms the first mask layer at described epitaxial loayer, and described the first mask layer comprises a plurality of spaced mask layers unit, leaves the first gap of pre-sizing between each mask layer unit;
Step S32 removes described second semiconductor layer of region, described the first gap, and luminescent layer and part the first semiconductor layer are to form groove;
Step S33 removes described the first mask layer;
Repeating said steps S30 N time removes the described epitaxial loayer of part and resilient coating to described substrate, wherein among the step S31, leave the N gap of pre-sizing between each mask layer unit, the width in N gap forms the isolation channel with N step, N 〉=2 greater than the width in N-1 gap.
2. manufacture method according to claim 1 is characterized in that, described N equals 3.
3. manufacture method according to claim 1 is characterized in that, the width in the first gap is 5 ~ 15 μ m among the described step S31.
4. manufacture method according to claim 3 is characterized in that, among the described step S32, removes the second semiconductor layer for the first time, and the degree of depth of luminescent layer and part the first semiconductor layer is 2 ~ 3 μ m.
5. each described manufacture method is characterized in that according to claim 1-4, and described mask layer is by SiO
2, chromium, nickel or photoresist make.
6. manufacture method according to claim 5 is characterized in that, described mask layer is made by photoresist.
7. manufacture method according to claim 1, it is characterized in that, after removing the N mask layer, form transparency conducting layer at described the second semiconductor layer, the sidewall with described transparency conducting layer edge, the second semiconductor layer, luminescent layer and the first semiconductor layer on described isolation channel forms electric insulation layer.
8. manufacture method according to claim 7 is characterized in that, described electric insulation layer is reserved with the through hole that passes through for the electric connection line of finishing electrical connection.
9. according to the described manufacture method of claim l, it is characterized in that described step S40 specifically may further comprise the steps:
Step S41 is at unit formation first electrode of described the first semiconductor layer;
Step S42 forms the second electrode at described the second semiconductor layer; And
Step S43 finishes the electrical connection between the first electrode and the second electrode between each unit.
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| CN 201110069891 CN102176498B (en) | 2011-03-22 | 2011-03-22 | Manufacturing method of LED chip |
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| CN 201110069891 CN102176498B (en) | 2011-03-22 | 2011-03-22 | Manufacturing method of LED chip |
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| CN102176498A CN102176498A (en) | 2011-09-07 |
| CN102176498B true CN102176498B (en) | 2013-01-16 |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101925915B1 (en) * | 2011-10-24 | 2018-12-06 | 엘지이노텍 주식회사 | Light emitting device |
| CN103700741B (en) * | 2012-09-28 | 2017-01-18 | 上海蓝光科技有限公司 | Low-voltage power-type LED (Light-emitting Diode) with large current density and manufacture method thereof |
| CN104037296A (en) * | 2013-03-07 | 2014-09-10 | 百士杰企业有限公司 | Light-emitting element and manufacturing method thereof |
| CN103730431B (en) * | 2014-01-07 | 2018-08-17 | 宝钢金属有限公司 | A kind of high-power array LED chip surface radiator structure and production method |
| CN105023932B (en) * | 2014-04-29 | 2018-11-09 | 映瑞光电科技(上海)有限公司 | A kind of vertical LED array element that combination LED epitaxial structure is integrated with LED package substrate |
| WO2015196340A1 (en) * | 2014-06-23 | 2015-12-30 | 华为技术有限公司 | Chip heat dissipation structure and terminal device |
| CN105655450B (en) * | 2014-11-13 | 2019-01-18 | 北京北方华创微电子装备有限公司 | The passivation layer deposition method of high voltage LED chip |
| CN106206900A (en) * | 2015-05-08 | 2016-12-07 | 广东德力光电有限公司 | A kind of highlighted packed LED chip |
| CN105633224A (en) * | 2016-01-04 | 2016-06-01 | 厦门市三安光电科技有限公司 | LED chip electrode, LED chip structure and fabrication methods of LED chip electrode and LED chip structure |
| CN107768490B (en) * | 2017-10-26 | 2020-07-10 | 江苏新广联半导体有限公司 | Preparation method for optimizing performance of GaN-based L ED chip |
| CN111725251B (en) * | 2020-07-04 | 2023-04-21 | 深圳市惠合显示有限公司 | High-resolution full-color micro LED display |
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| JPH04196213A (en) * | 1990-11-27 | 1992-07-16 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH0537007A (en) * | 1991-07-26 | 1993-02-12 | Nikko Kyodo Co Ltd | Optical semiconductor device and manufacture thereof |
| JPH1154792A (en) * | 1997-07-30 | 1999-02-26 | Oki Electric Ind Co Ltd | Element isolation structure, element isolation method and light emitting element array |
| CN100386890C (en) * | 2004-04-05 | 2008-05-07 | 清华大学 | Method of mfg. GaN-base LED |
| CN101728322B (en) * | 2008-10-22 | 2012-03-21 | 晶元光电股份有限公司 | Method for manufacturing light-emitting component array |
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