CN102169936A - Graphical substrate and light-emitting diode (LED) chip - Google Patents
Graphical substrate and light-emitting diode (LED) chip Download PDFInfo
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- CN102169936A CN102169936A CN2011100429992A CN201110042999A CN102169936A CN 102169936 A CN102169936 A CN 102169936A CN 2011100429992 A CN2011100429992 A CN 2011100429992A CN 201110042999 A CN201110042999 A CN 201110042999A CN 102169936 A CN102169936 A CN 102169936A
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Abstract
The invention provides a graphical substrate and a light-emitting diode (LED) chip. The graphical substrate comprises a basic substrate, graphical bumps and a graphical bump mask, wherein the graphical bumps are arranged in an array form and formed on the basic substrate; and the graphical bump mask at least covers the tops of the graphical bumps. The LED chip comprises an epitaxial layer, a transparent conductive layer, a connection electrode and the graphical substrate which is provided by the invention, wherein the epitaxial layer and the transparent conductive layer are grown on the graphical substrate sequentially. The graphical substrate and the LED chip which are provided by the invention have the advantages that: a lateral epitaxial region is increased by arrangement of the graphical bump mask, and the light emitting efficiency of the LED chip is improved, so the photoelectric performance of the LED chip is improved.
Description
Technical field
The present invention relates to the led chip technical field of structures, relate in particular to a kind of graph substrate and led chip.
Background technology
Along with the development of semiconductor lighting technology, the white light luminous efficiency of light-emitting diode (Light Emitting Diode is called for short LED) has also obtained improving greatly.
Only being produced by solid material itself of semiconductor solid led light source, the refractive index n of these materials is all greater than 2, much larger than the refractive index (n=1) of air or free space.Therefore, mainly there are following three kinds of losses in led light source from the angle of light outgoing:
One, because the do not match reflection (Fresnel loss) that causes and of refractive index at the interface along the interface loss that existence caused of interface loss ripple;
Two, the total reflection in the medium: when a branch of light from optically denser medium when optically thinner medium is injected, if incidence angle greater than critical angle, will total reflection take place at the interface.The refractive index of supposing optically denser medium is n
2, the refractive index of optically thinner medium is n
1, critical angle θ then
cBe defined as θ
c=arcsin (n
1/ n
2).Because the existence of total reflection, (solid angle of this cone is 2 π (1-cos θ only to be limited in an outgoing cone
c)) light in the scope can propagate into optically thinner medium from optically denser medium, light emission rate equals (1-cos θ
c)/2 perhaps are approximately θ
c 2/ 4, perhaps be approximately (n more simply
1/ n
2)
2/ 4, this approximate data is at θ
cSet up when very little.
Three, medium absorbs: be not equal to zero absorption coefficient if propagation medium exists, then light intensity can be along with the decay of the propagation distance exponentially in medium, and attenuation function is exp (α t).
In the visible light led light source based on gallium nitride (GaN), the refractive index of luminescence medium InGaN has difference because of different indium components, but all greater than 2.46.This has only sub-fraction to penetrate from optically denser medium with regard to mean the light that produces in InGaN.For a film gallium nitride (GaN) visible light LED, light has two outgoing cones.Approximately having only in this light that just is equivalent in InGaN to be produced 8% can outgoing.At low light extraction efficiency owing to total reflection caused, prior art proposes several improving one's methods, as surface coarsening, reduce optical loss by reducing total reflection, the led chip chamfering, improve light emission rate by increasing light cone, and photonic crystal, light spontaneous radiation rate and light outgoing strengthened at specific wavelength.In the industrialization environment, graph substrate and transparency electrode indium tin oxide (Indium-Tin Oxide, be called for short ITO) film also all is the method for common lifting LED light extraction efficiency (Light Extraction Efficiency is called for short LEE).
Graph substrate and surface coarsening are similar, by the alligatoring optical interface, strengthen the light diffuse scattering, and the reduction total internal reflection is to the restriction of LEE.Graph substrate not only can promote LEE, also can increase internal quantum efficiency (Internal Quantum Efficiency is called for short IQE), graph substrate is the indispensable key technology of high efficiency LED, but in actual use, have the graph substrate technology now bigger limitation is arranged.
Graph substrate of the prior art mainly contains two kinds of forms, Figure 1A is a kind of graph substrate cross-sectional view of prior art, Figure 1B is the another kind of graph substrate cross-sectional view of prior art, shown in Figure 1A and Figure 1B, graph substrate comprises basic substrate 10 and is formed on the figure projection 101 on basic substrate 10 surfaces.The cross section of the figure projection 101 of the graph substrate shown in Figure 1A be shaped as triangle, the cross section of the figure projection 101 of the graph substrate shown in Figure 1B be shaped as truncation triangle or trapezoidal.
Graph substrate mainly is based on it in the early stage reinforcement horizontal extension effect of introducing of extension to the raising of epitaxial quality.To this, can do such understanding: threading dislocation tends to along the fastest direction growth of the speed of growth.If vertical-growth speed is much larger than cross growth speed, then threading dislocation substantially the vertical epitaxial laminar surface upwards penetrate.This is very disadvantageous, if threading dislocation passes luminescent layer, can directly introduce non-radiative luminescence center, thereby reduce luminous efficiency.Otherwise, if cross growth speed much larger than vertical-growth speed, then threading dislocation can be bent to towards horizontal direction and penetrate.The lateral penetration of dislocation is very favorable to the luminous efficiency that improves device, mainly shows following three aspects:
One, certain horizontal dislocation line in part position may discharge the stress between epitaxial loayer and substrate.
Two, this will increase the probability that meets between dislocation greatly, make dislocation reaction become possibility, and the dislocation of some Bo Gesi vector equal and opposite in direction opposite in signs may be buried in oblivion in pairs, thereby play the effect that reduces dislocation density on the whole.
Three, some dislocations may obtain chance and terminate on epitaxial loayer-substrate interface on the figure protrusion direction.
Fig. 2 A is the distribution schematic diagram of threading dislocation when carrying out epitaxial growth on the graph substrate shown in Figure 1A.Shown in Fig. 2 A, resilient coating 21 and epitaxial loayer 20 are formed on basic substrate 10 and the figure projection 101.The sidewall of figure projection 101 generally is to be made of High-Miiler-Index Surface, so the epitaxial growth along sidewall direction unlikely takes place.So just may form horizontal extension district 222 at figure projection 101 peripheries, partial dislocation obtains crooked in horizontal extension district 222 even buries in oblivion to form the dislocation loop 231 that ends at epitaxial loayer inside.Most of dislocation becomes threading dislocation 232.Because horizontal extension district 222 is very little, therefore the raising to crystal mass helps limited.
Fig. 2 B is the distribution schematic diagram of threading dislocation when carrying out epitaxial growth on the graph substrate shown in Figure 1B.Shown in Fig. 2 B, horizontal extension district 222 becomes littler, and the raising of crystal mass is helped still less.And,, when epitaxial loayer intersects up and down, might introduce new defective such as low angle boundary 233 etc. because figure projection 101 upper surfaces also provide an extra epitaxial surface.
Summary of the invention
The invention provides a kind of graph substrate and led chip,, improve the luminous efficiency of led chip, thereby improve the photoelectric properties of led chip to increase the horizontal extension district.
The invention provides a kind of graph substrate, comprise basic substrate and the figure projection that is formed on the array format on the described basic substrate, also comprise:
Figure projection mask, described figure projection mask covers the top of described figure projection at least.
Aforesaid graph substrate, wherein,
The material of described figure projection mask is mixture, silicon dioxide, silicon nitride or the titanium dioxide that silicon dioxide and titanium dioxide alternating deposit form.
Aforesaid graph substrate, wherein,
The thickness of described figure projection mask is the 100-2000 nanometer.
Aforesaid graph substrate, wherein,
The top width of described figure projection is not more than the bottom width of described figure projection, and the bottom width of described figure projection is the 1-10 micron, and the spacing between the described figure projection is the 2-5 micron, and the height of described figure projection is the 1-3 micron.
Aforesaid graph substrate, wherein,
The cross section of described figure projection be shaped as trapezoidal or triangle.
Aforesaid graph substrate, wherein,
The outer surface of described graph substrate is formed with nano projection and nanometer depression.
Aforesaid graph substrate, wherein,
The lateral dimension of described nano projection and described nanometer depression is the 30-100 nanometer, and longitudinal size is the 50-200 nanometer.
Aforesaid graph substrate, wherein,
The material of described basic substrate is sapphire, carborundum, silicon, GaAs, gallium nitride, aluminium nitride or spinelle, the material of described figure projection is identical with the material of described basic substrate, and the material of described figure projection is different with the material of described figure projection mask.
Aforesaid graph substrate, wherein,
The material of described figure projection is identical with the material of described figure projection mask, and the material of described figure projection mask is different with the material of described basic substrate.
The invention provides a kind of led chip, comprise epitaxial loayer, transparency conducting layer and connection electrode, also comprise: graph substrate provided by the invention;
Described epitaxial loayer and transparency conducting layer are grown on the described graph substrate successively.
Aforesaid led chip, wherein,
Described epitaxial loayer comprises N type conductive layer, luminescent layer and the P-type conduction layer that is grown in successively on the described graph substrate;
Be formed with at least one epitaxial loayer platform on the described epitaxial loayer, described N type conductive layer is exposed in the bottom surface of described epitaxial loayer platform;
Described connection electrode comprises N type electrode and P type electrode, and described N type electrode is connected with described N type conductive layer, and described P type electrode is connected with described transparency conducting layer.
Aforesaid led chip, wherein,
Described layer at transparent layer is formed with the transparency conducting layer projection of array format.
Graph substrate provided by the invention and led chip, setting by figure projection mask, the epitaxial loayer of growing on this graph substrate can be by the mode cover graphics projection mask of horizontal extension, threading dislocation can bend to towards horizontal direction and penetrate, increased the horizontal extension district, improve the luminous efficiency of led chip, thereby improve the photoelectric properties of led chip.
Description of drawings
Figure 1A is a kind of graph substrate cross-sectional view of prior art;
Figure 1B is the another kind of graph substrate cross-sectional view of prior art;
Fig. 2 A is the distribution schematic diagram of threading dislocation when carrying out epitaxial growth on the graph substrate shown in Figure 1A;
Fig. 2 B is the distribution schematic diagram of threading dislocation when carrying out epitaxial growth on the graph substrate shown in Figure 1B;
The graph substrate cross-sectional view that Fig. 3 A provides for the embodiment of the invention one;
The manufacturing process structural representation of the graph substrate that Fig. 3 B and Fig. 3 C provide for the embodiment of the invention one;
Threading dislocation structural representation in the epitaxial process on the graph substrate that Fig. 3 D provides for the embodiment of the invention one;
The graph substrate cross-sectional view that Fig. 4 A provides for the embodiment of the invention two;
Threading dislocation structural representation in the epitaxial process on the graph substrate that Fig. 4 B provides for the embodiment of the invention two;
The graph substrate cross-sectional view that Fig. 5 A provides for the embodiment of the invention three;
Threading dislocation structural representation in the epitaxial process on the graph substrate that Fig. 5 B provides for the embodiment of the invention three;
A kind of graph substrate cross-sectional view that Fig. 6 A provides for the embodiment of the invention four;
The another kind of graph substrate cross-sectional view that Fig. 6 B provides for the embodiment of the invention four;
A kind of led chip cross-sectional view that Fig. 7 A provides for the embodiment of the invention five;
The another kind of led chip cross-sectional view that Fig. 7 B provides for the embodiment of the invention five;
Another led chip cross-sectional view that Fig. 7 C provides for the embodiment of the invention five.
Reference numeral:
The basic substrate of 10-; 101-figure projection; The 20-epitaxial loayer;
The 21-resilient coating; The 231-dislocation loop; 222-horizontal extension district;
The 232-threading dislocation; The 233-low angle boundary; 10 '-substrate;
102-figure projection mask; 103-protects mask; 105-nanometer mask projection;
The 106-nano projection; 106 '-nanometer depression; 30-N type conductive layer;
The 40-luminescent layer; 50-P type conductive layer; The 60-transparency conducting layer;
The 70-passivation layer; 81-N type electrode; 82-P type electrode.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention is clearer,, the technical scheme in the embodiment of the invention is clearly and completely described below in conjunction with the embodiment of the invention.Need to prove that in accompanying drawing or specification, similar or components identical is all used identical Reference numeral.
The embodiment of the invention provides a kind of graph substrate, comprises basic substrate and the figure projection that is formed on the array format on the basic substrate, also comprises figure projection mask, and figure projection mask is the top of cover graphics projection at least.
In the present embodiment, the figure projection is array format, distributes as the hexagonal closs packing.Figure projection mask is the top of cover graphics projection at least, i.e. the outer surface of upper that figure projection mask can the cover graphics projection, whole outer surfaces that also can the cover graphics projection.
The graph substrate that the embodiment of the invention provides, setting by figure projection mask, the epitaxial loayer of growing on this graph substrate can be by the mode cover graphics projection mask of horizontal extension, threading dislocation can bend to towards horizontal direction and penetrate, increased the horizontal extension district, improve the luminous efficiency of led chip, thereby improve the photoelectric properties of led chip.
In the present embodiment, the material of basic substrate is specifically as follows sapphire (sapphire), carborundum (SiC), silicon (Si), GaAs (GaAs), gallium nitride (GaN), aluminium nitride (AN) or spinelle (MgAl
2O
4) wait and be applicable to AlN, GaN, AlGaN, InGaN, the epitaxially grown backing material of AlInGaN.Preferably, the material of figure projection is identical with the material of basic substrate, and the figure projection specifically can be carried out etching and be formed on basic substrate.
In the present embodiment, when the material of the material of figure projection and basic substrate was identical, the material of figure projection mask was different with the material of figure projection and basic substrate, and preferably, the material of the protruding mask of figure is silicon dioxide (SiO
2) and titanium dioxide (TiO
2) the alternating deposit mixture, the silicon dioxide (SiO that form
2), silicon nitride (SiN
x) or titanium dioxide (TiO
2).Silicon dioxide, silicon nitride and titanium dioxide all are the transparent materials high temperature resistant, that chemical property is stable, the material of figure projection mask can be the homogenous material of one of them, also can be for the multilayer material alternating deposit forms, as forming for 1-20 time by silicon dioxide and titanium dioxide alternating deposit.
In the present embodiment, preferably, the top width of figure projection is not more than the bottom width of figure projection, and the bottom width of figure projection is the 1-10 micron, preferably, the bottom width of figure projection is the 2-5 micron, and the spacing between the figure projection is the 2-5 micron, and the height of figure projection is the 1-3 micron.The top width of figure projection is specially the width of the top maximum of figure projection, and the bottom width of figure projection is specially the width of the bottom maximum of figure projection.
In the present embodiment, preferably, the thickness range of figure projection mask is the 100-2000 nanometer, as being the 100-300 nanometer.The figure projection mask that is formed by silicon dioxide and titanium dioxide alternating deposit, the thickness of every layer of silicon dioxide film or titanium dioxide film is specifically as follows the 50-100 nanometer.
In the present embodiment, the material of the material of figure projection and figure projection mask also can be identical, and the material of figure projection mask is different with the material of basic substrate, the figure projection also can directly be made of figure projection mask, need not basic substrate is carried out etching and forms the figure projection, simplified manufacture craft.This moment, the thickness of figure projection mask was preferably the 1000-2000 nanometer.
In the present embodiment, preferably, the cross section of figure projection be shaped as trapezoidal or triangle.The shape of the figure projection of graph substrate can be for multiple, and protruding for its cross section is leg-of-mutton cone or pyramid as figure, perhaps for its cross section is trapezoidal frustum or terrace with edge, the concrete shape of figure projection is not exceeded with present embodiment.The trapezoidal or leg-of-mutton graph substrate structure that is shaped as to the cross section of figure projection describes in detail by the following examples.
Embodiment one
The graph substrate cross-sectional view that Fig. 3 A provides for the embodiment of the invention one.As shown in Figure 3A, this graph substrate comprises basic substrate 10 and is formed on the figure projection 101 of the array format on the basic substrate 10 that being shaped as of the cross section of figure projection 101 is trapezoidal, the top surface of figure projection mask 102 cover graphics projectioies 101.The manufacturing process structural representation of the graph substrate that Fig. 3 B and Fig. 3 C provide for the embodiment of the invention one.Shown in Fig. 3 B and Fig. 3 C, the structure and the forming process of each level in the present embodiment are specifically as follows:
Shown in Fig. 3 B; at first; go up the corresponding thin layer of the protruding mask of deposition one deck and figure 102 at substrate 10 '; deposition one deck photoresist, metal (Ni on the thin layer corresponding again with figure projection mask 102; Au etc.) or silicon dioxide, silicon nitride, form the protection mask 103 of figure projection mask 102, so that figure projection mask 102 is played a protective role; then litho pattern is etched on the protection mask 103 and on the figure projection mask 102, shown in Fig. 3 C.By dry etching, as plasma (ICP) etching, or wet etching, as concentrated sulfuric acid SPA (H
2SiO
4+ H
3PO
4), substrate 10 ' is etched figure projection 101, not etched part is basic substrate 10 on the substrate.If protection mask 103 is photoresist, metal (Ni, Au etc.), then will protect mask 103 by dissolution with solvents again, can obtain LED graph substrate as shown in Figure 3A.
Threading dislocation structural representation in the epitaxial process on the graph substrate that Fig. 3 D provides for the embodiment of the invention one, shown in Fig. 3 D, graph substrate growing epitaxial layers 20 in the present embodiment, because 102 pairs of epitaxially grown inhibitory action of figure projection mask do not have direct epitaxial growth on figure projection mask 102.Epitaxial loayer 20 has covered figure projection mask 102 by the mode of horizontal extension, increased horizontal extension district 222 greatly, and then make dislocation in horizontal extension district 222, obtain crooked even bury in oblivion, formation ends at the dislocation loop 231 of epitaxial loayer 20 inside, and the quantity of minimizing threading dislocation 232, reduce its density, thereby significantly improve the crystal mass of epitaxial loayer 20.
Embodiment two
The graph substrate cross-sectional view that Fig. 4 A provides for the embodiment of the invention two, shown in Fig. 4 A, the figure projection 101 that this comprises basic substrate 10 and is formed on the array format on the basic substrate 10, the shape of the cross section of this graph substrate figure projection 101 also is trapezoidal, the difference of the graph substrate that this graph substrate and embodiment one provide is, whole outer surfaces of figure projection mask 102 cover graphics projectioies 101.
Threading dislocation structural representation in the epitaxial process on the graph substrate that Fig. 4 B provides for the embodiment of the invention two, shown in Fig. 4 B, graph substrate growing epitaxial layers 20 in the present embodiment, it is same because figure projection 101 masks to epitaxially grown inhibitory action, do not have direct epitaxial growth on figure projection mask 102.Epitaxial loayer 20 has covered figure projection mask 102 by the mode of horizontal extension, increased horizontal extension district 222 greatly, and then make dislocation in horizontal extension district 222, obtain crooked even bury in oblivion, formation ends at the dislocation loop 231 of epitaxial loayer 20 inside, and the quantity of minimizing threading dislocation 232, reduce its density, thereby significantly improve the crystal mass of epitaxial loayer 20.
Embodiment three
The graph substrate cross-sectional view that Fig. 5 A provides for the embodiment of the invention three, shown in Fig. 5 A, the figure projection 101 that this comprises basic substrate 10 and is formed on the array format on the basic substrate 10, the difference of the graph substrate that this graph substrate and embodiment two provide is, the cross section of this graph substrate figure projection 101 be shaped as triangle, whole outer surfaces of figure projection mask 102 cover graphics projectioies 101.
Threading dislocation structural representation in the epitaxial process on the graph substrate that Fig. 5 B provides for the embodiment of the invention three, in the process of graph substrate growing epitaxial layers 20 in the present embodiment, dislocation loop 231 that forms and threading dislocation 232 are shown in Fig. 5 B, increase the effect of the crystal mass of the raising epitaxial loayer 20 that horizontal extension district 222 produced owing to the setting of figure projection mask 102, identical with embodiment two, this repeats no more.
Further, can also be formed with the nano projection and the nanometer depression of the nano-scale of array format on the outer surface of the graph substrate in the foregoing description.Preferably, nano projection and nanometer depression are alternately in above-mentioned graph substrate surface distributed, the lateral dimension of nano projection and nanometer depression is the 30-300 nanometer, longitudinal size is the 50-200 nanometer, the longitudinal size of nano projection is the height of nano projection, and the longitudinal size of nanometer depression is the degree of depth of nanometer depression.Distance between nano projection/nanometer depression is the 30-300 nanometer, and nano projection and nanometer depression Two dimensional Distribution can be suitable two-dimensional lattices, pile up as the solid matter hexagon to distribute, and also can be distribution at random.Setting by nano projection and nanometer depression can reduce the total reflection of light, thereby improve light emission rate, further improves the photoelectric properties of led chip.Four pairs of these graph substrate structures describe in detail by the following examples.
Embodiment four
A kind of graph substrate cross-sectional view that Fig. 6 A provides for the embodiment of the invention four.As shown in Figure 6A, cross section with figure projection 101 is trapezoidal, the graph substrate of the whole outer surfaces of figure projection mask 102 cover graphics substrates is an example, can pass through dry etching, further etching nanometer mask projection 105 on figure projection mask 102, nanometer mask projection 105 is combined with micron-sized figure projection 101, improved internal quantum efficiency IQE and the external quantum efficiency EQE of LED, and then improved the light extraction efficiency of led chip.Graph substrate shown in Fig. 6 A can be made as follows: be deposition pattern projection mask 102 (not illustrating in the drawings) on the trapezoidal graph substrate at figure projection 101 cross sections at first, on figure projection mask 102, deposit the metallic nickel film (Ni) of 5-20 nanometer again, pass through high-temperature quick thermal annealing then, as 750-950 ℃ of short annealing 10-150 second, make the metallic nickel film shrink and form the metallic nickel ball that diameter is about the 30-300 nanometer through annealing.By dry etching, etching figure projection mask 102 forms nanometer mask projection 105 shown in Fig. 6 A, thereby obtains this LED graph substrate then.
The another kind of graph substrate cross-sectional view that Fig. 6 B provides for the embodiment of the invention four.Embodiment among Fig. 6 B can make on the basis of the graph substrate among Fig. 6 A.After obtaining the graph substrate shown in Fig. 6 A, further etching makes nanometer depression 106 ' be formed on (degree of depth of nanometer depression 106 ' is about the 50-200 nanometer) in the backing material.The place that nanometer mask projection 105 covers has obtained nano projection 106 through etching with after removing.This method is equally applicable to other common (figure) substrate surface is formed the making of nanoscale projection, is the similar of the nano projection 106 of other shapes for the cross section of figure projection 101, and this repeats no more.
Embodiment five
The embodiment of the invention five provides a kind of led chip, and this led chip comprises epitaxial loayer, transparency conducting layer and connection electrode, also comprises the graph substrate that any embodiment of the present invention provides, and epitaxial loayer and transparency conducting layer are grown on the LED graph substrate successively.
The led chip that present embodiment provides, the top cover graphics projection mask of the projection of figure at least of its graph substrate, Sheng Chang epitaxial loayer on this basis, increased the horizontal extension district, improved the crystal mass of epitaxial loayer, improve the luminous efficiency of led chip, thereby improve the photoelectric properties of led chip.
In the present embodiment, epitaxial loayer comprises N type conductive layer, luminescent layer and the P-type conduction layer that is grown in successively on the graph substrate.Be formed with at least one epitaxial loayer platform on the epitaxial loayer, N type conductive layer is exposed in the bottom surface of epitaxial loayer platform.Connection electrode comprises N type electrode and P type electrode, and N type electrode is connected with N type conductive layer, and P type electrode is connected with transparency conducting layer.Usually led chip also has passivation layer, and passivation layer specifically can cover the sidewall and the bottom of the top epitaxial loayer platform of transparency conducting layer, and the part surface of N type electrode and P type electrode.Passivation layer also can cover on the transparency conducting layer again, behind the sidewall and bottom of epitaxial loayer platform, passivation layer on transparency conducting layer is offered the first half grooves to expose transparency conducting layer again, and on the passivation layer of the bottom of epitaxial loayer platform, offer the second half grooves to expose N type conductive layer, in the first half grooves, P type electrode is set again, in the second half grooves, N type electrode is set.
In the present embodiment, preferably, layer at transparent layer is formed with the transparency conducting layer projection of array format, to reduce the total reflection of light, further improves the light extraction efficiency of led chip.
A kind of led chip cross-sectional view that Fig. 7 A provides for the embodiment of the invention five.Shown in Fig. 7 A, the graph substrate that the graph substrate of this led chip provides for embodiment one, the LED graph substrate specifically comprises the figure projection mask 102 of basic substrate 10, figure projection 101 and cover graphics convex top, and growth has epitaxial loayer and transparency conducting layer 60 successively on the basis of this LED graph substrate.Epitaxial loayer comprises N type conductive layer 30, luminescent layer 40 and the P-type conduction layer 50 that is grown in successively on the LED graph substrate.The material of N type conductive layer 30 can be the GaN of silicon doping, AlGaN, and the single or multiple lift of InGaN, the material of luminescent layer 40 can be the InGaN individual layers, or InGaN Multiple Quantum Well (MQW), as GaN/InGaN MQW.P-type layer can be the GaN that magnesium mixes, AlGaN, the single or multiple lift of InGaN.The material of transparency conducting layer 60 can be ITO, ZnO, Au/NiO
xDeng.One side of epitaxial loayer is formed with the epitaxial loayer platform, and N type conductive layer 30 is exposed in the bottom surface of epitaxial loayer platform.N type electrode 81 is arranged on the N type conductive layer 30 of epitaxial loayer platform bottom, is connected with N type conductive layer 30, and P type electrode 82 is arranged on the transparency conducting layer 60, is connected with transparency conducting layer 60.The surface of led chip also is coated with passivation layer 70, passivation layer 70 exposed portions serve N type electrodes 81 and part P type electrode 82.
The another kind of led chip cross-sectional view that Fig. 7 B provides for the embodiment of the invention five, shown in Fig. 7 B, the graph substrate that the graph substrate of this led chip provides for embodiment two, another led chip cross-sectional view that Fig. 7 C provides for the embodiment of the invention five, shown in Fig. 7 C, the graph substrate that the graph substrate of this led chip provides for embodiment four, the structure of these two kinds of led chips and the similar of above-mentioned led chip, this repeats no more.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that previous embodiment is put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (12)
1. a graph substrate comprises basic substrate and the figure projection that is formed on the array format on the described basic substrate, it is characterized in that, also comprises:
Figure projection mask, described figure projection mask covers the top of described figure projection at least.
2. graph substrate according to claim 1 is characterized in that:
The material of described figure projection mask is mixture, silicon dioxide, silicon nitride or the titanium dioxide that silicon dioxide and titanium dioxide alternating deposit form.
3. graph substrate according to claim 1 and 2 is characterized in that:
The thickness of described figure projection mask is the 100-2000 nanometer.
4. graph substrate according to claim 1 is characterized in that:
The top width of described figure projection is not more than the bottom width of described figure projection, and the bottom width of described figure projection is the 1-10 micron, and the spacing between the described figure projection is the 2-5 micron, and the height of described figure projection is the 1-3 micron.
5. graph substrate according to claim 1 and 2 is characterized in that:
The cross section of described figure projection be shaped as trapezoidal or triangle.
6. graph substrate according to claim 4 is characterized in that:
The outer surface of described graph substrate is formed with nano projection and nanometer depression.
7. graph substrate according to claim 6 is characterized in that:
The lateral dimension of described nano projection and described nanometer depression is the 30-100 nanometer, and longitudinal size is the 50-200 nanometer.
8. graph substrate according to claim 1 is characterized in that:
The material of described basic substrate is sapphire, carborundum, silicon, GaAs, gallium nitride, aluminium nitride or spinelle, the material of described figure projection is identical with the material of described basic substrate, and the material of described figure projection is different with the material of described figure projection mask.
9. graph substrate according to claim 1 is characterized in that:
The material of described figure projection is identical with the material of described figure projection mask, and the material of described figure projection mask is different with the material of described basic substrate.
10. a led chip comprises epitaxial loayer, transparency conducting layer and connection electrode, it is characterized in that, also comprises: the arbitrary described graph substrate of claim 1-9;
Described epitaxial loayer and transparency conducting layer are grown on the described graph substrate successively.
11. led chip according to claim 10 is characterized in that:
Described epitaxial loayer comprises N type conductive layer, luminescent layer and the P-type conduction layer that is grown in successively on the described graph substrate;
Be formed with at least one epitaxial loayer platform on the described epitaxial loayer, described N type conductive layer is exposed in the bottom surface of described epitaxial loayer platform;
Described connection electrode comprises N type electrode and P type electrode, and described N type electrode is connected with described N type conductive layer, and described P type electrode is connected with described transparency conducting layer.
12. led chip according to claim 11 is characterized in that:
Described layer at transparent layer is formed with the transparency conducting layer projection of array format.
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| CN102437258A (en) * | 2011-12-06 | 2012-05-02 | 上海蓝光科技有限公司 | Patterned substrate for controlling gallium nitride nucleating growth position and preparation method thereof |
| CN103208568A (en) * | 2013-04-01 | 2013-07-17 | 厦门市三安光电科技有限公司 | Nitride light-emitting diode and manufacturing method |
| CN103715323A (en) * | 2012-10-09 | 2014-04-09 | 晶元光电股份有限公司 | Luminescence apparatus |
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| CN105261682A (en) * | 2015-10-16 | 2016-01-20 | 山东元旭光电有限公司 | Sapphire composite substrate and preparing method thereof |
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| CN105355739A (en) * | 2015-10-23 | 2016-02-24 | 安徽三安光电有限公司 | Patterned substrate, preparation method and light-emitting diode |
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| CN107833944B (en) * | 2017-11-13 | 2019-06-14 | 湘能华磊光电股份有限公司 | A kind of LED epitaxial layer structure and its growing method |
| CN108598232A (en) * | 2018-01-19 | 2018-09-28 | 浙江大学 | A kind of sapphire pattern substrate structure improving GaN base LED luminous efficiencies |
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