KR101360882B1

KR101360882B1 - Nitride semiconductor device and method of manufacturing the same

Info

Publication number: KR101360882B1
Application number: KR1020070082918A
Authority: KR
Inventors: 최석범; 백두고; 장태성; 우종균
Original assignee: 삼성전자주식회사
Priority date: 2007-08-17
Filing date: 2007-08-17
Publication date: 2014-02-12
Also published as: KR20090018458A

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride semiconductor device and a method of manufacturing the same, and in particular, an n-type cladding layer formed on the substrate, the upper surface of which has surface irregularities, and a portion of the surface irregularities of the n-type cladding layer. On the active layer formed along the profile of the surface irregularities, the p-type cladding layer formed on the active layer, the p-type electrode formed on the p-type cladding layer and the n-type cladding layer on which the active layer is not formed. It provides a nitride semiconductor element comprising an n-type electrode formed in the.

The present invention also provides a method of manufacturing the nitride semiconductor device.

Nitride, Luminous Efficiency, Operating Voltage, Quantum Well, Surface Unevenness

Description

Nitride semiconductor device and its manufacturing method {NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device such as a light emitting diode (LED), a laser diode (LD), a light emitting device such as a solar cell, an optical sensor, or a nitride semiconductor device used for electronic devices such as transistors and power devices.

Recently, III-V nitride semiconductors such as GaN have been spotlighted as core materials of light emitting devices such as light emitting diodes (LEDs) or laser diodes (LDs) due to their excellent physical and chemical properties. LEDs or LDs using III-V nitride semiconductor materials are widely used in light emitting devices for obtaining light in the blue or green wavelength band, and these light emitting devices are applied to light sources of various products such as electronic displays and lighting devices. The III-V nitride semiconductor is generally made of a GaN-based material having a composition formula of In _X Al _Y Ga ₁ _-X- _Y N (0≤X, 0≤Y, X + Y≤1).

Next, a conventional nitride semiconductor device (LED) using a III-V nitride semiconductor as described above will be described in detail with reference to FIG. 1.

1 is a cross-sectional view schematically showing the structure of a nitride semiconductor device according to the prior art.

As shown in FIG. 1, an LED device using a nitride semiconductor according to the related art includes a buffer layer 110 made of GaN, an n-type cladding layer 120, and a single quantum well SQW on a light transmissive substrate 100. An active layer 130 and a p-type cladding layer 140 having a multi-quantum well (MQW) structure containing InGaN or InGaN having a structure are sequentially stacked.

In addition, since some regions of the p-type cladding layer 140 and the active layer 130 are removed by some mesa etching process, some top surfaces of the n-type cladding layer 120 are exposed.

An n-type electrode 170 is formed on the exposed n-type cladding layer 120, and a transparent conductor layer 150 made of ITO or the like is formed on the p-type cladding layer 160. It is formed in a stacked structure.

As described above, the nitride semiconductor device may adopt a double heterostructure having an active layer 130 having a single quantum well or a multiple quantum well structure having a well layer made of InGaN.

By the way, when the active layer has a multi-quantum well structure, high luminous efficiency and luminous intensity can be obtained, but it is still limited in luminous efficiency and luminous intensity, i.e., light output, to use a nitride semiconductor element as a light source for illumination or an outdoor display. There is.

Therefore, there is a continuous demand for development of a nitride semiconductor device related technology capable of improving the light emitting efficiency and light output of the nitride semiconductor device.

An object of the present invention is to provide a nitride semiconductor device that can lower the operating voltage (V _f ) by increasing the area of the quantum well structure of the active layer to increase the luminous efficiency in order to solve the above problems.

Another object of the present invention is to provide a method of manufacturing the above-mentioned nitride semiconductor device.

In order to achieve the above object, the present invention provides a substrate, an n-type cladding layer formed on the substrate, the upper surface having a surface irregularities, and a profile of the surface irregularities on a portion of the surface irregularities of the n-type cladding layer; The active layer formed along with the p-type cladding layer formed on the active layer, the p-type electrode formed on the p-type cladding layer and the n-type cladding layer on which the active layer is not formed. It provides a nitride semiconductor device comprising a type electrode.

In the nitride semiconductor device of the present invention, the surface irregularities are preferably formed in a hemispherical or polygonal shape, and the hemispherical surface irregularities have a hemispherical surface having an inclination angle of 30 ° or less with respect to the n-type cladding layer surface. More preferably.

Further, in the nitride semiconductor device of the present invention, it is preferable to further include a buffer layer formed at the interface between the substrate and the n-type cladding layer.

In the nitride semiconductor device of the present invention, the hemispherical surface irregularities preferably have a diameter in the range of 2 μm to 20 μm.

In addition, in the nitride semiconductor device of the present invention, the surface irregularities are preferably located in the range of 20% to 60% of the total area of the n-type cladding layer.

In order to achieve the above object another object of the present invention is to form an n-type cladding layer on a substrate, to form a surface irregularities by etching a portion of the upper surface of the n-type cladding layer, and on the n-type cladding layer Forming an active layer along the profile of the surface unevenness, forming a p-type cladding layer on the active layer, mesa-etching a portion of the p-type cladding layer, the active layer and the n-type cladding layer to form the n-type Exposing a portion of an upper surface of the clad layer, forming an n-type electrode on the exposed n-type cladding layer, and forming a p-type electrode on the p-type cladding layer. It provides a manufacturing method.

In addition, in the method of manufacturing the nitride semiconductor device of the present invention, the etching process for forming the surface irregularities is preferably carried out using any one selected from dry etching or wet etching.

In the method of manufacturing the nitride semiconductor device of the present invention, the surface irregularities are preferably formed in a hemispherical or polygonal shape, more specifically, the hemispherical surface irregularities have a hemispherical surface of 30 with respect to the n-type cladding layer surface. It is preferable to form so that it may have an inclination angle of degrees or less.

In addition, in the method of manufacturing the nitride semiconductor device of the present invention, it is preferable to further include forming a buffer layer on the substrate before the step of forming the n-type clad layer on the substrate.

The present invention can increase the area of the quantum well structure of the active layer that can be formed in the unit area to lower the operating voltage (V _f ), to increase the luminous efficiency to secure high output characteristics.

Details of the technical configuration of the nitride semiconductor device and the manufacturing method of the present invention will be clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Throughout the specification, similar parts have been given the same reference numerals.

Structure of Nitride Semiconductor Device

Referring to Figure 2 will be described in detail with respect to the structure of the nitride semiconductor device according to an embodiment of the present invention.

2 is a cross-sectional view illustrating a structure of a nitride semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2, the nitride semiconductor device according to the embodiment of the present invention includes a substrate 100 that is light transmissive, a buffer layer 110, an n-type cladding layer 120, The active layer 130 and the p-type cladding layer 140 includes a light emitting structure formed by sequentially stacked, in particular, the upper surface of the n-type cladding layer 120 according to the present invention has a surface irregularities (120a), Accordingly, the active layer 130 positioned thereon is also formed to have the same profile as the profile of the surface irregularities 120a of the n-type cladding layer 120.

The substrate 100 is preferably formed using a transparent material including sapphire. In addition to sapphire, the substrate 100 may be formed of zinc oxide (ZnO), gallium nitride (GaN), silicon carbide (SiC), and aluminum nitride (AlN).

The buffer layer 110 is a layer for improving lattice matching with the substrate 100 before growing the n-type cladding layer 120, and is generally formed of a nitride including GaN or Ga. It may be omitted depending on the characteristics of the device and the process conditions.

The n-type and p-type cladding layers 120 and 140 and the active layer 130 have an In _X Al _Y Ga _1- _X- _Y N composition formula (where 0 ≦ X, 0 ≦ Y, and X + Y ≦ 1). It may be made of a semiconductor material having.

More specifically, the n-type nitride semiconductor layer 120 may be formed of a GaN layer or a GaN / AlGaN layer doped with n-type conductive impurities, for example, Si, Ge, Sn Etc. are used, and preferably Si is mainly used. In addition, the n-type cladding layer 120 has surface irregularities 120a formed in a hemispherical shape or a polygonal shape on an upper surface thereof. In this embodiment, the surface irregularities 120a of a hemispherical shape are shown in FIG. .

In addition, the hemispherical surface irregularities 120a are formed to have an inclination angle of 30 ° or less with respect to the n-type cladding layer 120 surface of the hemispherical surface in contact with the n-type cladding layer 120 surface. This is to maintain a uniform profile of the active layer 130 formed thereon.

In addition, the hemispherical surface irregularities 120a have a diameter in a range of 2 μm to 20 μm, and are formed to be positioned in a range of 20% to 60% of the total area of the n-type cladding layer 120.

Therefore, the active layer 130 is formed with the same profile as the surface unevenness 120a profile of the n-type cladding layer 120, thereby increasing the area of the quantum well structure corresponding to the unit area and lowering the driving voltage. The luminous efficiency can be improved.

The active layer 130 may have a multi-quantum well structure or a single quantum well structure in which a plurality of quantum well layers and a plurality of quantum barrier layers are alternately stacked.

The p-type cladding layer 140 may be formed of a GaN layer or a GaN / AlGaN layer doped with p-type conductive impurities. For example, Mg, Zn, Be, or the like may be used as the p-type conductive impurities. Preferably, Mg is mainly used.

A portion of the p-type cladding layer 140 and the active layer 130 are removed by mesa etching to expose a portion of the n-type cladding layer 120 disposed on the bottom surface.

A predetermined portion of the n-type nitride semiconductor layer 120 exposed by the mesa etching is formed with an n-type electrode 160 that serves as a reflection and an electrode at the same time, the current is applied to the p-type nitride semiconductor layer 140 The transparent conductor layer 150 and the p-type electrode 160 for diffusing are sequentially formed.

The transparent conductor layer 150 is an indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO) as a layer for increasing a current injection area to improve a current diffusion effect. ) And TCO (Transparent Conductive Oxide) is preferably made of any one film selected from the group consisting of.

Method of manufacturing nitride semiconductor device

A method of manufacturing a nitride semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS. 3A to 3D and FIG. 2 described above.

3A to 3D are cross-sectional views sequentially illustrating a method of manufacturing a nitride semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 3A, an n-type cladding layer 120 having a buffer layer 110 and surface irregularities 120a formed on an upper surface thereof is sequentially formed on the substrate 100.

Here, the substrate 100 is preferably formed using a transparent material including sapphire, in addition to sapphire, the substrate 110 is zinc oxide (ZnO), gallium nitride (GaN) , Silicon carbide (SiC) and aluminum nitride (AlN).

The buffer layer 110 is a layer for improving lattice matching between the substrate 100 and the n-type cladding layer 120, and may further form a GaN-based or SiC-based buffer layer, which may be applied to process conditions and device characteristics. It can be omitted accordingly.

The n-type cladding layer 120 may be a semiconductor material having an Al _x In _y Ga _(1-xy) N composition formula, where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and 0 ≦ x + y ≦ 1. It may be formed through a known nitride deposition process, such as organometallic chemical vapor deposition process.

More specifically, the n-type cladding layer 120 having the surface unevenness 120a formed on the upper surface of the n-type cladding layer 120 is first formed of a GaN layer or a GaN / AlGaN layer doped with n-type conductive impurities. Next, a portion of the upper surface of the n-type cladding layer 120 is removed by a wet or dry etching process to form surface irregularities 120a. In this case, the surface unevenness 120a serves to increase the area of the active layer 130, which will be described later, and may be formed in a hemispherical or polygonal shape according to process conditions and device characteristics.

However, in consideration of the growth uniformity of the active layer 130 to be formed on the n-type cladding layer 120 having the surface unevenness 120a, the surface unevenness 120a is preferably formed in a hemispherical shape. It is more preferable to form a surface of the hemisphere surface in contact with the surface of the n-type cladding layer 120 with an inclination angle of 30 ° or less with respect to the surface of the type cladding layer 120.

In addition, the hemispherical surface irregularities 120a have a diameter in the range of 2 μm to 20 μm in order to increase the area of the active layer to be formed by a subsequent process, and 20 to 20% of the total area of the n-type cladding layer 120. It is preferred to form it in the 60% range.

3B, the active layer 130 and the p-type cladding layer 140 are sequentially formed on the n-type cladding layer 120 on which the surface irregularities 120a are formed. In this case, the active layer 130 and the p-type cladding layer 140 are formed to have the same profile by the surface irregularities 120a of the n-type cladding layer 120 disposed below. That is, the luminous efficiency may be improved by increasing the area of the active layer 130 that can be formed per unit area.

The active layer 130 and the p-type cladding layer 140 have an Al _x In _y Ga _(1-xy) N composition formula, where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and 0 ≦ x + y ≦ 1. It may be a semiconductor material having, and may be formed through a known nitride deposition process, such as organometallic chemical deposition process.

Subsequently, as shown in FIG. 3C, some regions of the p-type cladding layer 140, the active layer 130, and the n-type cladding layer 120 are removed to expose some regions of the n-type cladding layer 120. A mesa etching process is performed.

3D, the transparent conductor layer 150 and the p-type electrode 160 for diffusing current are sequentially formed on the p-type cladding layer 140.

Next, the present invention forms the n-type electrode 170 on the exposed n-type cladding layer 120 as shown in FIG.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also within the scope of the present invention.

1 is a cross-sectional view showing the structure of a nitride semiconductor device according to the prior art.

2 is a cross-sectional view showing a structure of a nitride semiconductor device according to an embodiment of the present invention.

3A through 3D are cross-sectional views sequentially illustrating a method of manufacturing a nitride semiconductor device according to an embodiment of the present invention.

100 substrate 110 buffer layer

120: n-type cladding layer 120a: surface irregularities

130: active layer 140: p-type cladding layer

150: transparent conductive layer 160: p-type electrode

170: n-type electrode

Claims

Board;

An n-type cladding layer formed on the substrate, the upper surface having an uneven surface;

An active layer formed along a profile of the surface irregularities on a portion of the surface irregularities of the n-type cladding layer;

A p-type cladding layer formed on the active layer;

A p-type electrode formed on the p-type cladding layer; And

And an n-type electrode formed on the n-type cladding layer in which the active layer is not formed.

The surface irregularities are formed in a hemispherical shape, the hemispherical surface irregularities are nitrides, characterized in that the surface in contact with the n-type cladding layer surface of the hemispherical surface with respect to the n-type cladding layer surface having an inclination angle of 30 ° or less Semiconductor device.

The method of claim 1,

And a buffer layer formed at an interface between the substrate and the n-type cladding layer.

The method of claim 1,

The hemispherical surface irregularities are nitride semiconductor device, characterized in that having a diameter in the range of 2㎛ 20㎛.

The method of claim 1,

The surface irregularities are nitride semiconductor device, characterized in that located in the range of 20% to 60% of the total area of the n-type cladding layer.

Forming an n-type cladding layer on the substrate;

Etching a portion of the upper surface of the n-type clad layer to form surface irregularities;

Forming an active layer along the profile of the surface irregularities on the n-type cladding layer;

Forming a p-type cladding layer on the active layer;

Mesa-etching a portion of the p-type cladding layer, an active layer, and an n-type cladding layer to expose a portion of the upper surface of the n-type cladding layer;

Forming an n-type electrode on the exposed n-type cladding layer; And

Forming a p-type electrode on the p-type cladding layer;

The surface irregularities are formed in a hemispherical shape, wherein the hemispherical surface irregularities are formed such that the surface of the hemispherical surface in contact with the surface of the n-type cladding layer has an inclination angle of 30 ° or less with respect to the surface of the n-type cladding layer. Method of manufacturing nitride semiconductor device.

The method of claim 5,

The etching process for forming the surface irregularities is a method of manufacturing a nitride semiconductor device, characterized in that the progress using any one selected from dry etching or wet etching.

The method of claim 5,

Prior to forming an n-type cladding layer on the substrate,

And forming a buffer layer on the substrate.

The method of claim 5,

The hemispherical surface irregularities are formed to have a diameter in the range of 2㎛ 20㎛.

The method of claim 5,

The surface irregularities are formed to be positioned in the range of 20% to 60% of the total area of the n-type cladding layer.

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