CN102169831B - Manufacturing method of silicon-on-insulator lateral insulated-gate bipolar transistor (SOI LIGBT) device unit of lateral channel with positive (p) buried layer - Google Patents
Manufacturing method of silicon-on-insulator lateral insulated-gate bipolar transistor (SOI LIGBT) device unit of lateral channel with positive (p) buried layer Download PDFInfo
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- CN102169831B CN102169831B CN 201110056336 CN201110056336A CN102169831B CN 102169831 B CN102169831 B CN 102169831B CN 201110056336 CN201110056336 CN 201110056336 CN 201110056336 A CN201110056336 A CN 201110056336A CN 102169831 B CN102169831 B CN 102169831B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000012212 insulator Substances 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 12
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 12
- 238000009826 distribution Methods 0.000 claims abstract description 9
- 230000003139 buffering effect Effects 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- 238000003466 welding Methods 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005538 encapsulation Methods 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 abstract 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
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Abstract
The invention relates to a manufacturing method of a silicon-on-insulator lateral insulated-gate bipolar transistor (SOI LIGBT) device unit of a lateral channel with a positive (p) buried layer. An SOI LIGBT device which is manufactured by the conventional method is abruptly degraded or even invalid in a high-temperature and large-current environment. In the method provided by the invention, the SOI LIGBT device is manufactured by using an SOI material with a p-buried layer; a reverse bias pn junction which is formed by the p-buried layer with reverse impurity concentration distribution and a negative (n) top-layer semiconductor with forward impurity concentration distribution is used for longitudinal voltage resistance; and the SOI LIGBT device unit of the lateral channel with the p buried layer is manufactured by etching for nine times and oxidation twice. The device unit which is manufactured by the method improves the longitudinal voltage resistance of the device under the condition of reducing the thickness of a buried oxidation layer, reduces a self-heating effect, improves the thermal property of the device and improves the reliability of the device.
Description
Technical field
The invention belongs to technical field of semiconductors, relate to the silicon on a kind of lateral channel SOI(insulating barrier of the p of having buried regions) the LIGBT(lateral insulated gate bipolar transistor) the SOI CMOS VLSI process implementation method of device cell.
Background technology
SOI LIGBT device is owing to its less volume, weight, higher working temperature and stronger Radiation hardness, lower cost and higher reliability have extensive use as contactless power electronic switching or analog line driver in the technology such as intelligent electric power electronics, hot environment power electronics, space power electronics and vehicles power electronics.SOI CMOS VLSI technology because its technical maturity is high, the medium isolation performance is good, isolation technology is simple, be convenient to three-dimensional integrated, be convenient to micro photo-electro-mechanical and power and radio frequency monolithic system integrated, be convenient to improve the advantages such as integration density and integrated performance, make at VLSI, SOC(monolithic integrated system) make, SPIC(intelligent power integrated system) make and TDS(three-dimensional integrated system) field such as manufacturing has extensive use.
How existing SOI LIGBT device is by SOI CMOS VLSI fabrication techniques, and its process is as follows:
1. the certain depth place forms buried insulating barrier under a side surface of certain doping type silicon wafer, this silicon wafer is isolated into two semiconductor regions fully, wherein, a thicker side is as substrate, and a thinner side is used for making device and circuit as the top layer semiconductor;
With polished top layer semiconductor through the oxidation first time, for the first time nitrogenize, etching forms the isolated area window, the top layer semiconductor in the isolated area is adopted LOCOS(carrying out local oxide isolation technique for the first time) remove, forming the isolating oxide layer that isolated insulation layer and buried insulating barrier are combined as a whole, is several silicon island with the top layer semiconductor isolation;
3. enough distances of being separated by in the silicon island etch and are parallel to each other but perpendicular to the window of isolated insulation layer, mix the impurity identical with the requirement of top layer semiconductor conductivity types by window, obtain the higher semiconductor regions identical with the top layer semiconductor conductivity types of a kind of concentration as buffering area, and remove top layer semiconductor surface insulating barrier;
4. with for the second time oxidation of top layer semiconductor, etching forms and is parallel to each other and perpendicular to the window of isolated insulation layer, wherein half is positioned at buffering area for the third time, second half forms field oxide isolator between two adjacent windows between buffering area.And then carry out thin oxide gate and form gate oxide, depositing polysilicon, the 4th time etching forms polysilicon gate, field plate and interconnection line, the 5th time etching forms trap doping window, then carries out trap dopant implant and high annealing and advances formation the well region with certain impurities concentration distribution opposite with the top layer semiconductor conductivity types and the anode region that is positioned within the buffering area;
5. carry out the 6th etching and form source area doping window in the well region, formation and well region and opposite source area mix and anneal;
6. carry out the 7th etching and form well region ohmic contact doping window and anode region ohmic contact doping window, and mix and short annealing forms the ohmic contact heavy doping in these two kinds of zones, conduction type is identical with well region;
7. carry out the 8th etching and form contact conductor contact hole window, then carry out metallic film growth or deposit, and carry out etching formation metal electrode lead-in wire, Metal field plate, metal interconnecting wires and pressure welding point the 9th time;
8. deposit passivation layer, etching metal crimp solder joint contact window carries out pin pressure welding and encapsulation.
The SOI material that these SOI LIGBT devices adopt mostly is thick buried oxidation layer, vertical single thin top layer semiconductor SOI material of doping type.The vertical withstand voltage main of this class SOI LIGBT device born by thick buried oxidation layer.Because the thermal conductivity of oxide layer is very low, thickness is very large again, bring the serious radiating condition requirement from heating problems and harshness for this class high pressure, large electric current, high-power component, device must be installed heavy radiator in the process of using, be unfavorable for very much saving resource, energy-saving and cost-reducing, protection of the environment; Simultaneously, thin top layer semiconductor becomes the bottleneck that reduces SOI LIGBT device on state resistance, and limiting device is withstand voltage and the further raising of current capacity density, and the improvement of device architecture, has seriously hindered the development of device products, technology and industry.
Summary of the invention
The object of the invention is to for the deficiencies in the prior art, a kind of manufacture method of lateral channel SOI LIGBT device cell of the p of having buried regions is provided.
The inventive method may further comprise the steps:
1. adopt the thick film SOI disk, the buried insulating barrier of intermediate thin is isolated Semiconductor substrate and buried p-type layer fully, and the upper surface of buried p-type layer is covered fully by N-shaped top layer semiconductor.Wherein, buried p-type layer has reverse impurities concentration distribution, and the N-shaped top layer semiconductor of Uniform Doped is used for making device and circuit.
With polished N-shaped top layer semiconductor through the oxidation first time, for the first time nitrogenize, etching forms the isolated area window for the first time, N-shaped top layer semiconductor in the isolated area is adopted DTI(deep trench isolation technology) remove, forming the isolating oxide layer that isolated insulation layer and buried insulating barrier are combined as a whole, is a plurality of silicon island with N-shaped top layer semiconductor isolation.
3. etch in the silicon island and be parallel to each other and perpendicular to the window of isolated insulation layer, mix the impurity identical with the requirement of N-shaped top layer semiconductor conductivity types by window, obtain the higher semiconductor regions identical with N-shaped top layer semiconductor conductivity types of a kind of concentration as buffering area, and remove the exposed insulating barrier of top layer semiconductor surface.
4. with for the second time oxidation of top layer semiconductor, etching forms and is parallel to each other and perpendicular to the window of isolated insulation layer, wherein half is positioned at buffering area for the third time, second half forms field oxide isolator between two adjacent windows between buffering area; Carry out thin oxide gate and form gate oxide, depositing polysilicon, form polysilicon gate in the window that the 4th time is etched between buffering area, field oxide isolator upper surface sub-fraction at next-door neighbour's polysilicon gate forms polysilicon gate field plate and the polysilicon interconnection line that is connected as a single entity with polysilicon gate, the 5th time etching forms trap doping window, then carries out forming the well region with certain impurities concentration distribution opposite with N-shaped top layer semiconductor conductivity types and the anode region that is positioned within the buffering area in the window of trap dopant implant and high annealing propelling between buffering area.
5. carry out the 6th etching and form the interior source area doping window of well region, form simultaneously the anode in short circuit point doping window within the anode region, carry out the heavy doping opposite with the anode region dopant type with well region, and annealing formation heavy doping source region and the heavy doping anode in short circuit point that runs through the anode region, conduction type is opposite with well region.
6. carry out the 7th etching and form well region ohmic contact doping window and anode region ohmic contact doping window, and carrying out the heavy doping ohmic contact that the heavy doping identical with the anode region dopant type with well region and rapid thermal annealing form these two kinds of zones, conduction type is identical with well region.
7. carry out the 8th etching and form contact conductor contact hole window, then carry out metallic film growth or deposit, and carry out etching formation metal electrode lead-in wire, Metal field plate, metal interconnecting wires and pressure welding point the 9th time.
8. deposit passivation layer, etching metal crimp solder joint contact window carries out pin pressure welding and encapsulation.
The lateral channel SOI LIGBT device cell with p buried regions that the inventive method is made significantly improves the vertically withstand voltage of SOI LIGBT, and obviously reduce self-heating effect to the impact of device performance, reduce to adopt volume, weight and the cost of the various power electronic systems of this device, and improve the SOI LIGBT device products of system reliability.
Embodiment
Have the manufacture method of the lateral channel SOI LIGBT device cell of p buried regions, may further comprise the steps:
1. adopt the thick film SOI disk, the buried insulating barrier of intermediate thin is isolated Semiconductor substrate and buried p-type layer fully, and the upper surface of buried p-type layer is covered fully by N-shaped top layer semiconductor.Wherein, buried p-type layer has reverse impurities concentration distribution, and the N-shaped top layer semiconductor of Uniform Doped is used for making device and circuit.
With polished N-shaped top layer semiconductor through the oxidation first time, for the first time nitrogenize, etching forms the isolated area window for the first time, N-shaped top layer semiconductor in the isolated area is adopted DTI(deep trench isolation technology) remove, forming the isolating oxide layer that isolated insulation layer and buried insulating barrier are combined as a whole, is a plurality of silicon island with N-shaped top layer semiconductor isolation.
3. etch in the silicon island and be parallel to each other and perpendicular to the window of isolated insulation layer, mix the impurity identical with the requirement of N-shaped top layer semiconductor conductivity types by window, obtain the higher semiconductor regions identical with N-shaped top layer semiconductor conductivity types of a kind of concentration as buffering area, and remove the exposed insulating barrier of top layer semiconductor surface.
4. with for the second time oxidation of top layer semiconductor, etching forms and is parallel to each other and perpendicular to the window of isolated insulation layer, wherein half is positioned at buffering area for the third time, second half forms field oxide isolator between two adjacent windows between buffering area; Carry out thin oxide gate and form gate oxide, depositing polysilicon, form polysilicon gate in the window that the 4th time is etched between buffering area, field oxide isolator upper surface sub-fraction at next-door neighbour's polysilicon gate forms polysilicon gate field plate and the polysilicon interconnection line that is connected as a single entity with polysilicon gate, the 5th time etching forms trap doping window, then carries out forming the well region with certain impurities concentration distribution opposite with N-shaped top layer semiconductor conductivity types and the anode region that is positioned within the buffering area in the window of trap dopant implant and high annealing propelling between buffering area.
5. carry out the 6th etching and form the interior source area doping window of well region, form simultaneously the anode in short circuit point doping window within the anode region, carry out the heavy doping opposite with the anode region dopant type with well region, and annealing formation heavy doping source region and the heavy doping anode in short circuit point that runs through the anode region, conduction type is opposite with well region.
6. carry out the 7th etching and form well region ohmic contact doping window and anode region ohmic contact doping window, and carrying out the heavy doping ohmic contact that the heavy doping identical with the anode region dopant type with well region and rapid thermal annealing form these two kinds of zones, conduction type is identical with well region.
7. carry out the 8th etching and form contact conductor contact hole window, then carry out metallic film growth or deposit, and carry out etching formation metal electrode lead-in wire, Metal field plate, metal interconnecting wires and pressure welding point the 9th time.
8. deposit passivation layer, etching metal crimp solder joint contact window carries out pin pressure welding and encapsulation.
Claims (1)
1. have the manufacture method of the lateral channel SOI LIGBT device cell of p buried regions, it is characterized in that the concrete steps of the method are:
Step (1) adopts the thick film SOI disk, and the buried insulating barrier of intermediate thin is isolated Semiconductor substrate and buried p-type layer fully, and the upper surface of buried p-type layer is covered fully by N-shaped top layer semiconductor; Wherein, buried p-type layer has reverse impurities concentration distribution, and the N-shaped top layer semiconductor of Uniform Doped is used for making device and circuit;
Step (2) with polished N-shaped top layer semiconductor through the oxidation first time, for the first time nitrogenize, etching forms the isolated area window for the first time, adopt the deep trench isolation technology to remove the N-shaped top layer semiconductor in the isolated area, forming the isolating oxide layer that isolated insulation layer and buried insulating barrier are combined as a whole, is a plurality of silicon island with N-shaped top layer semiconductor isolation;
Step (3) etches in the silicon island and is parallel to each other and perpendicular to the window of isolated insulation layer, mix the impurity identical with the requirement of N-shaped top layer semiconductor conductivity types by window, obtain the higher semiconductor regions identical with N-shaped top layer semiconductor conductivity types of a kind of concentration as buffering area, and remove the exposed insulating barrier of top layer semiconductor surface;
Step (4) is with for the second time oxidation of top layer semiconductor, etching forms and is parallel to each other and perpendicular to the window of isolated insulation layer for the third time, wherein half is positioned at buffering area, second half forms field oxide isolator between two adjacent windows between buffering area; Carry out thin oxide gate and form gate oxide, depositing polysilicon, form polysilicon gate in the window that the 4th time is etched between buffering area, field oxide isolator upper surface sub-fraction at next-door neighbour's polysilicon gate forms polysilicon gate field plate and the polysilicon interconnection line that is connected as a single entity with polysilicon gate, the 5th time etching forms trap doping window, then carries out forming the well region with certain impurities concentration distribution opposite with N-shaped top layer semiconductor conductivity types and the anode region that is positioned within the buffering area in the window of trap dopant implant and high annealing propelling between buffering area;
Step (5) is carried out the 6th etching and is formed the interior source area doping window of well region, form simultaneously the anode in short circuit point doping window within the anode region, carry out the heavy doping opposite with the anode region dopant type with well region, and annealing formation heavy doping source region and the heavy doping anode in short circuit point that runs through the anode region, conduction type is opposite with well region;
Step (6) is carried out the 7th etching and is formed well region ohmic contact doping window and anode region ohmic contact doping window, and carrying out the heavy doping ohmic contact that the heavy doping identical with the anode region dopant type with well region and rapid thermal annealing form these two kinds of zones, conduction type is identical with well region;
Step (7) is carried out the 8th etching and is formed contact conductor contact hole window, then carries out metallic film growth or deposit, and carries out etching formation metal electrode lead-in wire, Metal field plate, metal interconnecting wires and pressure welding point the 9th time;
Step (8) deposit passivation layer, etching metal crimp solder joint contact window carries out pin pressure welding and encapsulation.
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| CN 201110056336 CN102169831B (en) | 2011-03-10 | 2011-03-10 | Manufacturing method of silicon-on-insulator lateral insulated-gate bipolar transistor (SOI LIGBT) device unit of lateral channel with positive (p) buried layer |
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| CN 201110056336 CN102169831B (en) | 2011-03-10 | 2011-03-10 | Manufacturing method of silicon-on-insulator lateral insulated-gate bipolar transistor (SOI LIGBT) device unit of lateral channel with positive (p) buried layer |
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