CN215418189U - Graphical SOI LDMOS device structure - Google Patents
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- CN215418189U CN215418189U CN202122099659.5U CN202122099659U CN215418189U CN 215418189 U CN215418189 U CN 215418189U CN 202122099659 U CN202122099659 U CN 202122099659U CN 215418189 U CN215418189 U CN 215418189U
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 84
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The utility model discloses a graphical SOI LDMOS device structure. The graphical SOI LDMOS device structure comprises a substrate, a first insulating layer and an epitaxial layer which are sequentially arranged in a laminated mode, wherein the surface of the first insulating layer is provided with a first region and a second region different from the first region, the first region of the first insulating layer is provided with a graphical window penetrating through the first insulating layer along the thickness direction, a silicon layer is filled in the graphical window, and the silicon layer is respectively in heat conduction connection with the epitaxial layer and the substrate; and a source, a drain, a gate and a gate matched field plate. The patterned SOI LDMOS device structure provided by the embodiment of the utility model reduces the thickness of an upper silicon device, so that an LDD (lightly doped drain) junction of an LDMOS device on an oxide layer is deeply contacted with the oxide layer, thereby reducing Cds, lowering Cdb, remarkably reducing Coss and improving the high-frequency performance and efficiency of the LDMOS.
Description
Technical Field
The utility model particularly relates to a graphical SOI LDMOS device structure, and belongs to the technical field of semiconductors.
Background
Fig. 1 shows a cross-sectional view of a plane layout of an SOI wafer in a conventional SOI LDMOS, in which 1 is a substrate, 2 is a silicon oxide second insulating layer, and 3 is an epitaxial layer, wherein the silicon oxide second insulating layer 2 is a fully connected SOI, and since the thermal conductivity of the silicon oxide second insulating layer is only one twentieth of that of bulk silicon, heat dissipation is a big problem for the conventional SOI, and the main reason for the heat dissipation is self-heating effect, which has not been developed for many years.
In order to solve the self-heating effect of the SOI radio frequency power, the silicon thickness of the SOI upper layer is usually made to be more than 4 microns, and the junction temperature is lowered by increasing the silicon thermal melting, however, the following problems are brought about by the silicon thermal melting: 1) the effect of the thick silicon layer is not superior to that of bulk silicon, and the CdS or Cdb cannot be reduced remarkably, so that the Coss is reduced, and the high-frequency performance cannot be improved; 2) the LDD junction depth of the LDMOS cannot be 4 microns thick, and a p-type region can exist below the LDD, so that the effect of the silicon oxide second insulating layer is weakened; 3) the second silicon oxide insulating layers in the conventional SOI structure are connected into a whole, and a TSV process is needed to form a back side grounding, while the TSV process needs to etch through holes to penetrate through the silicon epitaxy, the second silicon oxide insulating layers and the silicon substrate layer, and different etching selection ratios can influence the appearance, such as consistency, uniformity and the like, of the through holes, so that the reliability and consistency of devices are reduced.
SUMMERY OF THE UTILITY MODEL
The utility model mainly aims to provide a graphical SOI LDMOS device structure to overcome the defects in the prior art.
In order to achieve the purpose of the utility model, the technical scheme adopted by the utility model comprises the following steps:
the graphical SOI LDMOS device structure provided by the embodiment of the utility model comprises: the silicon-based epitaxial wafer comprises a substrate, a first insulating layer and an epitaxial layer, wherein the substrate, the first insulating layer and the epitaxial layer are sequentially stacked, the surface of the first insulating layer is provided with a first region and a second region different from the first region, the first region of the first insulating layer is provided with a pattern window penetrating through the first insulating layer along the thickness direction, the pattern window is filled with a silicon layer, and the silicon layer is respectively in heat conduction connection with the epitaxial layer and the substrate; and
source, drain, gate and field plate matched with the gate.
Compared with the prior art, the utility model has the advantages that:
1) according to the graphical SOI LDMOS device structure provided by the embodiment of the utility model, the first insulating layer is graphical instead of a continuous whole piece, the first insulating layer is laid out according to the needs of a circuit or a device, the rest part without a graphical window of the first insulating layer is still a silicon layer and is connected with an upper silicon device and a substrate, and heat generated by the upper silicon device is introduced into the substrate, so that the purpose of reducing the junction temperature of the upper silicon device (such as LDMOS) is achieved;
2) according to the graphical SOI LDMOS device structure provided by the embodiment of the utility model, the thickness of an upper silicon device is reduced, so that an LDD (lightly doped drain) junction of an LDMOS device on a first insulating layer is deeply covered on the first insulating layer, Cds is reduced, Cdb is reduced, Coss can be remarkably reduced, and the high-frequency performance and efficiency of the LDMOS are improved;
3) the thin upper silicon layer enables Shallow Trench Isolation (STI) to conveniently contact the first insulating layer to form a thick oxide layer, parasitic effects of passive devices (such as inductors, capacitors and the like) manufactured on the oxide layer are small, and the resonance Q value is high, so that high-frequency loss of the devices is greatly reduced, and meanwhile, the efficiency of the amplifier or front and rear end modules is greatly improved.
Drawings
FIG. 1 is a cross-sectional view of a SOI wafer layout of a prior art SOI LDMOS;
FIG. 2 is a cross-sectional view of a patterned SOI wafer oxide layer layout in accordance with an exemplary embodiment of the present invention;
FIG. 3 is a top plan view of a patterned SOI wafer oxide layer layout provided in an exemplary embodiment of the present invention;
FIGS. 4-10 are schematic diagrams illustrating a process flow for fabricating a patterned SOI LDMOS device structure according to an exemplary embodiment of the present invention;
FIG. 11 is a cross-sectional view of a planar module layout of a low resistance substrate patterned SOI LDMOS device structure in accordance with an exemplary embodiment of the present invention;
FIG. 12 is a cross-sectional plan view of a module layout of a high resistance substrate patterned SOI LDMOS device structure according to an exemplary embodiment of the present invention;
fig. 13 is a layout diagram of a high-resistance substrate patterned SOI LDMOS device structure provided in an exemplary embodiment of the present invention.
Detailed Description
In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The technical solution, its implementation and principles, etc. will be further explained as follows.
The embodiment of the utility model provides a graphical SOI LDMOS device structure, which solves the heat dissipation problem of an SOI radio frequency power amplifier, can fully integrate the front end and the rear end to form a single chip solution, can be applied to the fields of base stations, mobile communication terminals, Internet of things, radars, radio frequency heating, illumination and the like, and is a key component of a radio frequency power amplifier.
The traditional SOI is connected into an oxide layer, a TSV process is needed to form back grounding, an etching through hole needs to penetrate through a silicon epitaxy layer, the oxide layer and a silicon substrate, the appearance of the through hole is affected by different etching selection ratios, such as consistency and uniformity, the connecting through hole only needs to etch the epitaxial layer and the substrate silicon, the etching ratios are consistent, and therefore the quality of the formed connecting through hole is high, and the reliability and the consistency of devices can be improved.
Aiming at the defects of the conventional SOI LDMOS, the graphical SOI LDMOS device structure provided by the embodiment of the utility model can greatly reduce the output capacitance, has better heat dissipation performance and solves the contradiction between the two design indexes of the SOI LDMOS output capacitance and the heat dissipation.
The graphical SOI LDMOS provided by the embodiment of the utility model can meet the requirements of higher frequency and higher output power of future 5G communication, and meanwhile, after the heat dissipation problem is solved, the performance, stability and long-term reliability of the front-end and rear-end integrated single chip can be guaranteed. In addition, the insulating interlayers of the traditional SOI are connected into a piece, the back side grounding is formed by using a TSV process, the TSV process needs to etch a through hole to penetrate through the silicon epitaxy layer, the first insulating layer and the silicon substrate, the appearance (such as consistency, uniformity and the like) of the through hole is affected by different etching selection ratios, the through hole only needs to etch the epitaxy layer and the substrate silicon, the etching ratios are consistent, therefore, the quality of the through hole is high, and the reliability and the consistency of the obtained device are greatly improved.
The graphical SOI LDMOS device structure provided by the embodiment of the utility model comprises: the silicon-based epitaxial wafer comprises a substrate, a first insulating layer and an epitaxial layer, wherein the substrate, the first insulating layer and the epitaxial layer are sequentially stacked, the surface of the first insulating layer is provided with a first region and a second region different from the first region, the first region of the first insulating layer is provided with a pattern window penetrating through the first insulating layer along the thickness direction, the pattern window is filled with a silicon layer, and the silicon layer is respectively in heat conduction connection with the epitaxial layer and the substrate; and
source, drain, gate and field plate matched with the gate.
Furthermore, the epitaxial layer comprises an SOI LDMOS active region which is correspondingly arranged in the first region of the first insulating layer, and the SOI LDMOS active region is also in heat conduction connection with a silicon layer arranged in the graphic window.
Furthermore, the SOI LDMOS active region includes a first well region and a second well region, a first doped region and a second doped region are formed in the first well region, a third doped region is formed in the second well region, the first doped region and the second doped region are connected to the source electrode, the third doped region is connected to the drain electrode, the source electrode is further electrically connected to the first metal plate, the drain electrode is further electrically connected to the second metal plate, and the first metal plate and the second metal plate are disposed above the epitaxial layer along the thickness direction;
the first well region and the first doped region are of a first conductivity type, and the second well region, the second doped region and the third doped region are of a second conductivity type.
Further, the first conductive type is a P type, and the second conductive type is an N type.
Furthermore, the first doped region and the second doped region are correspondingly disposed above the pattern window, and the second well region and the third doped region are correspondingly disposed above the second region of the first insulating layer.
Furthermore, the grid electrode and the field plate are arranged above the first well region, and the grid electrode and the field plate are correspondingly arranged above the second region of the first insulating layer; preferably, a gate dielectric layer is further disposed between the gate and the epitaxial layer.
Furthermore, the first metal plate is connected with the substrate through a first electric connection structure, is connected with the source electrode through a second electric connection structure, and is connected with the drain electrode through a third electric connection structure.
Further, one end of the first electrical connection structure is connected with the first metal pole plate, and the other end of the first electrical connection structure penetrates through the epitaxial layer and the silicon layer in the pattern window along the thickness direction and is arranged inside the substrate, or the other end of the first electrical connection structure penetrates through the epitaxial layer and the silicon layer in the pattern window along the thickness direction and is connected with the surface of the substrate, which is back to the epitaxial layer.
Further, the first electrical connection structure comprises a tungsten plug or a TSV through hole.
Further, the substrate is a low resistance substrate or a high resistance substrate.
Furthermore, the epitaxial layer further comprises an amplifier active region and a switch active region, the amplifier active region and the switch active region are correspondingly arranged in the second region of the first insulating layer, and isolation layers are further arranged among the SOI LDMOS active region, the amplifier active region and the switch active region and are isolated from each other through the isolation layers.
Further, the isolation layer includes a silicon oxide layer.
In some specific embodiments, the epitaxial layer further includes a passive device structure layer disposed on the second insulating layer, the second insulating layer is disposed in the second region of the first insulating layer, and the passive device structure layer is electrically isolated from the active region by the second insulating layer.
Further, the second insulating layer includes a silicon oxide layer.
Further, the thickness of first insulating layer is 20nm-4um, the thickness of epitaxial layer is 20nm-5um, the thickness of substrate is within 500 um.
Furthermore, the substrate, the silicon layer and the epitaxial layer are all made of silicon.
Further, the silicon layer is integrated with the substrate.
Further, the material of the first insulating layer includes silicon oxide, and the heat transfer coefficient of the substrate is greater than that of the first insulating layer, for example, the heat transfer coefficient of the first insulating layer is 7.6W/(mK), and the heat transfer coefficient of silicon is 150W/(mK).
Further, the substrate comprises silicon, and the first insulating layer comprises silicon oxide.
Further, the thickness of the first insulating layer is not more than 1 μm.
Further, the thickness of the epitaxial layer is not more than 3 μm.
It should be noted that only the power amplifier portion needs a patterned insulating layer, the insulating layer is only disposed in a region corresponding to the drift region, a window (i.e., no insulating layer) is disposed in a region corresponding to the source TSV via, the boundary of the insulating layer is located at the edge of the gate close to the drain, and is within 1um each left and right of the boundary, and the rf switch, the low-noise amplifier, and the passive device do not need a patterned insulating layer.
As will be described in further detail with reference to the drawings, the embodiments, implementations, principles, and so on of the present invention are well known to those skilled in the art, except for those specifically mentioned.
Referring to fig. 2 and fig. 3, a patterned SOI LDMOS device structure according to an embodiment of the present invention includes: the structure comprises a substrate 1, a first insulating layer 2 and an epitaxial layer 3 which are sequentially stacked, wherein the surface of the first insulating layer 2 is provided with a first region and a second region different from the first region, the first region of the first insulating layer 2 is provided with a pattern window 200 penetrating through the first insulating layer along the thickness direction, the pattern window 200 is filled with a silicon layer, and the silicon layer is respectively in heat conduction connection with the epitaxial layer and the substrate; and a source electrode, a drain electrode, a gate electrode 13 and a field plate 22, wherein the substrate 1, the epitaxial layer 3 and the silicon layer are all made of silicon, the first insulating layer 2 is made of silicon dioxide, and the silicon layer may be integrally provided with the substrate.
Referring to fig. 4-10, a method for fabricating a patterned SOI LDMOS device structure includes:
the method comprises the following steps: providing a supporting silicon wafer 1, i.e. a silicon substrate;
step two: etching a plurality of grooves 100 with different depths on the first surface of the supporting silicon wafer by using a graphical etching process, wherein the depth of each groove is 10nm-4 um;
step three: depositing an insulating layer 2 on the first surface of the supporting silicon wafer 1, at least filling the insulating layer 2 into the groove 100, and then grinding the insulating layer 2 by adopting a Chemical Mechanical Polishing (CMP) process so that the top surface of the insulating layer 2 is flush with the first surface of the supporting silicon wafer 1;
step four: providing a donor silicon wafer 300, and performing hydrogen implantation on the donor silicon wafer 300 to an implantation depth of 20nm-5um, so as to form a hydrogen implantation layer 400 inside the donor silicon wafer 300, wherein the hydrogen implantation layer 400 separates the donor silicon wafer 300 to form a top silicon layer 310 and a donor silicon wafer 320;
step five: bonding a supporting silicon wafer 1 and a donor silicon wafer 300 by using a wafer bonding device, wherein a top silicon layer 310 of the donor silicon wafer 300 is combined with a first surface of the supporting silicon wafer 1;
step six: the donor silicon wafer 320 is peeled from the hydrogen implantation layer 400, the top silicon layer 310 and the support silicon wafer 1 are combined to form an SOI wafer, and the peeled donor silicon wafer 320 can be reused to form a new donor silicon wafer, and it can be understood that the top silicon layer 310 is the epitaxial layer 3, or the epitaxial layer 3 is formed on the basis of the top silicon layer 310;
step seven: the SOI wafer is polished to remove the residual hydrogen implanted layer 400, and the finally formed SOI wafer top silicon layer 300 has a thickness of 20nm to 5um and the patterned silicon dioxide insulating layer has a thickness of 20nm to 4 um.
Specifically, referring to fig. 11 and 12, the epitaxial layer 3 includes an SOI LDMOS active region 5, a low noise ratio amplifier active region 6, a switch active region 7, and a passive device structure layer, wherein the SOI LDMOS active region 5 is correspondingly disposed in a first region of the first insulating layer 2 and corresponds to a pattern window, the SOI LDMOS active region 5 is further thermally connected to the substrate 1 disposed in the pattern window 21, the amplifier active region and the switch active region are further disposed in a second region of the first insulating layer 2, the low noise ratio amplifier active region 6, the switch active region 7, and the passive device structure layer are further disposed between the SOI LDMOS active region 5, the low noise ratio amplifier active region 6, and the switch active region 7 and are mutually isolated by a silicon oxide isolation layer 4, the passive device structure layer is disposed on the second insulating layer 8, the second insulating layer 8 is arranged on the first insulating layer, and the passive device structure layer is electrically isolated from the SOI LDMOS active region 5, the low-noise-coefficient amplifier active region 6 and the switch active region 7 through the second insulating layer 8.
Specifically, the field plate 22 may be a TSV array, which is at least used for isolating the LDMOS power amplifier region, so that crosstalk of the power amplifier to other regions can be effectively reduced, and waste heat conducted by the power amplifier can be effectively dissipated to the ground, thereby reducing the influence of the power amplifier on low noise amplification and lamp switching performance to the greatest extent, and improving the final competitiveness of the radio frequency chip module.
Note that the substrate in the device structure shown in fig. 11 is a low-resistance substrate, and the substrate in the device structure shown in fig. 12 is a high-resistance substrate.
Specifically, referring to fig. 13, the SOI LDMOS active region 5 includes a P-type well region 16 and an N-type well region 17, and a P-type heavily doped region (P-type well region) is formed in the P-type well region 16+)14 and N-type heavily doped region (N)+)15, an N-type heavily doped region (N) is formed in the N-type well region 17+)20, said P-type heavily doped region (P)+)14 and N-type heavily doped region (N)+)15 is connected to a source electrode, the source electrode is further connected to a first metal plate 11 through a second metal connection hole (i.e., the second electrical connection structure) 12, the first metal plate 11 is further connected to the substrate 1 through a first metal connection hole (i.e., the first electrical connection structure) 9, and the N-type heavily doped region (N)+)20 is connected to the drain electrode, which is electrically connected to the second metal plate via a third metal connection hole (i.e., the aforementioned third electrical connection structure) 19, wherein the P-type heavily doped region (P)+)14 and N-type heavily doped region (N)+)15 are correspondingly disposed in the P-well 16 and above the pattern window 200, and the structure 23 is a metal silicide, specifically titanium silicide, which is mainly used to improve the contact resistance between the metal hole 12 and the silicon P + (14) and N + (15).
Specifically, the first metal connection hole 9 penetrates through the epitaxial layer 3 and the silicon layer in the pattern window along the thickness direction and is arranged inside the substrate 1, or the first metal connection hole 9 penetrates through the epitaxial layer 3 and the silicon layer in the pattern window along the thickness direction and is connected with the surface of the substrate 1, which is back to the epitaxial layer, so that the source end of the transistor is grounded.
Specifically, the field plate 22 is grounded, the field plate 22 is mainly used for breakdown voltage, reducing the HCI effect caused by high-voltage operation, and reducing the feedback capacitance Cgd, the lengths of the field plate 22 and the N-type well region 17 can be elaborately designed into LDMOS devices with different static operating voltages to meet the application of different power levels, such as 5V mobile phone application, 12V Wifi application, 28V base station application and the like, wherein the length of the N-type well region is not more than 10um, and the length of the field plate is not more than 2/3 of the N-type well region, so as to obtain better breakdown voltage.
Specifically, the first metal connection hole, the second metal connection hole, and the third metal connection hole may be a tungsten plug or a TSV through hole, but are not limited thereto.
Specifically, a gate dielectric layer may be further disposed between the gate 13 and the epitaxial layer 3.
Specifically, the arrow 21 in fig. 13 points to the heat dissipation direction, the design of the discontinuity of the first insulating layer 2 is critical, and heat is conducted out from the region of the pattern window 200 (i.e., between the discontinuous silicon dioxide) connecting the epitaxial layer 3 and the substrate 1, so as to improve the heat dissipation condition of the SOI LDMOS.
According to the patterned SOI LDMOS device structure provided by the embodiment of the utility model, the first insulating layer is patterned instead of a continuous whole piece, the first insulating layer is laid out according to the needs of a circuit or a device, the rest part without the first insulating layer (namely, a patterned window area of an oxide layer) is still a silicon layer and is connected with an upper silicon device (namely, an epitaxial layer and the bottom silicon device) and a substrate, and heat generated by the upper silicon device is conducted into the lower silicon device (substrate), so that the aim of reducing the junction temperature of the upper silicon device (such as LDMOS) is fulfilled.
According to the graphical SOI LDMOS device structure provided by the embodiment of the utility model, the thickness of an upper silicon device is reduced, so that an LDD junction of the LDMOS device on an oxide layer (namely a first insulating layer) is deeply contacted with the oxide layer, the Cds is reduced, the Cdb is reduced, the Coss can be obviously reduced, and the high-frequency performance and the efficiency of the LDMOS are improved; in addition, the thin upper silicon layer enables Shallow Trench Isolation (STI) to conveniently contact the first insulating layer to form a thick oxide layer, parasitic effects of passive devices (such as inductors, capacitors and the like) manufactured on the oxide layer are small, and the resonance Q value is high, so that high-frequency loss of the devices is greatly reduced, and meanwhile, the efficiency of the amplifier or front and rear end modules is greatly improved.
It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. A graphical SOI LDMOS device structure, comprising: the silicon-based epitaxial wafer comprises a substrate, a first insulating layer and an epitaxial layer, wherein the substrate, the first insulating layer and the epitaxial layer are sequentially stacked, the surface of the first insulating layer is provided with a first region and a second region different from the first region, the first region of the first insulating layer is provided with a pattern window penetrating through the first insulating layer along the thickness direction, the pattern window is filled with a silicon layer, and the silicon layer is respectively in heat conduction connection with the epitaxial layer and the substrate; and
the epitaxial layer comprises an SOI LDMOS active region, the SOI LDMOS active region is correspondingly arranged in a first region of the first insulating layer, and the SOI LDMOS active region is further in heat conduction connection with a silicon layer arranged in the graphic window.
2. The patterned SOI LDMOS device structure of claim 1, wherein: the SOI LDMOS active region comprises a first well region and a second well region, a first doped region and a second doped region are formed in the first well region, a third doped region is formed in the second well region, the first doped region and the second doped region are connected with a source electrode, the third doped region is connected with a drain electrode, and
the source electrode is also electrically connected with the first metal polar plate, the drain electrode is also electrically connected with the second metal polar plate, and the first metal polar plate and the second metal polar plate are arranged above the epitaxial layer along the thickness direction;
the first well region and the first doped region are of a first conductivity type, and the second well region, the second doped region and the third doped region are of a second conductivity type.
3. The patterned SOI LDMOS device structure of claim 2, wherein: the first doped region and the second doped region are correspondingly arranged above the pattern window, and the second well region and the third doped region are correspondingly arranged above the second region of the first insulating layer.
4. The patterned SOI LDMOS device structure of claim 2, wherein: the first metal polar plate is connected with the substrate through a first electric connection structure, is connected with the source electrode through a second electric connection structure, and is connected with the drain electrode through a third electric connection structure.
5. The patterned SOI LDMOS device structure of claim 4, wherein: one end of the first electric connection structure is connected with the first metal polar plate, and the other end of the first electric connection structure penetrates through the epitaxial layer and the silicon layer in the pattern window along the thickness direction and is arranged inside the substrate, or the other end of the first electric connection structure penetrates through the epitaxial layer and the silicon layer in the pattern window along the thickness direction and is connected with the surface of the substrate back to the epitaxial layer.
6. The patterned SOI LDMOS device structure of claim 5, wherein: the first electric connection structure comprises a tungsten plug or a TSV through hole, and the substrate is a low-resistance substrate or a high-resistance substrate.
7. The patterned SOI LDMOS device structure of claim 1, wherein: the epitaxial layer further comprises an amplifier active region and a switch active region, the amplifier active region and the switch active region are correspondingly arranged in the second region of the first insulating layer, and isolating layers are further arranged among the SOI LDMOS active region, the amplifier active region and the switch active region and are isolated from each other through the isolating layers.
8. The patterned SOI LDMOS device structure of claim 1, wherein: the epitaxial layer further comprises a passive device structure layer, the passive device structure layer is arranged on the second insulating layer, the second insulating layer is arranged in the second area of the first insulating layer, and the passive device structure layer is electrically isolated from the active area through the second insulating layer.
9. The patterned SOI LDMOS device structure of claim 1, wherein: the thickness of first insulating layer is 20nm-4um, the thickness of epitaxial layer is 20nm-5um, the thickness of substrate is within 500 um.
10. The patterned SOI LDMOS device structure of claim 1, wherein: the silicon layer is integrated with the substrate.
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| CN202110672378.6A Active CN115274848B (en) | 2021-04-29 | 2021-06-17 | Super-junction LDMOS device of patterned layout interlayer oxide layer SOI |
| CN202110940172.7A Pending CN115274816A (en) | 2021-04-29 | 2021-08-16 | High-resistance substrate TSV grounded super-junction LDMOS device and manufacturing method thereof |
| CN202111023606.3A Pending CN115274850A (en) | 2021-04-29 | 2021-09-01 | Graphical oxidation interlayer layout SOI wafer structure for radio frequency single chip integration |
| CN202111008265.2A Pending CN115274548A (en) | 2021-04-29 | 2021-09-01 | SOI wafer and manufacturing method of TSV in SOI wafer |
| CN202122099659.5U Active CN215418189U (en) | 2021-04-29 | 2021-09-01 | Graphical SOI LDMOS device structure |
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| CN202110672378.6A Active CN115274848B (en) | 2021-04-29 | 2021-06-17 | Super-junction LDMOS device of patterned layout interlayer oxide layer SOI |
| CN202110940172.7A Pending CN115274816A (en) | 2021-04-29 | 2021-08-16 | High-resistance substrate TSV grounded super-junction LDMOS device and manufacturing method thereof |
| CN202111023606.3A Pending CN115274850A (en) | 2021-04-29 | 2021-09-01 | Graphical oxidation interlayer layout SOI wafer structure for radio frequency single chip integration |
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