CN109616472B - Semiconductor device structure and forming method - Google Patents

Semiconductor device structure and forming method Download PDF

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CN109616472B
CN109616472B CN201811529843.5A CN201811529843A CN109616472B CN 109616472 B CN109616472 B CN 109616472B CN 201811529843 A CN201811529843 A CN 201811529843A CN 109616472 B CN109616472 B CN 109616472B
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active region
well active
contact hole
back contact
injection
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CN109616472A (en
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顾学强
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Shanghai Weijing Electronic Technology Co ltd
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Shanghai Weijing Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

The invention discloses a semiconductor device structure, which is characterized in that a conventional semiconductor substrate is used for manufacturing devices, and the devices are connected with shallow trench isolation through back trench isolation, so that complete medium isolation among the devices is realized; the bottom of the back groove isolation is in contact with the N + source drain and the P + source drain, so that parasitic capacitance between the N + source drain and the P well and between the P + source drain and the N well are eliminated, and the switching speed of the MOS device is improved; through back N + injection and P + injection, a back contact hole and a back metal layer process, the grounding of a P well of an NMOS is realized, an N well of a PMOS is connected with a power supply, and the series resistance of body contact is reduced, so that the floating body effect of an SOI device is avoided; and the back contact hole is connected with the side walls of the N-well active region and the P-well active region on the silicon substrate, and heat generated in the device can be quickly led out through the contact hole and the metal layer, so that the self-heating effect is avoided, and the performance degradation of the device is prevented. The invention also discloses a forming method of the semiconductor device structure.

Description

Semiconductor device structure and forming method
Technical Field
The invention relates to the technical field of semiconductor processing, in particular to a semiconductor device structure and a forming method.
Background
For half a century, the semiconductor industry has conducted reductions in transistor size, increases in transistor density, and increases in performance on a duty-by-duty basis in accordance with moore's law. However, as the dimensions of bulk silicon transistor devices in planar structures are getting closer to the physical limits, moore's law is also getting closer to its termination; therefore, some new structures of semiconductor devices called "non-classical CMOS" have been proposed. These techniques include FinFETs, carbon nanotubes, and Silicon On Insulator (SOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (Ge on insulator: geOI), among others. The performance of the semiconductor device can be further improved by these new structures.
Among them, semiconductor devices on an insulator have attracted much attention because of their simple processes and superior performance. Semiconductor-on-insulator is a technique for fabricating devices on an insulating layer rather than on a conventional silicon substrate, thereby achieving all-dielectric isolation of individual transistors. Compared with the traditional planar bulk silicon process, the SOI technology has the advantages of high speed, low power consumption and high integration level.
As CMOS processes enter the deep sub-micron regime, SOI, siGeOI & GeOI, are receiving increasing attention in order to achieve high performance and low power devices. Compared with a bulk silicon device, the unique insulating buried oxide layer separates the device from the substrate, realizes the full dielectric isolation of a single transistor, eliminates the influence (namely the bulk effect) of the substrate on the device, fundamentally eliminates the Latch-Up of the bulk silicon CMOS device, inhibits the parasitic effect of the bulk silicon device to a great extent, fully exerts the potential of the silicon integration technology, greatly improves the performance of a circuit, and has the working performance close to an ideal device. Whether in the aspect of device size reduction, radio frequency or low voltage, low power consumption and other applications, the technology shows to be the main technology of the future SoC. By using the semiconductor-on-insulator technology, a logic circuit, an analog circuit and an RF circuit can be integrated on one chip under the condition of small mutual interference, so that the semiconductor-on-insulator integrated circuit has a very wide development prospect and becomes an important technology for researching and developing a large-scale integrated circuit with high speed, low power consumption, high integration degree and high reliability.
But the device structure of the semiconductor device on the insulator with full isolation also causes the deterioration of the parameter performance of part of the devices. As shown in fig. 1, which is a cross-sectional view of a conventional non-fully depleted silicon-on-insulator device. Generally, an SOI silicon wafer is processed by SIMOX or SMART CUT technology to finally form a three-layer structure of a substrate silicon wafer 10, a silicon dioxide insulating medium 11 and a device silicon layer 12; then, the fabrication of CMOS (i.e., NMOS and PMOS) devices is performed in the device silicon layer 12, and finally, the contact holes 13 and the subsequent metal interconnections 15 are formed to form a circuit structure. Since the NMOS and PMOS transistors are surrounded by the trench isolation 16 and the carbon dioxide dielectric layer 12, full device-to-device isolation is achieved. However, since the devices are fully isolated, the NMOS and PMOS body regions 14 of fig. 1 cannot be effectively connected to a power supply or ground, creating a so-called floating body effect. Although the floating body effect can be improved through the device layout, the floating body effect still appears when the body contact region is far away from the channel region due to the larger resistance of the body region 14, so that the output curve of the MOS transistor is abnormal. Meanwhile, the thermal conductivity of the silicon dioxide 12 below the body region 14 is poor, which causes the self-heating effect of the device, so that the carrier mobility of the device is reduced, and the performance of the device is deteriorated. In addition, the preparation process of the SOI silicon wafer is complex and the manufacturing cost is high.
Therefore, there is a need for a new type of semiconductor device that can be manufactured using a lower cost semiconductor substrate without using an SOI silicon wafer, while avoiding the floating body effect and self-heating effect of the SOI device.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned deficiencies of the prior art and to providing a semiconductor device structure and method of forming the same.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a semiconductor device structure, comprising: a plurality of structures disposed on the front and back sides of the semiconductor substrate; wherein the content of the first and second substances,
the structure arranged on the front surface of the semiconductor substrate comprises:
shallow trench isolation, a well active region, a source drain and a gate on the front surface of the semiconductor substrate;
a back dielectric layer on the front surface of the semiconductor substrate, and a back metal interconnection layer in the back dielectric layer;
the structure arranged on the back surface of the semiconductor substrate comprises:
a back side trench isolation and heavily doped injection layer on the back side of the semiconductor substrate; the back surface trench isolation is positioned above and connected with the shallow trench isolation and the source drain, and completely covers the shallow trench isolation and the source drain, and the heavily doped injection layer is connected and positioned above the well active region;
the semiconductor substrate comprises a back dielectric layer, a back contact hole and a back metal layer, wherein the back dielectric layer is positioned on the back surface of the semiconductor substrate, the back contact hole is positioned in the back dielectric layer, the lower end of the back contact hole is connected with the heavily doped injection layer and the well active region, and the back metal layer is connected with the upper end of the back contact hole;
wherein, the side wall of the back contact hole extends downwards to be at least connected with the side wall of the heavily doped injection layer.
Further, the number of the back contact holes is 1 to multiple; when the width of the well active region is smaller than the minimum design rule of the back contact holes, 1 back contact hole is adopted, and the side wall of the back contact hole extends downwards to be connected with at least the side wall of the heavily doped injection layer; and when the width of the well active region is larger than the minimum design rule of the back contact holes, adopting a plurality of back contact holes, and enabling the outer side walls of the two back contact holes positioned on the outermost sides to extend downwards to be connected with the side walls of the heavily doped injection layers at least.
Further, the side wall of the back contact hole extends downwards to be simultaneously connected with the side walls of the heavily doped injection layer and the well active region.
Further, the semiconductor device structure is an NMOS or PMOS structure.
Furthermore, the semiconductor device structure is a structure in which the NMOS and the PMOS are alternately arranged, and the NMOS and the PMOS are isolated by a full isolation structure formed by the upper and lower connected shallow trench isolation and back trench isolation.
Further, when the semiconductor device structure is an NMOS structure, the well active region is a P well active region, and the heavily doped injection layer is a P + injection region; when the semiconductor device structure is a PMOS structure, the well active region is an N well active region, and the heavily doped injection layer is an N + injection region.
A method for forming a semiconductor device structure, comprising:
providing a semiconductor substrate, and forming shallow trench isolation, a P well active region, an N + source drain and a grid of an NMOS (N-channel metal oxide semiconductor), and an N well active region, a P + source drain and a grid of a PMOS (P-channel metal oxide semiconductor) on the front surface of the semiconductor substrate;
depositing a back-end dielectric layer on the surface of the front side of the semiconductor substrate, and forming a contact hole and a back-end metal interconnection layer in the back-end dielectric layer;
inverting the semiconductor substrate to bond the surface of the subsequent dielectric layer with a slide glass; then carrying out first annealing;
thinning the back of the semiconductor substrate to enable the thickness of the thinned semiconductor substrate to be smaller than the injection depth of the N-well active region and the P-well active region;
p + injection is carried out in a P well active region of the NMOS, and N + injection is carried out in an N well active region of the PMOS; then carrying out second annealing, and carrying out activation of N + injection and P + injection;
forming a back groove on the back of the semiconductor substrate, filling a medium in the back groove to form a back groove isolation which is connected with the shallow groove isolation and the source drain up and down, and completely covering the shallow groove isolation and the source drain from the top by the back groove isolation so as to form a full isolation structure between the NMOS and the PMOS;
depositing a back dielectric layer on the back surface of the semiconductor substrate, defining and filling a back contact hole in the back dielectric layer, forming a back contact hole of an NMOS (N-channel metal oxide semiconductor) and a back contact hole of a PMOS (P-channel metal oxide semiconductor), and enabling the side wall of the back contact hole to extend downwards so as to form ohmic contacts between the back contact hole of the PMOS and the N + injection and N well active region and between the back contact hole of the NMOS and the P + injection and P well active region respectively;
and forming a back metal layer on the back contact hole, and realizing the power supply connection and the ground connection of the N-well active region and the P-well active region through the connection of the back metal layer, a power supply and the ground.
Further, when the width of the N well active region/the P well active region is smaller than the minimum design rule of the back contact hole, 1 back contact hole is formed in the PMOS/NMOS, and the side wall of the 1 back contact hole extends downwards to be simultaneously connected with the side wall of the N + injection and N well active region/P + injection and P well active region; and when the width of the N-well active region/P-well active region is larger than the minimum design rule of the back contact holes, forming a plurality of back contact holes in the PMOS/NMOS, and extending the outer side walls of the two back contact holes positioned at the outermost sides downwards to be connected with the side walls of the N + injection and N-well active region/P + injection and P-well active region.
Further, the semiconductor substrate is a silicon, germanium, silicon carbide or gallium nitride substrate, or an elemental substance substrate of indium phosphide, or a compound substrate of indium phosphide; the filling medium in the back groove isolation is one or more of silicon dioxide, silicon nitride and silicon oxynitride.
Further, the second annealing is laser annealing or low-temperature annealing.
According to the technical scheme, the conventional semiconductor substrate is used for manufacturing the semiconductor device, and the conventional semiconductor process, the stacking process, the back groove process and the back metallization process are used for manufacturing the semiconductor device, so that NMOS and PMOS devices which are fully isolated and avoid a floating body effect and a self-heating effect can be manufactured without using an SOI substrate. The invention has the following advantages:
(1) By connecting the back trench isolation with the shallow trench isolation, complete dielectric isolation between devices is achieved.
(2) The bottom of the back groove isolation is in contact with the N + source drain of the NMOS and the P + source drain of the PMOS, parasitic capacitance between the N + source drain and the P well active region and parasitic capacitance between the P + source drain and the N well active region are eliminated, and the switching speed of the MOS device is improved.
(3) Through back N + injection and P + injection, a back contact hole and a back metal layer process, grounding of a P well active region of the NMOS is realized, and a N well active region of the PMOS is connected with a power supply, so that series resistance of body contact is reduced, and a floating body effect of the SOI device is avoided; and the back contact hole is connected with the N + injection active region, the N trap active region, the P + injection active region and the P trap active region on the silicon substrate, and heat generated in the device can be quickly led out through the back contact hole and the back metal layer, so that the self-heating effect is avoided, and the performance degradation of the device is prevented.
(4) Through layout design, the back contact holes are covered with the back groove isolation regions at the edges of the active region, and the back contact holes wrapping the two sides of the active region are formed, so that contact resistance can be further reduced, heat conductivity can be further improved, and the floating body effect and the self-heating effect of the device can be reduced.
Drawings
Fig. 1 is a schematic diagram of a conventional non-fully depleted silicon-on-insulator device.
Fig. 2 is a schematic diagram of a semiconductor device structure according to a preferred embodiment of the invention.
Fig. 3-11 are process steps of a method of forming a semiconductor device structure according to a preferred embodiment of the invention.
Detailed Description
The following provides a more detailed description of embodiments of the present invention, with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following detailed description of the present invention, please refer to fig. 2, wherein fig. 2 is a schematic diagram of a semiconductor device structure according to a preferred embodiment of the present invention. As shown in fig. 2, a semiconductor device structure of the present invention includes a plurality of structures disposed on the front and back surfaces of a semiconductor substrate 22. The semiconductor substrate 22 may be a silicon, germanium, silicon carbide, or gallium nitride substrate, or an elemental substrate of indium phosphide, or a compound substrate of indium phosphide. The following will explain a silicon substrate as an example. The semiconductor device structure of the invention can be an NMOS or PMOS structure; alternatively, the semiconductor device structure of the present invention may be a structure in which NMOS and PMOS are alternately arranged. The present invention will be described in detail below with a structure in which NMOS and PMOS are alternately arranged.
Please refer to fig. 2. In a semiconductor device structure of the present invention, the structure provided on the front surface of the silicon substrate 22 may include:
shallow trench isolation 21 arranged on the front surface of the silicon substrate 22, a P well active region 25, N + source drain 23 and gate 20 of NMOS, an N well active region 25', P + source drain 23' and gate 20' of PMOS.
A back dielectric layer 32 provided on the front surface of the silicon substrate 22, and a back metal interconnection layer 31 provided in the back dielectric layer 32. The subsequent metal interconnection layer 31 is connected to the silicon substrate 22 through the contact hole 30.
Please refer to fig. 2. Meanwhile, in a semiconductor device structure of the present invention, a structure provided on the back surface of the silicon substrate 22 includes:
backside trench isolation 24 and P + implant regions for NMOS 26 and N + implant regions for PMOS 26' provided on the backside of silicon substrate 22.
A backside dielectric layer 29 disposed on the backside surface of the silicon substrate 22, backside contact holes 28 and 28 'disposed in the backside dielectric layer 29, and a backside metal layer 27 disposed on the backside contact holes 28 and 28'.
Backside contact holes 28, 28' are located in the NMOS and PMOS regions, respectively. Wherein, the lower end of the back contact hole 28 in the NMOS region is connected with the P + injection region 26 and the P well active region 25, and the upper end is connected with the back metal layer 27; the lower end of the back contact hole 28 'located in the PMOS region connects the N + implant region 26' and the N well active region, while the upper end is connected to the back metal layer 27. The sidewalls of the back contact holes 28 and 28 'may extend down to meet at least the sidewalls of the heavily doped implant layer P + implant region 26 and N + implant region 26'.
Please refer to fig. 2. The lower end of the back trench isolation 24 is connected to and located above the shallow trench isolation 21 and the N + source drain 23 and the P + source drain 23', and meanwhile, the lower end of the back trench isolation 24 also completely covers the surfaces of the shallow trench isolation 21 and the N + source drain 23 and the P + source drain 23'. The P + injection region 26 in the heavily doped injection layer is connected and positioned above the P well active region 25, and the N + injection region 26 'is connected and positioned above the N well active region 25'.
The upper end of the backside trench isolation 24 and the P + implant region 26, N + implant region 26' may be exposed at the backside surface of the silicon substrate 22.
The backside trench isolation 24 is filled with a dielectric material. The NMOS and the PMOS are connected through the back groove isolation and the shallow groove isolation, so that complete medium isolation between devices is realized, and the full isolation effect similar to that of a silicon-on-insulator device is achieved; and the bottom of the back groove isolation is completely contacted with the N + source drain of the NMOS and the P + source drain of the PMOS, so that parasitic junction capacitances between the N + source drain and the P well active region and between the P + source drain and the N well active region are eliminated, and the switching speed of the MOS device is improved.
The backside contact holes 28, 28 'may be disposed in 1 to more than one of the NMOS and PMOS regions above the P + implant region 26 and the N + implant region 26', respectively, according to the heat dissipation requirement. For example, when the width of the well active region is smaller than the minimum design rule of the back contact holes, 1 back contact hole can be adopted, and the side wall of the back contact hole extends downwards to be at least connected with the side wall of the heavily doped injection layer; when the width of the well active region is larger than the minimum design rule of the back contact holes, a plurality of back contact holes can be adopted, and the outer side walls of the two back contact holes positioned at the outermost sides extend downwards to be at least connected with the side walls of the heavily doped injection layer.
The sidewalls of the back contact hole may extend down to meet the sidewalls of the heavily doped implant layer and the well active region at the same time
For example, as shown in fig. 2, when the channel width a of the PMOS device is smaller than the minimum design rule of the backside contact hole, the single hole backside contact hole 28 'is used to cover the backside trench isolation region 24 under the transistor, so as to partially or completely wrap the N-well active region 25'; when the channel width b of the NMOS device is larger than the minimum design rule of the back contact hole, a plurality of back contact holes 28 are needed under the transistor, but the back contact holes 28 at the left and right sides cover the back trench isolation region 24 to partially or completely wrap the P-well active region 25.
The fully wrapped backside contact hole can reduce the series resistance of the body contact and increase the thermal conductivity of the device.
The N + injection and the P + injection are led out through the back contact hole and the back metal layer, and then the N well active region and the P well active region are reversely biased through the bias voltage of the circuit, namely the power supply voltage is applied to the back metal layer of the PMOS, and the ground level is applied to the back metal layer of the NMOS, so that the floating body effect is avoided; meanwhile, the back contact hole is filled with metal materials such as tungsten and the like, so that the back contact hole is a good thermal conductor, heat formed in the semiconductor substrate can be quickly led out through the back contact hole and the back metal layer, and the self-heating effect of the device is avoided.
Meanwhile, the back contact hole and the N well active region/P well active region form a wrapping type contact, so that the contact resistance of the back contact hole can be effectively reduced, and the thermal conductivity can be obviously improved.
A method for forming a semiconductor device structure according to the present invention will be described in detail below with reference to the accompanying drawings.
Referring to fig. 3-11, fig. 3-11 are process steps of a method for forming a semiconductor device structure according to a preferred embodiment of the invention. As shown in fig. 3-11, a method for forming a semiconductor device structure of the present invention can be used to form the semiconductor device structure. Taking the silicon substrate 22 as an example, the method for forming a semiconductor device structure of the present invention may include the following steps:
first, as shown in fig. 3, shallow trench isolation 21, a P-well active region 25, N + source drain 23 and gate 20 of an nmos, and N-well active region 25', P + source drain 23' and gate 20' of a PMOS may be formed on the front surface of a silicon substrate 22 using a conventional CMOS fabrication process. The gate 20 of the NMOS and the gate 20' of the PMOS can be made of polysilicon material.
Next, a subsequent dielectric layer material is deposited on the front surface of the silicon substrate 22 to form a subsequent dielectric layer 32, and a contact hole 30 and a subsequent metal interconnection layer 31 are formed in the subsequent dielectric layer 32.
Then, as shown in fig. 4, the silicon substrate 22, which has completed the conventional CMOS process, is inverted, and the surface of the subsequent dielectric layer 32 is adhesively bonded to a carrier 33. And then a conventional annealing (first annealing) is performed.
Next, as shown in fig. 5, the back side of the silicon substrate 22 may be thinned by grinding, wet etching, chemical mechanical polishing, and other processes, so that the thickness of the thinned silicon substrate 22 is smaller than the implantation depth of the N-well active region 25' and the P-well active region 25.
Next, as shown in fig. 6, P + implantation may be performed in the P-well active region 25 of the NMOS and N + implantation may be performed in the N-well active region 25' of the PMOS through an ion implantation process; then, annealing (second annealing) is performed to perform activation of the N + implantation and the P + implantation, thereby forming N + implantation regions 26', P + implantation regions 26. The second annealing can adopt laser annealing or low-temperature annealing to activate the N + implantation and the P + implantation on the premise of not influencing the performance of the device in the conventional CMOS process.
Again, as shown in fig. 7, a back trench 24 'whose position corresponds to the shallow trench isolation 21 and the N + source and drain 23 and the P + source and drain 23' may be formed on the back surface of the silicon substrate 22 by photolithography, dry etching or wet etching, and the bottom of the back trench 24 'covers the shallow trench isolation 21 region, the N + source and drain 23 region, and the P + source and drain 23' region. When the back trench 24 'is etched, a part of the dielectric layer in the shallow trench isolation 21 needs to be removed, and the bottom of the back trench 24' is in complete contact with the P + source drain and N + source drain surfaces.
Next, as shown in fig. 8, a dielectric filling is performed in the backside trench 24', and the dielectric may be one or more of silicon dioxide, silicon nitride and silicon oxynitride, so as to form a backside trench isolation 24. The back trench isolation 24 completely covers the surfaces of the shallow trench isolation 21, the N + source drain 23 and the P + source drain 23' from above, and the back trench is combined with the shallow trench isolation 21 formed in a conventional CMOS process, thereby forming an all-dielectric isolation structure between the NMOS and the PMOS.
Again, as shown in fig. 9, a conventional dielectric layer material may be deposited on the backside surface of the silicon substrate 22 by chemical vapor deposition or the like to form a backside dielectric layer 29. The material of the back dielectric layer may be the same as the dielectric of the trench isolation, and may be one or more of silicon dioxide, silicon nitride, and silicon oxynitride, for example.
Subsequently, as shown in fig. 10, the back contact holes 28-1 and 28-2 can be defined in the back dielectric layer 29 by photolithography and etching, so as to extract the N-well active region and the P-well active region, thereby reducing the series resistance of the body contact and increasing the thermal conductivity of the device.
In order to further reduce the body contact resistance and improve the self-heating effect, when the channel width a of the PMOS device is smaller than the minimum design rule of the back contact hole, as shown in fig. 2, a single-hole back contact hole 28-2 may be used by layout design, i.e., under the transistor with a smaller channel width, so that the back contact hole covers the back trench region at both sides of the N well. Through the etching process, as the back groove and the back medium both use the same insulating medium, the back contact hole forms a downward over-etching area in the back groove area at two sides of the N well in the back groove etching process. Through subsequent metal deposition, metal completely wraps the N-well active region on two sides, so that the body contact resistance is reduced and the self-heating effect is reduced.
When the channel width b of the NMOS device is larger than the minimum design rule of the back contact holes, namely when the channel width is larger, a plurality of back contact holes 28-1 can be used through layout design, the boundaries of the two back contact holes at the leftmost side and the rightmost side exceed the boundary of the active region of the P well, and back contact hole patterns wrapping the active region are formed on the two sides of the P well through etching. The fully wrapped backside contact hole can reduce the series resistance of the body contact and increase the thermal conductivity of the device.
Thereafter, as shown in FIG. 11, the backside contact holes 28-1 and 28-2 are filled and planarized, and for example, 3 backside contact holes 28 are formed in the NMOS and 1 backside contact hole 28' is formed in the PMOS. The back contact fill metal may be a CMOS process compatible metal material such as tungsten, aluminum, or copper, thereby forming ohmic contacts between the back contact 28 and the P + implant region 26 and the P-well active region 25, ohmic contacts between the back contact 28' and the N + implant region 26' and the N-well active region 25', and forming a thermally conductive channel for the device.
Finally, as shown in fig. 2, a back metal layer 27 is formed on the back contact holes 28, 28'. The power and ground connections of the N-well active region 25' and the P-well active region 25 are made through the connection of the back metal layer 27 to power and ground.
In summary, the present invention performs the fabrication of the semiconductor device through the conventional semiconductor process, the stacking process, the back trench process and the back metallization process, so that the fully isolated NMOS and PMOS devices can be fabricated without using an SOI substrate. Meanwhile, the back surface trench isolation is connected with the shallow trench isolation, so that complete medium isolation among devices is realized; the bottom of the back groove isolation is in contact with an N + source drain of an NMOS and a P + source drain of a PMOS, so that parasitic capacitance between the N + source drain and a P well and between the P + source drain and the N well are eliminated, and the switching speed of an MOS device is improved; through back N + injection and P + injection, a back contact hole and a back metal layer process, the grounding of a P well of an NMOS is realized, an N well of a PMOS is connected with a power supply, and the series resistance of body contact is reduced, so that the floating body effect of an SOI device is avoided; and the back contact hole is connected with the N + injection and the P + injection on the silicon substrate, and heat generated in the device can be quickly led out through the contact hole and the metal layer, so that the self-heating effect is avoided, and the performance degradation of the device is prevented. In addition, through layout design, the back contact holes are covered with the back groove isolation regions at the edges of the active region, and the back contact holes wrapping the two sides of the active region are formed, so that contact resistance can be further reduced, heat conductivity can be further improved, and the floating body effect and the self-heating effect of the device can be reduced. The present invention uses conventional silicon substrates for semiconductor device fabrication and is therefore compatible with conventional semiconductor processing.
The above description is only a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of the present invention, so that any equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.

Claims (10)

1. A semiconductor device structure, comprising: a plurality of structures disposed on the front and back sides of the semiconductor substrate; wherein the content of the first and second substances,
the structure arranged on the front surface of the semiconductor substrate comprises:
shallow trench isolation, a well active region, a source drain and a gate on the front surface of the semiconductor substrate;
a back dielectric layer on the front surface of the semiconductor substrate, and a back metal interconnection layer in the back dielectric layer;
the structure arranged on the back surface of the semiconductor substrate comprises:
a back side trench isolation and heavily doped implant layer on the back side of the semiconductor substrate; the back surface trench isolation is positioned above and connected with the shallow trench isolation and the source drain, and completely covers the shallow trench isolation and the source drain, and the heavily doped injection layer is connected and positioned above the well active region;
the semiconductor substrate comprises a back dielectric layer, a back contact hole and a back metal layer, wherein the back dielectric layer is positioned on the back surface of the semiconductor substrate, the back contact hole is positioned in the back dielectric layer, the lower end of the back contact hole is connected with the heavily doped injection layer and the well active region, and the back metal layer is connected with the back metal layer positioned on the upper end of the back contact hole;
wherein, the side wall of the back contact hole extends downwards to be at least connected with the side wall of the heavily doped injection layer.
2. The semiconductor device structure according to claim 1, wherein the back contact hole is 1 to plural; when the width of the well active region is smaller than the minimum design rule of the back contact holes, 1 back contact hole is adopted, and the side wall of the back contact hole extends downwards to be connected with at least the side wall of the heavily doped injection layer; and when the width of the well active region is larger than the minimum design rule of the back contact holes, adopting a plurality of back contact holes, and enabling the outer side walls of the two back contact holes positioned on the outermost side to extend downwards to be connected with at least the side wall of the heavily doped injection layer.
3. The semiconductor device structure of claim 1 or 2, wherein sidewalls of the back contact holes extend down to meet sidewalls of the heavily doped implant layer and well active region simultaneously.
4. The semiconductor device structure of claim 1, wherein the semiconductor device structure is an NMOS or PMOS structure.
5. The semiconductor device structure of claim 1, wherein the semiconductor device structure is a structure in which NMOS and PMOS are alternately arranged, and the NMOS and the PMOS are isolated by a full isolation structure formed by upper and lower connected shallow trench isolation and backside trench isolation.
6. The semiconductor device structure of claim 4 or 5, wherein when the semiconductor device structure is an NMOS structure, the well active region is a P-well active region and the heavily doped implant layer is a P + implant region; when the semiconductor device structure is a PMOS structure, the well active region is an N well active region, and the heavily doped injection layer is an N + injection region.
7. A method for forming a semiconductor device structure, comprising:
providing a semiconductor substrate, and forming shallow trench isolation, a P well active region, an N + source drain and a grid of an NMOS (N-channel metal oxide semiconductor), and an N well active region, a P + source drain and a grid of a PMOS (P-channel metal oxide semiconductor) on the front surface of the semiconductor substrate;
depositing a back-end dielectric layer on the surface of the front side of the semiconductor substrate, and forming a contact hole and a back-end metal interconnection layer in the back-end dielectric layer;
inverting the semiconductor substrate to bond the surface of the subsequent dielectric layer with a slide glass; then carrying out first annealing;
thinning the back of the semiconductor substrate to enable the thickness of the thinned semiconductor substrate to be smaller than the injection depth of the N-well active region and the P-well active region;
p + injection is carried out in a P well active region of the NMOS, and N + injection is carried out in an N well active region of the PMOS; then carrying out second annealing, and carrying out activation of N + injection and P + injection;
forming a back groove on the back of the semiconductor substrate, filling a medium in the back groove to form a back groove isolation which is connected with the shallow groove isolation and the source drain up and down, and completely covering the shallow groove isolation and the source drain from the top by the back groove isolation so as to form a full isolation structure between the NMOS and the PMOS;
depositing a back dielectric layer on the back surface of the semiconductor substrate, defining and filling a back contact hole in the back dielectric layer, forming a back contact hole of an NMOS (N-channel metal oxide semiconductor) and a back contact hole of a PMOS (P-channel metal oxide semiconductor), and enabling the side wall of the back contact hole to extend downwards so as to form ohmic contacts between the back contact hole of the PMOS and an N + injection and N well active region and between the back contact hole of the NMOS and a P + injection and P well active region respectively;
and forming a back metal layer on the back contact hole, and realizing the power supply connection and the ground connection of the N-well active region and the P-well active region through the connection of the back metal layer, a power supply and the ground.
8. The method as claimed in claim 7, wherein when the width of the N/P well active region is less than the minimum design rule of the back contact hole, 1 back contact hole is formed in the PMOS/NMOS and the sidewall of the 1 back contact hole is extended downward to meet the sidewalls of the N + implant and the N/P + implant and P well active regions at the same time; and when the width of the N-well active region/P-well active region is larger than the minimum design rule of the back contact holes, forming a plurality of back contact holes on the PMOS/NMOS, and extending the outer side walls of the two back contact holes positioned on the outermost sides downwards to be connected with the side walls of the N + injection and N-well active region/P + injection and P-well active region.
9. The method for forming a semiconductor device structure according to claim 7, wherein the semiconductor substrate is a silicon, germanium, silicon carbide, or gallium nitride substrate, or an elemental substrate of indium phosphide, or a compound substrate of indium phosphide; the filling medium in the back groove isolation is one or more of silicon dioxide, silicon nitride and silicon oxynitride.
10. The method of claim 7, wherein the second anneal is a laser anneal or a low temperature anneal.
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