CN102163980A - Method for processing consistency of sum-difference channel signal transmission delays through automatic calibration - Google Patents
Method for processing consistency of sum-difference channel signal transmission delays through automatic calibration Download PDFInfo
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- CN102163980A CN102163980A CN2011101269774A CN201110126977A CN102163980A CN 102163980 A CN102163980 A CN 102163980A CN 2011101269774 A CN2011101269774 A CN 2011101269774A CN 201110126977 A CN201110126977 A CN 201110126977A CN 102163980 A CN102163980 A CN 102163980A
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Abstract
The invention provides a method for processing the consistency of sum-difference channel through automatic calibration in a double-channel monopulse mechanism, and when the method is applied to the process of extracting angular error signals by using a sum-difference cross-correlation algorithm, the peak values of sum and difference signals subjected to cross-correlation can be improved effectively, thereby obtaining the maximum angular error detection sensitivity. The method is implemented by the technical scheme which comprises the following steps: in a digital signal processing module in a field-programmable gate array (FPGA) chip, inputting sum signals by a memory (first in first out FIFO1) controlled by a high-speed system clock, and inputting difference signals by a memory (FIFO2) controlled by another high-speed system clock; in a digital signal processor (DSP) chip, designing a logic control program for the whole phase calibration process, wherein the logic control program is used for receiving a phase calibration command issued by application software and controlling the read-write retardation change of the FIFO1 and the FIFO2; and through combining the DSP program with a position (pitching) phase shifter, automatically organizing a process to complete the calibration on sum-difference channel delays, thereby calibrating the sum-difference channel delays to be consistent.
Description
Technical field
The present invention is a kind of in field of aerospace two-channel monopulse system and difference cross correlation algorithm track receiver, will calibrate consistent processing method with difference channel signal propagation delay time.
Background technology
At present, in fields such as space flight measurement and controls, the signal form that ground installation receives is more and more multiple various, and multiple signal form has been proposed the angle tracking demand.Prior art is usually utilized and the their cross correlation of difference signal, adopts to adapt to multiple signal and poor passage cross-correlation angle error demodulating algorithm.But this algorithm is when realizing, because and factor such as difference channel signal propagation delay time difference, can directly cause with the difference signal cross-correlation after the loss of correlation peak, and then influence the sensitivity of angle error demodulation, especially under more and more lower signal to noise ratio application background, it is particularly outstanding that this influence seems.
Therefore the signal propagation delay time difference that need calibrate and differ from passage as much as possible guarantees that this algorithm can obtain optimum demodulation performance.
Summary of the invention
Separate the problems referred to above of timing existence at the realization angular error signal in order to overcome two-channel monopulse system and difference cross correlation algorithm track receiver, the invention provides and a kind ofly can save the alignment time, reduce and the loss of difference signal cross-correlation, safeguards system obtains great angle error detection sensitivity, improves the automatic realization and the consistent processing method of difference channel signal propagation delay time calibration of system angle tracking performance.
Above-mentioned purpose of the present invention can reach by following measure: a kind of automatic calibration and the consistent processing method of difference channel signal propagation delay time is characterized in that comprising the steps:
In the digital signal processing module in programmable gate array chip (FPGA), adopt two memories (FIFO1 and FIFO2) by the High Speed System clock control control respectively and, the difference input signal the read-write retardation, by FIFO1 input and road signal, by FIFO2 input difference road signal; In DSP chip (DSP), the logic control program of whole phase calibration process is set, be used to receive the phase alignment order that application software is assigned, the read-write retardation of control break FIFO1 and FIFO2, the DSP program is in conjunction with orientation (pitching) phase shifter, automatically the calibration of channel time delay is finished and differed to organization flow, will be consistent with the calibration of difference channel transfer time delay.
The present invention has following beneficial effect than prior art:
The present invention unites realization by the digital signal processing module of design in FPGA and the control program in the DSP, DSP procedure auto-control calibration flow process, automatically tissue is finished whole calibration process, the monitoring display calibration result, need not more human intervention, to automatically calibrate consistent with difference channel signal propagation delay time difference, effectively overcome two-channel monopulse system and difference cross correlation algorithm track receiver when realizing because and factor such as difference channel signal propagation delay time difference that cause with the loss difference signal cross-correlation peak value, and then the influence of diagonal angle error-detecting sensitivity.
Adopt two memories (FIFO1 and FIFO2) in the FPGA by the High Speed System clock control, respectively control and, the difference input signal the read-write retardation, to reach the purpose of delay variation calibration, the judgement foundation of calibration process is can obtain the output of error voltage maximum value under corresponding read-write delaying state.
The control of the present invention by calibrating hunting zone parameter n by the delay inequality of application software control, can be according to estimating to two channel time delay differences, realize and the calibration control of difference channel time delay difference in relative small range, save the time of calibration process, guaranteed the normal demodulation of angular error signal, reduced associated loss effectively with difference signal, the sensitivity of angle error detection and the tracking accuracy of system angle tracking system have been improved, for antenna realizes that to the tracking target aircraft autotracking provides the reliable technique basis.
Description of drawings
Below in conjunction with drawings and Examples invention is further specified.
Fig. 1 is the control flow block diagram of DSP program of the present invention.
Fig. 2 is the theory diagram that the present invention is used for and differs from cross-correlation extraction angle error voltage.
Embodiment
Consult Fig. 1.In following examples, calibration and difference channel signal propagation delay time consistent processing method be by design in programmable gate array chip (FPGA) digital signal processing module and the control program in the DSP chip (DSP) unite realization.
In the digital signal processing module in programmable gate array chip (FPGA), adopt two memories (FIFO1 and FIFO2) by the High Speed System clock control control respectively and, the read-write retardation of difference input signal, the system works clock directly determine and differs from the precision of channel signal propagation delay time calibration.Input and road signal change its retardation by FIFO1, and input difference road signal changes its retardation by FIFO2; In DSP chip (DSP), design the logic control program of whole time delay calibration process, be used to receive the time delay calibration command that application software is assigned, the read-write retardation of FIFO1 and FIFO2 in the control break FPGA, the DSP program is in conjunction with orientation (pitching) phase shifter, and tissue will be consistent with the calibration of difference channel transfer time delay automatically.
Apparatus is got the application software that reaches time delay calibration command function ready and is assigned the time delay calibration command, receive this order by the DSP program, start calibration process, the DSP program control changes the read-write retardation of FIFO1 and FIFO2, carry out the search of optimal delay amount, last DSP program is set to the Search Results of retardation in the FPGA, will be consistent with the calibration of difference channel signal propagation delay time, finish whole calibration process.
The read-write degree of depth of FIFO1, FIFO2 is N, the maximum delay scope that the size decision of N and difference channel signal propagation delay time can be calibrated.In the time delay calibration process, the read-write retardation that the DSP program at first is provided with FIFO2 is N/2, the read-write retardation of control FIFO1 changes (N/2-n)～(N/2+n) scope in, carries out the search that the best of FIFO1 is read and write retardation n1 in the time delay control range an of ± n High Speed System clock correspondence; The read-write retardation of DSP program control FIFO2 is N/2 then, the read-write retardation of FIFO1 is n1, will be with to differ from two channel signal propagation delay times calibrations consistent, and wherein n is the scope that the time delay calibration is searched for, n≤N/2 is a controllable parameter that is changed by above-mentioned application software.
In the search procedure of FIFO1 optimal delay amount n1, the DSP program at first is set at N/2 with the read-write retardation of FIFO2, the read-write retardation of controlling then FIFO1 changes in (N/2-n)～(N/2+n) scope successively, each read-write retardation that changes FIFO1, the phase shift value that the DSP program is just controlled FPGA inner orientation (pitching) phase shifter changes in 0 °～180 ° scopes, the read-write retardation of error voltage maximum value point in the record phase shift process and current FIFO1, DSP program pairing state of a control according to angle error voltage maximum value point in (2n+1) individual state of noting is best as decision rule, finds out the best read-write retardation n1 of FIFO1.Be chosen in 180 ° and search in the non-360-degree scope, can on the basis that does not influence calibration result, shorten the time of whole calibration process.After finishing the time delay calibration process, the DSP Automatic Program is provided with time delay calibration result n1, N/2 in FPGA, will be with to differ from two channel signal propagation delay times calibrations consistent, and be reported to application software to be monitored it.
Whole calibration process is an operating in a key, only needs application software to assign a control command, can automatically realize the The whole control flow process.
Above-described only is the preferred embodiments of the present invention.Should be pointed out that for the person of ordinary skill of the art, under the prerequisite that does not break away from the principle of the invention, can also make some distortion and improvement, these changes and change should be considered as belonging to protection scope of the present invention.
Claims (5)
1. a calibration and the consistent processing method of difference channel signal propagation delay time automatically is characterized in that comprising the steps:
In the digital signal processing module in programmable gate array chip (FPGA), adopt two memories (FIFO1 and FIFO2) by the High Speed System clock control control respectively and, the difference input signal the read-write retardation, by FIFO1 input and road signal, by FIFO2 input difference road signal; In DSP chip (DSP), the logic control program of whole phase calibration process is set, be used to receive the phase alignment order that application software is assigned, the read-write retardation of control break FIFO1 and FIFO2, the DSP program is in conjunction with orientation (pitching) phase shifter, automatically the calibration of channel time delay is finished and differed to organization flow, will be consistent with the calibration of difference channel transfer time delay.
2. automatic calibration as claimed in claim 1 and the consistent processing method of difference channel signal propagation delay time, it is characterized in that, utilization possesses the application software of assigning time delay calibration command function and assigns the time delay calibration command, receive mentioned order by the DSP program, start calibration process, the DSP program control changes the read-write retardation of FIFO1 and FIFO2, carry out the search of optimal delay amount, be set in the FPGA by the Search Results of DSP program at last retardation, will be consistent with the calibration of difference channel signal propagation delay time, finish whole calibration process.
3. automatic calibration as claimed in claim 2 and the consistent processing method of difference channel signal propagation delay time, in the time delay calibration process, the read-write retardation that the DSP program at first is provided with FIFO2 is N/2, the read-write retardation of control FIFO1 changes in (N/2-n)～(N/2+n) scope, in the time delay control range an of ± n High Speed System clock correspondence, carry out the search of the best read-write retardation n1 of FIFO1; Read-write retardation by DSP program control FIFO2 is N/2 then, the read-write retardation of FIFO1 is n1, will be with to differ from two channel signal propagation delay times calibrations consistent, and wherein n is the scope that the time delay calibration is searched for, n≤N/2 is a controllable parameter that is changed by above-mentioned application software.
4. automatic calibration as claimed in claim 3 and the consistent processing method of difference channel signal propagation delay time, it is characterized in that, in the search procedure of described FIFO1 optimal delay amount n1, the DSP program at first is set at N/2 with the read-write retardation of FIFO2, the read-write retardation of controlling then FIFO1 changes in (N/2-n)～(N/2+n) scope successively, each read-write retardation that changes FIFO1, the phase shift value that the DSP program is just controlled FPGA inner orientation (pitching) phase shifter changes in 0 °～180 ° scopes, the read-write retardation of error voltage maximum value point in the record phase shift process and current FIFO1, DSP program pairing state of a control according to angle error voltage maximum value point in (2n+1) individual state of noting is best as decision rule, finds out the best read-write retardation n1 of FIFO1.
5. automatic calibration as claimed in claim 1 and difference channel signal propagation delay time consistent processing method is characterized in that the read-write degree of depth of FIFO1, FIFO2 is N, the maximum delay scope that the size of N has determined and difference channel signal propagation delay time can be calibrated.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103066997A (en) * | 2012-11-29 | 2013-04-24 | 电子科技大学 | Two-channel seamless digit delay implementation method based on field programmable gate array (FPGA) |
| CN104731550A (en) * | 2015-03-12 | 2015-06-24 | 电子科技大学 | Double-clock bidirectional digital delay method based on single FIFO |
| CN105187094A (en) * | 2015-07-13 | 2015-12-23 | 中国电子科技集团公司第十研究所 | Demodulation method of dual-channel tracking receiver frequency spreading and hopping system angle error signal |
| CN107703479A (en) * | 2017-09-25 | 2018-02-16 | 中国电子科技集团公司第三十六研究所 | A kind of method and apparatus eliminated with poor phase difference between channels |
| CN108988928A (en) * | 2018-05-23 | 2018-12-11 | 中国电子科技集团公司第五十四研究所 | A method of the detection of two-channel monopulse angle error is carried out in frequency domain |
| CN109347535A (en) * | 2018-07-02 | 2019-02-15 | 成都国恒空间技术工程有限公司 | A kind of method that the non-blind demodulation of PCMA sends signal delay adjustment |
| WO2021203895A1 (en) * | 2020-04-08 | 2021-10-14 | 长鑫存储技术有限公司 | Training method for semiconductor memory and related device |
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| US20050201454A1 (en) * | 2004-03-12 | 2005-09-15 | Intel Corporation | System and method for automatically calibrating two-tap and multi-tap equalization for a communications link |
| CN101826888A (en) * | 2010-03-15 | 2010-09-08 | 中国电子科技集团公司第十研究所 | Processing method of automatically calibrating sum-and-difference passage spread spectrum code phase to coincidence |
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| US20050201454A1 (en) * | 2004-03-12 | 2005-09-15 | Intel Corporation | System and method for automatically calibrating two-tap and multi-tap equalization for a communications link |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103066997A (en) * | 2012-11-29 | 2013-04-24 | 电子科技大学 | Two-channel seamless digit delay implementation method based on field programmable gate array (FPGA) |
| CN103066997B (en) * | 2012-11-29 | 2016-03-30 | 电子科技大学 | Digital delay implementation method that a kind of binary channels based on FPGA is seamless |
| CN104731550A (en) * | 2015-03-12 | 2015-06-24 | 电子科技大学 | Double-clock bidirectional digital delay method based on single FIFO |
| CN104731550B (en) * | 2015-03-12 | 2017-10-17 | 电子科技大学 | A kind of Clock Doubled bi-directional digital related method thereof based on single FIFO |
| CN105187094A (en) * | 2015-07-13 | 2015-12-23 | 中国电子科技集团公司第十研究所 | Demodulation method of dual-channel tracking receiver frequency spreading and hopping system angle error signal |
| CN105187094B (en) * | 2015-07-13 | 2017-08-04 | 中国电子科技集团公司第十研究所 | The demodulation method of dual-channel track receiver system with frequency spreading and hopping angular error signal |
| CN107703479A (en) * | 2017-09-25 | 2018-02-16 | 中国电子科技集团公司第三十六研究所 | A kind of method and apparatus eliminated with poor phase difference between channels |
| CN107703479B (en) * | 2017-09-25 | 2020-02-07 | 中国电子科技集团公司第三十六研究所 | Method and device for eliminating sum-difference channel phase difference |
| CN108988928A (en) * | 2018-05-23 | 2018-12-11 | 中国电子科技集团公司第五十四研究所 | A method of the detection of two-channel monopulse angle error is carried out in frequency domain |
| CN108988928B (en) * | 2018-05-23 | 2020-09-22 | 中国电子科技集团公司第五十四研究所 | Method for detecting double-channel single-pulse angle error in frequency domain |
| CN109347535A (en) * | 2018-07-02 | 2019-02-15 | 成都国恒空间技术工程有限公司 | A kind of method that the non-blind demodulation of PCMA sends signal delay adjustment |
| WO2021203895A1 (en) * | 2020-04-08 | 2021-10-14 | 长鑫存储技术有限公司 | Training method for semiconductor memory and related device |
| US11579810B2 (en) | 2020-04-08 | 2023-02-14 | Changxin Memory Technologies, Inc. | Semiconductor memory training method and related device |
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Application publication date: 20110824 |