CN103856220A - Radio frequency cancellation system and method for dual-channel receiver of passive radar - Google Patents
Radio frequency cancellation system and method for dual-channel receiver of passive radar Download PDFInfo
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- CN103856220A CN103856220A CN201410036411.6A CN201410036411A CN103856220A CN 103856220 A CN103856220 A CN 103856220A CN 201410036411 A CN201410036411 A CN 201410036411A CN 103856220 A CN103856220 A CN 103856220A
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Abstract
The invention discloses a radio frequency cancellation system and method for a dual-channel receiver of a passive radar. The cancellation system comprises an analog phase shifter, an analog attenuator, a radio frequency switch, a combiner, a first digital analog converter, a second digital analog converter, an FPGA controller, an FLASH storage and an upper computer. The cancellation method comprises the calibration stage and the radar working stage, wherein in the calibration stage, the dual-channel receiver controls a target echo receiving antenna to rotate by a circle at the set step length, a system is calibrated in every direction, and an attenuator code word and a phase shifter code word in each direction are obtained; the radar works normally. The radio frequency cancellation system and method are simple, direct wave signals are restrained by more than 30 dB through radio frequency cancellation, the cancellation ratio is large, the dynamic receiving range of the whole radar is wider, and the requirement that a weak target reflection signal is extracted from an external radiation source signal is met.
Description
Technical field
The invention belongs to radio-frequency technique field, be specifically related to a kind of passive radar two-channel receiver radio frequency cancellation system and method.
Background technology
We know, passive radar utilizes external radiation source (transmitting of TV, broadcast, the mobile radio communication) detection of a target, and itself is emitting electromagnetic wave initiatively not, is not easy to be found by enemy's reconnaissance system.Therefore passive radar have disguised high, the advantage such as antijamming capability is strong, and operating distance is far away, this is significant for the survival ability that improves the Military Electronics system under modern electronic warfare environment.
Because the power of external radiation source signal is relatively little, thereby the signal power reflecting by target is also just fainter; Meanwhile, be also mixed with and from direct access, reveal the tetanic arrived wave signal of coming in target echo receive path, this will certainly flood real target position information.Conventionally, in radar and external radiation source in 10Km situation, more than arriving the high 70dB of the relative target echo signal power of direct-path signal at radar receiver place, so, direct wave is effectively suppressed and extracts the weak target reflected signal being submerged in direct wave to become a difficult problem of Passive Radar System.For solving this difficult problem, low sidelobe antenna is generally taked in this area, radio frequency offsets, the technical measures such as adaptive-filtering, wherein, it is to utilize direct wave reception antenna and target echo reception antenna to receive respectively direct wave and target echo that radio frequency offsets, radar receiver adopts two-channel receiver, the direct wave that direct wave antenna reception is arrived is after low noise amplifier is processed, enter radio frequency cancellation system by power splitter again, using the direct wave channel signal that enters radio frequency cancellation system as with reference to signal, adopt cancellation techniques to suppress the direct wave channel signal of sneaking in target echo channel signal.At present, the circuit complexity of general radio frequency cancellation system, and offset DeGrain, can only realize the cancellation ratio of 20dB left and right, difference power after cancellation ratio refers to and offsets the direct-path signal power of sneaking in front target echo passage and offset, makes the reception dynamic range of radar be difficult to meet the requirement of extracting weak target reflected signal from external radiation source signal.
Summary of the invention
The object of the invention is to, a kind of passive radar two-channel receiver radio frequency cancellation system and implementation method are provided, this system and implementation method are simple, offset more than direct-path signal inhibition 30dB by radio frequency, cancellation ratio is large, make the reception dynamic range of whole radar higher, meet the requirement of extracting weak target reflected signal from external radiation source signal.
In order to realize above-mentioned task, the present invention takes following technical solution:
A kind of passive radar two-channel receiver radio frequency cancellation system, comprises analog phase shifter, analog attenuator, radio-frequency (RF) switch, mixer, the first digital to analog converter, the second digital to analog converter, FPGA controller, FLASH memory and host computer, wherein:
Analog phase shifter connects the analog output of the second digital to analog converter, the direct wave channel signal of power splitter transmission and the input of analog attenuator, send the control voltage of Yi road direct wave channel signal and the output of the second analog to digital converter for receiving power splitter, and according to controlling voltage, direct wave channel signal is carried out to phase shift processing, direct wave channel signal after treatment phase shift is sent to analog attenuator;
Analog attenuator connects analog output, the output of analog phase shifter and the input of radio-frequency (RF) switch of the first digital to analog converter, for receiving the direct wave channel signal of analog phase shifter transmission and the control voltage of the first analog to digital converter output, and according to controlling voltage, direct wave channel signal is carried out to attenuation processing, and the direct wave channel signal after attenuation processing is sent to radio-frequency (RF) switch;
Output of the output of radio-frequency (RF) switch connecting analog attenuator, FPGA controller and an input of mixer, carry out opening and closing for the open command and the out code that send according to FPGA controller, under opening, receive in real time the direct wave channel signal that analog attenuator sends, and this signal is sent to mixer;
The output of mixer linking objective echo channel signal and radio-frequency (RF) switch, for being added the target echo channel signal of direct wave channel signal and radio-frequency (RF) switch transmission to be combined into a road signal output;
The digital input end of the first digital to analog converter connects FPGA controller, and its analog output connects attenuator, controls voltage to analog attenuator in order to output, thereby changes the attenuation of analog attenuator;
The digital input end of the second digital to analog converter connects FPGA controller; Its analog output connecting analog phase shifter, controls voltage to analog phase shifter in order to output, thereby changes the amount of phase shift of analog phase shifter;
FPGA controller connects radio-frequency (RF) switch, the first digital to analog converter, the second digital to analog converter, host computer, FLASH memory; For controlling the opening and closing of radio-frequency (RF) switch; Adjust instruction and phase adjusted instruction for the amplitude that receives host computer, and export control signal according to amplitude adjustment instruction and phase adjusted instruction to the first digital to analog converter and the second digital to analog converter; And deposit according to azimuth information and frequency point information correspondence the phase shifter code word of sending into the first digital to analog converter in FLASH memory with the attenuator code word of sending into the second digital to analog converter;
FLASH memory connects FPGA controller, for store directions information and frequency point information and corresponding phase shifter code word and attenuator code word thereof;
Host computer connects FPGA controller, adjusts instruction for send radio-frequency (RF) switch open command, amplitude adjustment instruction and phase place to FPGA controller.
Further, described system also comprises the 100M clock being connected with FPGA controller.
Further, described host computer connects FPGA controller by CAN bus.
The radio frequency of applying above-mentioned passive radar two-channel receiver radio frequency cancellation system offsets method, comprises calibration phase and radar working stage:
Calibration phase:
Two-channel receiver control target echo reception antenna rotates a circle to set step-length, and in each orientation, system is demarcated; Obtain under each orientation, system offsets effect and meets while being not less than 30dB, attenuator code word and phase shifter code word that FPGA controller sends to the first digital to analog converter and the second digital to analog converter respectively, and deposit them in FLASH memory;
Radar working stage:
(1) what two-channel receiver Real-Time Monitoring host computer sent offsets instruction; Offset instruction if receive, two-channel receiver carries out direct wave passage and the reception of target echo channel signal by direct wave reception antenna and target echo reception antenna simultaneously; Enter step (2);
(2) host computer is opened to FPGA controller transmission unlatching control command radio-frequency (RF) switch; Host computer sends code-disc information and the frequency point information of current time to FPGA controller, FPGA controller is according to code-disc information and frequency point information, from FLASH memory, read phase shifter code word corresponding to this group code dish information and frequency point information and attenuator code word, and they are sent into respectively to the first digital to analog converter and the first digital to analog converter; The first digital to analog converter, according to the attenuator code word receiving, is controlled voltage to analog attenuator output; The second digital to analog converter arrives phase shifter code word to analog phase shifter output control voltage according to receiving; Analog phase shifter carries out phase shift processing according to the control voltage receiving to direct wave signal of communication; The direct wave channel signal that analog attenuator sends analog phase shifter according to the control voltage receiving carries out attenuation processing; The target echo channel signal that the direct wave channel signal that mixer sends radio-frequency (RF) switch and target echo reception antenna send is merged into a road signal and outputs to frequency mixer.
Further, in described calibration phase, the step-length of described target echo reception antenna rotation is 1 °.
Further, in described calibration phase, the concrete steps of in each orientation, system being demarcated are as follows:
(1) radar two-channel receiver judges whether the demarcation instruction of receiving that host computer is sent, if receive demarcation instruction, radar two-channel receiver receives direct-path signal and target echo signal by direct wave reception antenna and target echo reception antenna simultaneously, enters step (2);
(2) the intermediate frequency output signal power of the target echo channel signal that signal processor record object echo reception antenna receives; Enter step (3);
(3) host computer sends and demarcates open command to FPGA controller, and FPGA controller control radio-frequency (RF) switch is opened, and makes the direct-path signal of analog attenuator to send to mixer by radio-frequency (RF) switch; Host computer generation amplitude adjusts instruction and phase place is adjusted instruction and sends to FPGA controller, FPGA controller is adjusted instruction according to the amplitude receiving and is sent attenuator code word to the first digital to analog converter, adjusts instruction send phase shifter code word to the second digital to analog converter according to the phase place receiving; Until the difference of the power that the intermediate frequency output signal power of the target echo channel signal that signal processor obtains obtains than step (2) is not less than 30dB, and record attenuator code word and the phase shifter code word of current time;
The first digital to analog converter, according to the attenuator code word receiving, is controlled voltage to analog attenuator output; The second digital to analog converter arrives phase shifter code word to analog phase shifter output control voltage according to receiving; Analog phase shifter carries out phase shift processing according to the control voltage receiving to direct wave channel signal; The direct wave channel signal that analog attenuator 2 sends analog phase shifter according to the control voltage receiving carries out attenuation processing; The target echo channel signal that the direct wave channel signal that mixer sends radio-frequency (RF) switch and target echo reception antenna send is merged into a road signal and outputs to frequency mixer; The power of the intermediate frequency output signal power of the target echo channel signal sending from frequency mixer and step (2) record is done poor the poor of power that obtain by signal processor;
Enter step (4);
(4) FPGA controller receives the storage instruction that host computer sends, and according to storage instruction, deposit with azimuth information and the frequency point information of the corresponding current time of attenuator code word that sends to the first digital to analog converter the phase shifter code word that sends to the first digital to analog converter in FLASH memory;
(5) host computer sends out code to FPGA controller, and FPGA controller control radio-frequency (RF) switch is closed, and so far, the calibration phase in an orientation of target echo reception antenna finishes.
Further, described phase shifter code word and attenuator code word are 12 Bits Serial data.
Further, in described step (3), host computer is adjusted out of phase and amplitude is divided into coarse adjustment process and accurate adjustment process:
Coarse adjustment process: host computer changes taking step-length as 4dB within the scope of 0～64dB according to amplitude, and under each definite amplitude, phase place is changed to the adjustment instruction of generation amplitude and phase place adjustment instruction with 1～10 ° of step-length within the scope of 0～540 °, and each amplitude adjustment instruction and phase bit instruction are sent; If the difference of the power that the intermediate frequency output signal power of the target echo channel signal that signal processor obtains obtains than step (2) is not less than 30dB, stop adjusting; Otherwise enter accurate adjustment;
Accurate adjustment process: record maximum amplitude and the phase place of difference that makes power in coarse adjustment process, the amplitude that makes direct wave channel signal this amplitude ± change taking step-length as 0.02dB within the scope of 4dB, and under each definite amplitude, make phase place this phase place ± 1～10 ° within the scope of with 0.2 ° of variation of step-length, if the difference power that the intermediate frequency output signal power of the target echo channel signal that signal processor obtains obtains than step (2) is not less than 30dB, stop adjusting.
Compared with prior art, advantage of the present invention is as follows:
1, in the present invention, direct wave channel signal carries out the adjustment of power and phase place through analog attenuator, analog phase shifter successively, then superpose and offset in mixer with target echo channel signal, realized with target echo channel signal in direct wave component there is small amplitude difference and approach the phase difference of 180 degree, effectively realize and offseting.
2, adopt host computer under each orientation of target echo reception antenna, two of FPGA control circuit controls are not less than the digital to analog converter output of 12 as the control voltage of analog phase shifter and analog attenuator, through coarse adjustment and the accurate adjustment process of phase place and amplitude, make the precision of phase-shift phase, attenuation of direct wave channel signal higher.
3, radio frequency cancellation system circuit of the present invention is simple, and method is simple, more than cancellation ratio can reach 30dB, is very easy to realize sneaking into the inhibition of the direct-path signal in target echo passage.
Brief description of the drawings
Fig. 1 is the theory diagram of passive radar two-channel receiver radio frequency cancellation system of the present invention.
Fig. 2 is the flow chart that passive radar two-channel receiver radio frequency of the present invention offsets the calibration phase in method.
Fig. 3 is the flow chart that offsets that passive radar two-channel receiver radio frequency of the present invention offsets radar normal work stage in method.
Below in conjunction with drawings and Examples, the present invention is described in further detail.
Embodiment
Theoretical foundation of the present invention is that two-way amplitude signal identical and single spin-echo is cancelled out each other by vector superposed, thereby reaches the wherein effect of a road signal of inhibition.In actual conditions, as long as there is very little amplitude difference and contrary phase difference in two paths of signals, after mixer coherent superposition, will produce and offset effect, as the difference power of two paths of signals is less than 0.1dB, inverted phases is poor is less than 1 °, and after offseting, wherein a road signal power will be than offseting the front lower 30dB of falling above (cancellation ratio).
Passive radar two-channel receiver radio frequency cancellation system of the present invention, comprises analog phase shifter 1, analog attenuator 2, radio-frequency (RF) switch 3, mixer 4, the first digital to analog converter 5, the second digital to analog converter 6, FPGA controller 7, FLASH memory 8, host computer 9 and 100M clock 10.Wherein:
Analog phase shifter 1 connects the analog output of the second digital to analog converter 6, the direct wave channel signal of power splitter transmission and the input of analog attenuator 2, the control voltage of exporting for receiving power splitter transmission Yi road direct wave channel signal and the second analog to digital converter 6, and according to controlling voltage, direct wave channel signal is carried out to phase shift processing, direct wave channel signal after treatment phase shift is sent to analog attenuator 2;
Analog attenuator 2 connects analog output, the output of analog phase shifter 1 and the input of radio-frequency (RF) switch of the first digital to analog converter 5, the control voltage of exporting for receiving direct wave channel signal that analog phase shifter 1 sends and the first analog to digital converter 5, and according to controlling voltage, direct wave channel signal is carried out to attenuation processing, and the direct wave channel signal after attenuation processing is sent to radio-frequency (RF) switch 3;
Output of the output of radio-frequency (RF) switch 3 connecting analog attenuators 2, FPGA controller 7 and an input of mixer 4, carry out opening and closing for the open command and the out code that send according to FPGA controller 7, under opening, receive in real time the direct wave channel signal that analog attenuator 2 sends, and this signal is sent to mixer 4;
The output of mixer 4 linking objective echo channel signals and radio-frequency (RF) switch 3, is added and is combined into a road signal output for the target echo channel signal that direct wave channel signal and radio-frequency (RF) switch 3 are sent;
The digital input end of the first digital to analog converter 5 connects FPGA controller 7, and its analog output connects attenuator 2, controls voltage to analog attenuator 2 in order to output, thereby changes the attenuation of analog attenuator 2;
The digital input end of the second digital to analog converter 6 connects FPGA controller 7; Its analog output connecting analog phase shifter 1, controls voltage to analog phase shifter 1 in order to output, thereby changes the amount of phase shift of analog phase shifter 1;
FLASH memory 8 connects FPGA controller 7, for store directions information and frequency point information and corresponding phase shifter code word and attenuator code word thereof.
Above-mentioned passive radar two-channel receiver radio frequency offsets method, comprises calibration phase and radar working stage:
1, calibration phase: radar receiver control target echo reception antenna is taking step-length 1 ° as one orientation rotation one week (0～360 °), and system is demarcated corresponding definite code-disc information and the frequency point information in each orientation in each orientation; In each orientation, (in each definite code-disc information and frequency point information) upper concrete steps that system is demarcated are as follows:
(1) radar two-channel receiver judges whether the demarcation instruction of receiving that host computer 9 is sent, if receive demarcation instruction, radar two-channel receiver receives direct-path signal and target echo signal by direct wave reception antenna and target echo reception antenna simultaneously, enters step (2);
(2) the intermediate frequency output signal power of the target echo channel signal that signal processor record object echo reception antenna receives; Enter step (3);
(3) host computer 9 sends and demarcates open command to FPGA controller 7, and FPGA controller 7 is controlled radio-frequency (RF) switch 3 and opened, and makes the direct-path signal of analog attenuator 2 to send to mixer 4 by radio-frequency (RF) switch; Host computer 9 generation amplitudes adjust instruction and phase place is adjusted instruction and sends to FPGA controller 7, FPGA controller 7 is adjusted instruction according to the amplitude receiving and is sent control signal (being called attenuator code word) to the first digital to analog converter 5, adjusts instruction send control signal (being called phase shifter code word) to the second digital to analog converter 6 according to the phase place receiving; Phase shifter code word and attenuator code word are 12 Bits Serial data; Until the difference power that the intermediate frequency output signal power of the target echo channel signal that signal processor obtains obtains than step (2) is not less than 30dB, and record attenuator code word and the phase shifter code word of current time; This attenuator code word and phase shifter code word are to make target echo antenna under current orientation (being current code-disc information and frequency point information), and system of the present invention offsets effect and meets the best code word that is not less than 30dB;
In said process, the first digital to analog converter 5, according to the attenuator code word receiving, is controlled voltage to analog attenuator 2 outputs; The second digital to analog converter 6 arrives phase shifter code word to analog phase shifter 1 output control voltage according to receiving; Analog phase shifter 1 carries out phase shift processing according to the control voltage receiving to direct wave channel signal; The direct wave channel signal that analog attenuator 2 sends analog phase shifter 1 according to the control voltage receiving carries out attenuation processing; The target echo channel signal that the direct wave channel signal that mixer 4 sends radio-frequency (RF) switch 3 and target echo reception antenna send is merged into a road signal and outputs to frequency mixer 11; The power of the intermediate frequency output signal power of the target echo channel signal sending from frequency mixer 11 and step (2) record is done the poor difference power that obtains by signal processor 13.
In said process, host computer 9 generates adjusting range adjustment instruction and phase place adjustment instruction is divided into coarse adjustment and accurate adjustment: coarse adjustment process is: host computer 9 changes taking step-length as 4dB within the scope of 0～64dB according to amplitude, and under each definite amplitude, phase place is changed to the adjustment instruction of generation amplitude and phase place adjustment instruction with 1～10 ° of step-length within the scope of 0～540 °, and each amplitude adjustment instruction and phase bit instruction are sent; If the difference power that the intermediate frequency output signal power of the target echo channel signal that signal processor 13 obtains obtains than step (2) is not less than 30dB, stop adjusting; Otherwise enter accurate adjustment, accurate adjustment process is: record the amplitude and the phase place that in coarse adjustment process, make difference power maximum, the amplitude that makes direct wave channel signal this amplitude ± change taking step-length as 0.02dB within the scope of 4dB, and under each definite amplitude, make phase place this phase place ± 1～10 ° within the scope of with 0.2 ° of variation of step-length, if the difference power that the intermediate frequency output signal power of the target echo channel signal that signal processor 13 obtains obtains than step (2) is not less than 30dB, stop adjusting.
Enter step (4);
(4) FPGA controller 7 receives the storage instruction that host computer 9 sends, and according to storage instruction, deposit with orientation (code-disc) information and the frequency point information of the corresponding current time of attenuator code word that sends to the first digital to analog converter 6 the phase shifter code word that sends to the first digital to analog converter 5 in FLASH memory 8;
(5) host computer 9 sends out code to FPGA controller 7, and FPGA controller 7 controls radio-frequency (RF) switch 3 and cuts out, and so far, the calibration phase in an orientation of target echo reception antenna finishes.
2, radar working stage
(1) after calibration phase finishes, system enters radar working stage, and within this stage, what two-channel receiver Real-Time Monitoring host computer 9 sent offsets instruction; Offset instruction if receive, two-channel receiver carries out direct wave passage and the reception of target echo channel signal by direct wave reception antenna and target echo reception antenna simultaneously; Enter step (2);
(2) host computer 9 is opened to FPGA controller 7 transmission unlatching control command radio-frequency (RF) switch 3; Host computer 9 sends code-disc information and the frequency point information (being the orientation of current goal echo reception antenna) of current time to FPGA controller 7, FPGA controller 7 is according to code-disc information and frequency point information, from FLASH memory 8, read phase shifter code word corresponding to this group code dish information and frequency point information and attenuator code word, and they are sent into respectively to the first digital to analog converter 5 and the first digital to analog converter 6; The first digital to analog converter 5, according to the attenuator code word receiving, is controlled voltage to analog attenuator 2 outputs; The second digital to analog converter 6 arrives phase shifter code word to analog phase shifter 1 output control voltage according to receiving; Analog phase shifter 1 carries out phase shift processing according to the control voltage receiving to direct wave signal of communication; The direct wave channel signal that analog attenuator 2 sends analog phase shifter 1 according to the control voltage receiving carries out attenuation processing; The target echo channel signal that the direct wave channel signal that mixer 4 sends radio-frequency (RF) switch 3 and target echo reception antenna send is merged into a road signal and outputs to frequency mixer 11; The intermediate frequency output signal of the target echo channel signal that frequency mixer 11 is sent is carried out signal processing by signal processor 13.
The technical scheme of following system of the present invention designs, and the system unit of the present embodiment is selected:
Analog phase shifter 1 is obtained by the analog phase shifter HMC934LP5E series connection of Liang Ge Hittite company, and analog attenuator 2 is obtained by the analog attenuator RVA-2000V35+ series connection of Liang Ge Mini company; Device handbook by HMC934LP5E provides, and the control voltage of HMC934LP5E is in the scope of 0-5v, and maximum tunable phase shift scope is 0 °～230 °, and after two HMC934LP5E series connection, maximum tunable phase shift scope is 0 °～460 °.And the phase-shift value of the analog phase shifter obtaining 1 after series connection and control voltage are good linear relationship; Adopt 12 figure place weighted-voltage D/A converter AD5623 outputs to make the voltage controling end of analog phase shifter 1, minimum tunable phase shift precision is 0.2 °.The control voltage of RVA-2000V35+ is in the scope of 0～2v, maximum adjustable damping scope is 0dB-32dB, the maximum adjustable damping scope of the analog attenuator 2 obtaining after two RVA-2000V35+ series connection is 0dB～64dB, equally, adopt AD5623 output to make the voltage controling end of analog attenuator 2, minimum adjustable damping precision is 0.02dB.The design objective of analog phase shifter 1 and analog attenuator 2 has ensured that the direct wave channel signal after adjustment and the direct-path signal in target echo have the difference power of 0.02dB, contrary phase difference, thus reach effect more than cancellation ratio 30dB.
The first analog to digital converter 5 and the second analog to digital converter 6 all adopt 12bit Voltage-output type digital to analog converter AD5623.
Claims (8)
1. a passive radar two-channel receiver radio frequency cancellation system, it is characterized in that, comprise analog phase shifter (1), analog attenuator (2), radio-frequency (RF) switch (3), mixer (4), the first digital to analog converter (5), the second digital to analog converter (6), FPGA controller (7), FLASH memory (8) and host computer (9), wherein:
Analog phase shifter (1) connects the analog output of the second digital to analog converter (6), the direct wave channel signal of power splitter transmission and the input of analog attenuator (2), be used for receiving the control voltage of power splitter transmission Yi road direct wave channel signal and the second analog to digital converter (6) output, and according to controlling voltage, direct wave channel signal is carried out to phase shift processing, direct wave channel signal after treatment phase shift is sent to analog attenuator (2);
Analog attenuator (2) connects analog output, the output of analog phase shifter (1) and the input of radio-frequency (RF) switch of the first digital to analog converter (5), be used for receiving the direct wave channel signal of analog phase shifter (1) transmission and the control voltage of the first analog to digital converter (5) output, and according to controlling voltage, direct wave channel signal is carried out to attenuation processing, and the direct wave channel signal after attenuation processing is sent to radio-frequency (RF) switch (3);
Output of the output of radio-frequency (RF) switch (3) connecting analog attenuator (2), FPGA controller (7) and an input of mixer (4), carry out opening and closing for the open command and the out code that send according to FPGA controller (7), under opening, receive in real time the direct wave channel signal that analog attenuator (2) sends, and this signal is sent to mixer (4);
The output of mixer (4) linking objective echo channel signal and radio-frequency (RF) switch (3), for being added the target echo channel signal of direct wave channel signal and radio-frequency (RF) switch (3) transmission to be combined into a road signal output;
The digital input end of the first digital to analog converter (5) connects FPGA controller (7), and its analog output connects attenuator (2), controls voltage to analog attenuator (2) in order to output, thereby changes the attenuation of analog attenuator (2);
The digital input end of the second digital to analog converter (6) connects FPGA controller (7); Its analog output connecting analog phase shifter (1), controls voltage to analog phase shifter (1) in order to output, thereby changes the amount of phase shift of analog phase shifter (1);
FPGA controller (7) connects radio-frequency (RF) switch (3), the first digital to analog converter (5), the second digital to analog converter (6), host computer (9), FLASH memory (8); Be used for controlling the opening and closing of radio-frequency (RF) switch (3); Be used for receiving amplitude adjustment instruction and the phase adjusted instruction of host computer (9), and export control signal according to amplitude adjustment instruction and phase adjusted instruction to the first digital to analog converter (5) and the second digital to analog converter (6); And deposit according to azimuth information and frequency point information correspondence the phase shifter code word of sending into the first digital to analog converter (5) in FLASH memory (8) with the attenuator code word of sending into the second digital to analog converter (6);
FLASH memory (8) connects FPGA controller (7), for store directions information and frequency point information and corresponding phase shifter code word and attenuator code word thereof;
Host computer (9), by connecting FPGA controller (7), is adjusted instruction for send radio-frequency (RF) switch open command, amplitude adjustment instruction and phase place to FPGA controller (7).
2. passive radar two-channel receiver radio frequency cancellation system as claimed in claim 1, is characterized in that, described system also comprises the 100M clock (10) being connected with FPGA controller (7).
3. passive radar two-channel receiver radio frequency cancellation system as claimed in claim 1, is characterized in that, described host computer (9) connects FPGA controller (7) by CAN bus (14).
4. application rights requires the passive radar two-channel receiver radio system described in 1 to carry out the method that radio frequency offsets, and it is characterized in that, comprises calibration phase and radar working stage:
Calibration phase:
Two-channel receiver control target echo reception antenna rotates a circle to set step-length, and in each orientation, system is demarcated; Obtain under each orientation, system offsets effect and meets while being not less than 30dB, attenuator code word and phase shifter code word that FPGA controller (7) sends to the first digital to analog converter (5) and the second digital to analog converter (6) respectively, and deposit them in FLASH memory (8);
Radar working stage:
(1) what two-channel receiver Real-Time Monitoring host computer (9) sent offsets instruction; Offset instruction if receive, two-channel receiver carries out direct wave passage and the reception of target echo channel signal by direct wave reception antenna and target echo reception antenna simultaneously; Enter step (2);
(2) host computer (9) is opened to FPGA controller (7) transmission unlatching control command radio-frequency (RF) switch (3); Host computer (9) sends code-disc information and the frequency point information of current time to FPGA controller (7), FPGA controller (7) is according to code-disc information and frequency point information, from FLASH memory (8), read phase shifter code word corresponding to this group code dish information and frequency point information and attenuator code word, and they are sent into respectively to the first digital to analog converter (5) and the first digital to analog converter (6); The first digital to analog converter (5), according to the attenuator code word receiving, is controlled voltage to analog attenuator (2) output; The second digital to analog converter (6) arrives phase shifter code word to analog phase shifter (1) output control voltage according to receiving; Analog phase shifter (1) carries out phase shift processing according to the control voltage receiving to direct wave signal of communication; The direct wave channel signal that analog attenuator (2) sends analog phase shifter (1) according to the control voltage receiving carries out attenuation processing; The target echo channel signal that the direct wave channel signal that mixer (4) sends radio-frequency (RF) switch (3) and target echo reception antenna send is merged into a road signal and is outputed to frequency mixer (11).
5. passive radar two-channel receiver radio frequency as claimed in claim 4 offsets method, it is characterized in that, in described calibration phase, the step-length of described target echo reception antenna rotation is 1 °.
6. passive radar two-channel receiver radio frequency as claimed in claim 4 offsets method, it is characterized in that, in described calibration phase, the concrete steps of in each orientation, system being demarcated are as follows:
(1) radar two-channel receiver judges whether the demarcation instruction of receiving that host computer (9) is sent, if receive demarcation instruction, radar two-channel receiver receives direct-path signal and target echo signal by direct wave reception antenna and target echo reception antenna simultaneously, enters step (2);
(2) the intermediate frequency output signal power of the target echo channel signal that signal processor record object echo reception antenna receives; Enter step (3);
(3) host computer (9) sends and demarcates open command to FPGA controller (7), and FPGA controller (7) is controlled radio-frequency (RF) switch (3) and opened, and makes the direct-path signal of analog attenuator (2) to send to mixer (4) by radio-frequency (RF) switch; Host computer (9) generation amplitude adjusts instruction and phase place is adjusted instruction and sends to FPGA controller (7), FPGA controller (7) is adjusted instruction according to the amplitude receiving and is sent attenuator code word to the first digital to analog converter (5), adjusts instruction send phase shifter code word to the second digital to analog converter (6) according to the phase place receiving; Until the difference power that the intermediate frequency output signal power of the target echo channel signal that signal processor obtains obtains than step (2) is not less than 30dB, and record attenuator code word and the phase shifter code word of current time;
The first digital to analog converter (5), according to the attenuator code word receiving, is controlled voltage to analog attenuator (2) output; The second digital to analog converter (6) arrives phase shifter code word to analog phase shifter (1) output control voltage according to receiving; Analog phase shifter (1) carries out phase shift processing according to the control voltage receiving to direct wave channel signal; The direct wave channel signal that analog attenuator (2) sends analog phase shifter (1) according to the control voltage receiving carries out attenuation processing; The target echo channel signal that the direct wave channel signal that mixer (4) sends radio-frequency (RF) switch (3) and target echo reception antenna send is merged into a road signal and is outputed to frequency mixer (11); The power of the intermediate frequency output signal power of the target echo channel signal sending from frequency mixer 11 and step (2) record is done the poor difference power that obtains by signal processor 13;
Enter step (4);
(4) FPGA controller (7) receives the storage instruction that host computer (9) sends, and according to storage instruction, deposit with azimuth information and the frequency point information of the corresponding current time of attenuator code word that sends to the first digital to analog converter (6) the phase shifter code word that sends to the first digital to analog converter (5) in FLASH memory (8);
(5) host computer (9) sends out code to FPGA controller (7), and FPGA controller (7) controls radio-frequency (RF) switch (3) and cuts out, and so far, the calibration phase in an orientation of target echo reception antenna finishes.
7. passive radar two-channel receiver radio frequency as claimed in claim 4 offsets method, it is characterized in that, described phase shifter code word and attenuator code word are 12 Bits Serial data.
8. passive radar two-channel receiver radio frequency as claimed in claim 4 offsets method, it is characterized in that, in described step (3), host computer (9) is adjusted out of phase and amplitude is divided into coarse adjustment process and accurate adjustment process:
Coarse adjustment process: host computer (9) changes taking step-length as 4dB within the scope of 0～64dB according to amplitude, and under each definite amplitude, phase place is changed to the adjustment instruction of generation amplitude and phase place adjustment instruction with 1～10 ° of step-length within the scope of 0～540 °, and each amplitude adjustment instruction and phase bit instruction are sent; If the difference power that the intermediate frequency output signal power of the target echo channel signal that signal processor 13 obtains obtains than step (2) is not less than 30dB, stop adjusting; Otherwise enter accurate adjustment;
Accurate adjustment process: record the amplitude and the phase place that make difference power maximum in coarse adjustment process, the amplitude that makes direct wave channel signal this amplitude ± change taking step-length as 0.02dB within the scope of 4dB, and under each definite amplitude, make phase place this phase place ± 1～10 ° within the scope of with 0.2 ° of variation of step-length, if the difference power that the intermediate frequency output signal power of the target echo channel signal that signal processor 13 obtains obtains than step (2) is not less than 30dB, stop adjusting.
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