CN114665908B - Attenuation phase shifting system with adjustable amplitude and phase precision - Google Patents

Attenuation phase shifting system with adjustable amplitude and phase precision Download PDF

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CN114665908B
CN114665908B CN202210281221.5A CN202210281221A CN114665908B CN 114665908 B CN114665908 B CN 114665908B CN 202210281221 A CN202210281221 A CN 202210281221A CN 114665908 B CN114665908 B CN 114665908B
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phase
bit
bits
attenuation
control
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CN114665908A (en
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庞东伟
金来福
丁德志
韦玲玲
王小虎
吴士伟
桂勇锋
段宗明
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CETC 38 Research Institute
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00—Auxiliary devices
    • H01P1/18—Phase-shifters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00—Auxiliary devices
    • H01P1/22—Attenuating devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention discloses an attenuation phase-shifting system with adjustable amplitude and phase precision, belonging to the technical field of chip circuit design, comprises an active numerical control attenuator, an active numerical control phase shifter and a table-look-up code value register. In the invention, under the background that an external system requires 6-bit attenuation 6-bit phase shift, the direct attenuation bit number and the phase shift bit number are respectively increased to 9 bits, so that the amplitude and phase precision is further improved to be possible; furthermore based on the present architecture of the present invention, under the conditions of system complexity and permission of the time for writing data into the power-on table-lookup value register, the 9-bit direct control bit can be increased still further; and as the direct control bit increases, the corresponding attenuation and phase shift are also respectively increased from the original 64 bits to 512 bits, under the condition that the external 6-bit control bit is unchanged, each attenuation state and each phase shift state can be selected from a plurality of states; for different attenuations of the system the index requirement of the phase-shifting precision, different code values can be written into a table lookup code value register to realize on-chip adjustment and optimization of the amplitude-phase multifunctional chip.

Description

Attenuation phase shifting system with adjustable amplitude and phase precision
Technical Field
The invention relates to the technical field of chip circuit design, in particular to an attenuation phase shifting system with adjustable amplitude and phase precision.
Background
The realization of high-precision numerical control attenuation and phase shift is a core technology of a phased array receiving and transmitting system, however, certain deviation exists in simulation and actual measurement in the actual chip circuit design. If the 6-bit attenuation and 6-bit displacement are required by the system, if the 6-bit direct control bit attenuator and the 6-bit direct control bit shifter are aimed for simulation during design, a certain amplitude-phase precision offset often exists in actual measurement, and then the chip needs to be repeatedly and iteratively optimized to meet the requirement of expected precision.
Conventional digitally controlled attenuators can typically be implemented in combination with MOS switching transistors, based on passive T or PI type resistive networks, by attenuating the bits for the cells: the cascade of 0.5dB, 1dB, 2dB, 4dB, 8dB and 16dB realizes the attenuation of 6 bits of 0-31.5 dB, but the deviation of the processing, manufacturing or simulation of the resistance value often causes the deviation of the attenuation value. The traditional numerical control phase shifter can be usually combined with a MOS switch tube, and is realized based on a passive T or PI type LC high-low pass network, namely, through unit phase shifting: the cascade of 5.625 degrees, 11.25 degrees, 22.5 degrees, 45 degrees, 90 degrees and 180 degrees realizes 0-354.375 degrees of phase shifting, and the phase shifting value is often offset due to the deviation of L, C machining and manufacturing or simulation. Correction of the amplitude and phase accuracy often requires multiple rounds of iterative optimization, which also further increases the cost of chip development.
The improvement of the amplitude and phase precision can be realized by improving the direct attenuation bit number and the phase shift bit number, the operation is simple and easy, but the following problems exist: the increase of the number of direct attenuation bits and the number of phase shift bits causes the index of the number of bits to be inconsistent with the index of the number of bits required by an external system; even if the number of bits is increased, the offset of the amplitude and phase precision caused by the manufacturing process or simulation deviation of the semiconductor cannot be avoided, and the correction still needs to be realized through multiple rounds of iteration; the on-chip adjustment optimization cannot be realized for index requirements of different attenuation phase shift precision of the system. For this purpose, an attenuated phase shift system with adjustable amplitude and phase accuracy is proposed.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the invention provides an attenuation phase shifting system with adjustable amplitude and phase precision, which solves the problems that amplitude and phase precision of an amplitude and phase control chip in the existing phased array receiving and transmitting system needs to be optimized in a multi-round flow sheet iteration mode and cannot be adjusted in a sheet mode according to amplitude and phase precision index requirements.
The invention solves the technical problems through the following technical scheme that the invention comprises an active numerical control attenuator, an active numerical control phase shifter and a table-lookup code value register; the active digital control attenuator and the active digital control phase shifter are controlled by at least 9 bit control bits, the table lookup code value register comprises a first latch, a second latch, a buffer and an addressing device, serial signals are converted into serial-parallel code values through the first latch, then the second latch is controlled to complete signal latching, writing operation on the table lookup code value register is completed, the 6-bit attenuation address bits and the 6-bit phase shift address bits are used for respectively addressing 64 9-bit binary attenuation codes and 64 9-bit binary phase shift codes through the addressing device, enabling is achieved through controlling a selection switch, the 9-bit attenuation codes and the 9-bit phase shift codes are output to the active digital control attenuator and the active digital control phase shifter respectively, attenuation and phase shift are controlled, and then accuracy adjustment is carried out on 6-bit attenuation and 6-bit phase shift required by a phased array system.
Further, the control bits of the active numerical control attenuator and the active numerical control phase shifter are 9 bits.
Further, the active digital control attenuator is an active digital control variable gain amplifier, the active digital control variable gain amplifier comprises two stages of variable gain amplifiers, and the active digital control variable gain amplifier completes attenuator amplitude modulation through the two stages of variable gain amplifiers.
Furthermore, the active digital control variable gain amplifier has 6 bits, the corresponding control bits are VC 1-VC 6 respectively, the two stages of variable gain amplifiers are cascaded with 12 bits of control bits, the 12 bits of attenuator control bits are reduced to 9 bits, and the corresponding gain ratios are respectively: when the unit gain is converted to 1XdB, the variable gain amplifier can respectively realize the changes of +/-1 XdB, +/-2 XdB, +/-4 XdB, +/-8 XdB, +/-16 XdB and +/-32 XdB by controlling the on and off of the bias of each tail current source.
Still further, the variable gain amplifier includes 6 scaled first Gilbert cells, the 6 scaled first Gilbert cells being connected in parallel to provide gain ratios of 1:2:4:8:16:32, respectively.
Further, the active digital control phase shifter comprises a quadrature signal generator, two VGA variable gain amplifiers and an adder, a pair of radio frequency differential input signals are input into the quadrature signal generator, the quadrature signal generator outputs two orthogonal differential signals I and Q paths, and the I and Q paths of signals respectively pass through one VGA variable gain amplifier and then are combined into one differential signal through the adder.
Further, the active digital controlled variable gain amplifier comprises a phase synthesis circuit and a DAC bias circuit; the phase synthesis circuit comprises MOS transistors M1-M14, wherein the grids of the MOS transistors M1 and M8 are voltage bias ends VB2 and VB4 respectively, and the source electrode is grounded; the drain electrode of the MOS tube M1 is connected with the source electrodes of the MOS tubes M2 and M3, the drain electrode of the MOS tube M8 is connected with the source electrodes of the MOS tubes M9 and M10, and the grid electrodes of the MOS tubes M2 and M3 are connected with the source electrodes of the MOS tubes through the control switches VI and M3
Figure SMS_7
Connected to a voltage bias terminalVB1 and the gates of the MOS transistors M9 and M10 are controlled by switches VQ and +.>
Figure SMS_6
The MOS transistor is connected to a voltage bias end VB3, the drain electrodes of the MOS transistors M2 are connected to the source electrodes of the M4 and M5, the drain electrodes of the MOS transistors M3 are connected to the source electrodes of the MOS transistors M6 and M7, the drain electrode of the MOS transistor M9 is connected to the source electrodes of the MOS transistors M11 and M12, the drain electrode of the MOS transistor M10 is connected to the source electrodes of the MOS transistors M13 and M14, the grid electrodes of the MOS transistors M4 and M7 are connected with RFI+ signals, the grid electrodes of the MOS transistors M5 and M6 are connected with RFI-signals, the grid electrodes of the MOS transistors M11 and M14 are connected with RFQ+ signals, the drain electrodes of the MOS transistors M12 and M13 are connected with RFQ-signals, the drain electrodes of the MOS transistors M4, M6, M11 and M13 are connected with an Iout+ end, and the drain electrodes of the MOS transistors M5, M7 and M12 and M14 are connected with an Iout-end; the DAC bias circuit comprises 7- bit 1X,2X,4X,8X,16X,32X and 64X current bias circuits and MOS tubes M15-M18, wherein the 7-bit current bias circuits respectively pass through paired switch control signals V1 and +.>
Figure SMS_15
V2 and->
Figure SMS_8
V3 and->
Figure SMS_11
V4 and->
Figure SMS_14
V5 and->
Figure SMS_16
V6 and->
Figure SMS_3
V7 and->
Figure SMS_12
Controlling the current flowing through M15, M17, M16 and M18, wherein the source electrodes of the MOS tubes M15 and M16 are grounded, the grid electrodes and the drain electrodes are respectively short-circuited and respectively connected to voltage bias ends VB2 and VB4 and then respectively connected to the source electrodes of the MOS tubes M17 and M18, the grid electrodes and the drain electrodes of the MOS tubes M17 and M18 are respectively short-circuited and respectively connected to voltage bias ends VB1 and VB3 and then respectively connected to V1 to V7 and V1/>
Figure SMS_1
Controlled switches, V1 and->
Figure SMS_10
V2 and->
Figure SMS_4
V3 and->
Figure SMS_17
V4 and->
Figure SMS_5
V5 and->
Figure SMS_13
V6 and->
Figure SMS_2
V7 and->
Figure SMS_9
The controlled switching transistors are short-circuited to 1X,2X,4X,8X,16X,32X,64X current sources, respectively.
Compared with the prior art, the invention has the following advantages: according to the attenuation phase shifting system with adjustable amplitude and phase precision, under the background that an external system requires 6-bit attenuation 6-bit phase shifting, the number of direct attenuation bits and the number of phase shifting bits are respectively increased to 9 bits, so that the amplitude and phase precision is possibly further improved; in addition, based on the architecture, under the conditions that the system complexity and the time allowed for writing data into a power-on table lookup code value register are allowed, the 9-bit direct control bit can be further increased; along with the increase of the direct control bits, the corresponding attenuation and phase shift bits are respectively increased from the original 64 bits to 512 bits, and each attenuation state and phase shift state can be selected from a plurality of states under the condition that the external 6-bit control bits are unchanged; for the index requirements of different attenuation phase shift precision of the system, different code values can be written into a table-lookup code value register to realize on-chip adjustment and optimization of the amplitude-phase multifunctional chip.
Drawings
FIG. 1 is a schematic diagram of an attenuated phase-shift system with adjustable amplitude and phase accuracy in accordance with an embodiment of the present invention;
FIG. 2a is a schematic diagram of a digital controlled active variable gain amplifier based on a CMOS process in an embodiment of the present invention;
FIG. 2b is a schematic circuit diagram of a single 6-bit variable gain amplifier in an embodiment of the present invention;
FIG. 3a is a schematic diagram of an active digital phase shifter based on a CMOS process in an embodiment of the present invention;
fig. 3b is a schematic circuit diagram of an orthogonal two-way variable gain amplifier and adder in an embodiment of the invention.
Detailed Description
The following describes in detail the examples of the present invention, which are implemented on the premise of the technical solution of the present invention, and detailed embodiments and specific operation procedures are given, but the scope of protection of the present invention is not limited to the following examples.
As shown in fig. 1, this embodiment provides a technical solution: the attenuation phase shifting system with adjustable amplitude and phase precision is based on a silicon-based process, realizes the amplitude and phase control of a 9-bit numerical control active attenuator and a 9-bit numerical control active phase shifter by integrating a searchable code value register on a chip under the background that an external system requires 6-bit attenuation and 6-bit phase shifting, and the framework can realize the adjustment and optimization of the amplitude and phase precision by writing data stored in the searchable code value register; theoretically, as the number of direct control bits of the attenuator and the phase shifter increases, the amplitude and phase precision also increases; based on the framework of the invention, high-precision attenuation and phase shift can be realized by expanding the internal attenuation and phase shift direct control bit number of the chip under the condition that the total attenuation and phase shift control bit of an external system is unchanged; the invention is suitable for the microwave millimeter wave receiving and transmitting circuit based on the phased array architecture.
Specifically, the architecture of the invention comprises a 9-bit active numerical control attenuator, a 9-bit active numerical control phase shifter and a table lookup value register. The 1152-bit serial data SDIN passes through the first-stage latch under the condition that the CLK clock signal and the chip selection signal SEL_R are enabled, and then realizes control signal serial-parallel conversion and latching through the second-stage latch signal SYN_R, and then completes the write operation on 128 9-bit binary registers; the 6-bit attenuation address bits A1-A6 and the 6-bit phase shift address bits P1-P6 respectively address 64 9-bit binary attenuation codes and 64 9-bit binary phase shift codes through an addresser, and the desired 9-bit attenuation codes and 9-bit phase shift codes are output through controlling the enabling of a selection switch, so that attenuation and phase shift are controlled.
As shown in fig. 1, the connection implementation manner between each module in the architecture of the present invention is as follows: the table look-up register input signal includes: the serial code input signal SDIN, the clock signal CLK, the chip select signal SEL_R, the two-stage latch signals SYN_ R, A1-A6 6 bit attenuation bit control bits, and the P1-P6 6 bit attenuation bit control bits, and the output signal of the table lookup code value register comprises: AA 1-AA 9 9 direct attenuator control bit sum PP 1-PP 9 9 bits direct phase shifter control bits; AA 1-AA 9 are connected with attenuator control bits, and PP 1-PP 9 are connected with phase shifter control bits.
The table lookup code value register internal module connection implementation mode is as follows: the code value is respectively latched into P1-P9, P10-P18 … P1135-P1143 and P1144-P1152 through two-stage latches, the total number of the 9-bit 2 system registers is 128, the address bits A1-A6 and P1-P6 are input through an addressing device, the output control signals of the addressing device are respectively connected to the 128 registers to control the corresponding 9-bit attenuation and phase shift control code output, and the output signals are finally output through a buffer.
As shown in fig. 2a and 2b, the schematic diagrams of the structure of the digital controlled active variable gain amplifier based on the CMOS process and the schematic circuit diagram of the single 6-bit variable gain amplifier are respectively designed in the invention, and the function of 9-bit digital controlled attenuation is realized through the active digital controlled variable gain amplifier. The circuit implementation is as follows: the active numerical control variable gain amplifier is realized by cascading two stages of 6-bit variable gain amplifiers, and each stage of variable gain amplifier is realized in the same principle, namely, is realized by parallel connection of 6 proportional Gilbert units. Wherein 6 Gilbert units provide gain ratios of 1:2:4:8:16:32, respectively, and the unit gain conversion is 1XdB, the gain of the variable gain amplifier is changed by controlling the on and off of each tail current source bias to achieve the changes of + -1 XdB, + -2 XdB, + -4 XdB, + -8 XdB, + -16 XdB and + -32 XdB, respectively. The method comprises the steps that each stage of variable gain amplifier for realizing the attenuator is 6 bits, corresponding control bits are VC 1-VC 6 respectively, 12 bits of control bits are cascaded in two stages, the control bits of the second stage of active numerical control variable gain amplifier are 6 bits, the 6 bits of control bits are combined in pairs to form 3 bits of control bits, gain change proportion of 3:12:48 is correspondingly realized, the 12 bits of attenuator control bits are reduced to 9 bits, and the corresponding gain proportions are respectively: 1:2:3:4:8:12:16:32:48.
The circuit of the single 6-bit variable gain amplifier is formed by parallel connection of 6-bit Gilbert units, wherein the single Gilbert units are connected in the following way: the switch for controlling the bias of the MOS tube M1 and the MOS tube M2 is arranged at the grid electrode of the switch, the drain electrode of the MOS tube M1 is connected with the source electrodes of the MOS tube M3 and the MOS tube M4, the drain electrode of the MOS tube M2 is connected with the source electrodes of the MOS tube M5 and the MOS tube M6, the source electrodes of the MOS tube M1 and the MOS tube M2 are grounded, the grid electrodes of the MOS tube M3 and the MOS tube M4 respectively input radio frequency differential signals RF 1-and RF1-, the drain electrode of the MOS tube M3 and the drain electrode of the MOS tube M5 are connected with each other to output RFOUT1+, and the drain electrode of the MOS tube M4 and the drain electrode of the MOS tube M6 are connected with each other to output RFOUT1-.
As shown in fig. 3a and 3b, the schematic circuit diagrams of the active digital control phase shifter based on the CMOS process and the two orthogonal variable gain amplifiers and adders are respectively designed in the invention, and the function of 9-bit digital control attenuation is realized through the active digital control phase shifter. The structure connection implementation mode of the active numerical control phase shifter is as follows: the RF+ and RF-pair of radio frequency differential input signals are input into a quadrature signal generator, the quadrature signal generator outputs two orthogonal differential signals I and Q paths, the signals respectively pass through a VGA variable gain amplifier, and then one differential signal is synthesized through an adder.
The implementation mode of the orthogonal two-path VGA variable gain amplifier and the adder is as follows: MOS tubes M1-M7 and M8-M14 are respectively connected into Gilbert units and used as VGA variable gain amplifiers of I-path and Q-path, and then Iout+ and Iout-of each Gilbert unit are respectively short-circuited to realize that two paths of orthogonal signals are added and combined to realize single-path output and expected phase output; the VI and the VQ are used for respectively controlling the bias VB1 and VB3 switches of the M2, the M3, the M9 and the M10, the M4 to the M7 and the M11 to the M14 are used for completing signal radio frequency amplification, in addition, the tail current sources M1 and M8 are respectively biased through a 7-bit numerical control DAC current mirror, and each signal gain adjustment is realized by controlling the bias voltage.
The 7-bit digital control DAC current mirror bias circuit comprises 7- bit 1X,2X,4X,8X,16X,32X and 64X current bias circuits, which are respectively controlled by paired switch control signals: v1 and
Figure SMS_18
v2 and->
Figure SMS_19
V3 and->
Figure SMS_20
V4 and->
Figure SMS_21
V5 and->
Figure SMS_22
V6 and->
Figure SMS_23
V7 and->
Figure SMS_24
The magnitudes of the currents flowing through M15, M17 and M16 and M18 are controlled, M17 providing VB1, M15 providing VB2, M18 providing VB3, and M16 providing VB4.
The connection mode of the active numerical control phase shifter is as follows: the gates of M1 and M8 are voltage biases VB2 and VB4, respectively, and the sources thereof are grounded. M1 drain electrode is connected with the source electrodes of M2 and M3, M8 drain electrode is connected with the source electrodes of M9 and M10, and the grid electrodes of M2 and M3 pass through the control switches VI and
Figure SMS_27
the gates connected to voltage biases VB1, M9 and M10 are controlled by switches VQ and +.>
Figure SMS_30
Connected to voltage bias VB3, the drains of M2 are connected to the sources of M4 and M5, the drain of M3 is connected to the sources of M6 and M7, the drain of M9 is connected to the sources of M11 and M12, the drain of M10 is connected to the sources of M13 and M14, the gates of M4 and M7 are RFI+ signals, the gates of M5 and M6 are RFI-signals, and the gates of M11 and M14 are RFQ+ signalsThe gates of M12 and M13 are RFQ-signals, and the drains of M4, M6, M11 and M13 are connected to Iout+, and the drains of M5, M7, M12 and M14 are connected to Iout-. M15 and M16 are grounded, the gate and drain are respectively shorted to voltage biases VB2 and VB4, then respectively connected to the sources of M17 and M18, the gate and drain of M17 and M18 are respectively shorted to voltage biases VB1 and VB3, then respectively connected to V1-V7 and->
Figure SMS_33
Controlled switches, V1 and->
Figure SMS_26
V2 and->
Figure SMS_28
V3 and->
Figure SMS_32
V4 and->
Figure SMS_34
V5 and->
Figure SMS_25
V6 and->
Figure SMS_29
V7 and->
Figure SMS_31
The controlled switching tubes short-circuit current sources connected to 1x,2x,4x,8x,16x,32x,64x, respectively.
In summary, in the attenuation phase shift system with adjustable amplitude and phase precision in the above embodiment, under the background that the external system requires 6-bit attenuation 6-bit phase shift, the number of direct attenuation bits and the number of phase shift bits are respectively increased to 9 bits, so that further improvement of the amplitude and phase precision becomes possible; in addition, based on the architecture, under the conditions that the system complexity and the time allowed for writing data into a power-on table lookup code value register are allowed, the 9-bit direct control bit can be further increased; along with the increase of the direct control bits, the corresponding attenuation and phase shift bits are respectively increased from the original 64 bits to 512 bits, and each attenuation state and phase shift state can be selected from a plurality of states under the condition that the external 6-bit control bits are unchanged; for the index requirements of different attenuation phase shift precision of the system, different code values can be written into a table-lookup code value register to realize on-chip adjustment and optimization of the amplitude-phase multifunctional chip.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims (7)

1. An attenuated phase-shift system with adjustable amplitude and phase accuracy, comprising: an active digital control attenuator, an active digital control phase shifter and a table-look-up code value register; the active numerical control attenuator and the active numerical control phase shifter are controlled by at least 9-bit control bits, the table-look-up code value register comprises a first latch, a second-stage latch, a buffer, an addressing device and 128 9-bit 2-system registers, serial signals are converted into serial-parallel code values through the first latch, signal latching is completed through controlling the second-stage latch, writing operation of the table-look-up code value register is completed, 6-bit attenuation address bits and 6-bit phase shift address bits are respectively connected to the 128 9-bit 2-system registers through the addressing device, an output control signal of the addressing device is respectively connected to the 128 9-bit attenuation and phase shift control code output, the output signal is finally output through the buffer, 64 9-bit binary attenuation codes and 64 9-bit binary phase shift codes are respectively addressed, the 9-bit attenuation codes and 9-bit phase shift codes are respectively output to the active numerical control attenuator and the active numerical control phase shifter, attenuation and phase shift are controlled, and the required 6-bit attenuation and 6-bit phase shift precision adjustment of the phased array system are respectively realized.
2. An attenuated phase-shift system with adjustable amplitude and phase accuracy as claimed in claim 1, wherein: the control bits of the active numerical control attenuator and the active numerical control phase shifter are 9 bits.
3. An attenuated phase-shift system with adjustable amplitude and phase accuracy as claimed in claim 2, wherein: the active digital control attenuator is an active digital control variable gain amplifier, the active digital control variable gain amplifier comprises two stages of variable gain amplifiers, and the active digital control variable gain amplifier completes attenuator amplitude modulation through the two stages of variable gain amplifiers.
4. An attenuated phase-shift system with adjustable amplitude and phase accuracy as claimed in claim 3, wherein: the active numerical control variable gain amplifier is characterized in that each stage of variable gain amplifier is 6 bits, corresponding control bits are VC 1-VC 6 respectively, the two stages of variable gain amplifiers are cascaded with 12 total control bits, the 12 attenuator control bits are reduced to 9 bits, and the corresponding gain ratios are respectively: when the unit gain is converted to 1XdB, the variable gain amplifier can respectively realize the changes of +/-1 XdB, +/-2 XdB, +/-4 XdB, +/-8 XdB, +/-16 XdB and +/-32 XdB by controlling the on and off of the bias of each tail current source.
5. An adjustable amplitude and phase precision attenuated phase shift system as claimed in claim 4, wherein: the variable gain amplifier includes 6 proportional first Gilbert cells, the 6 proportional first Gilbert cells being connected in parallel to provide gain ratios of 1:2:4:8:16:32, respectively.
6. An adjustable amplitude and phase precision attenuated phase shift system as claimed in claim 5, wherein: the active digital control phase shifter comprises a quadrature signal generator, two VGA variable gain amplifiers and an adder, wherein a pair of radio frequency differential input signals are input into the quadrature signal generator, the quadrature signal generator outputs two orthogonal differential signals I and Q paths, the signals I and Q paths respectively pass through one VGA variable gain amplifier, and one differential signal is synthesized through the adder.
7. An adjustable amplitude and phase precision attenuated phase shift system as claimed in claim 4, wherein: the active digital controlled variable gain amplifier comprises a phase synthesis circuit and a phase synthesis circuitA DAC bias circuit; the phase synthesis circuit comprises MOS transistors M1-M14, wherein the grids of the MOS transistors M1 and M8 are voltage bias ends VB2 and VB4 respectively, and the source electrode is grounded; the drain electrode of the MOS tube M1 is connected with the source electrodes of the MOS tubes M2 and M3, the drain electrode of the MOS tube M8 is connected with the source electrodes of the MOS tubes M9 and M10, and the grid electrodes of the MOS tubes M2 and M3 are connected with the source electrodes of the MOS tubes through the control switches VI and M3
Figure QLYQS_9
The gates of the MOS transistors M9 and M10 are connected to the voltage bias terminal VB1 through control switches VQ and +.>
Figure QLYQS_6
The MOS transistor is connected to a voltage bias end VB3, the drain electrodes of the MOS transistors M2 are connected to the source electrodes of the M4 and M5, the drain electrodes of the MOS transistors M3 are connected to the source electrodes of the MOS transistors M6 and M7, the drain electrode of the MOS transistor M9 is connected to the source electrodes of the MOS transistors M11 and M12, the drain electrode of the MOS transistor M10 is connected to the source electrodes of the MOS transistors M13 and M14, the grid electrodes of the MOS transistors M4 and M7 are connected with RFI+ signals, the grid electrodes of the MOS transistors M5 and M6 are connected with RFI-signals, the grid electrodes of the MOS transistors M11 and M14 are connected with RFQ+ signals, the drain electrodes of the MOS transistors M12 and M13 are connected with RFQ-signals, the drain electrodes of the MOS transistors M4, M6, M11 and M13 are connected with an Iout+ end, and the drain electrodes of the MOS transistors M5, M7 and M12 and M14 are connected with an Iout-end; the DAC bias circuit comprises 7-bit 1X,2X,4X,8X,16X,32X and 64X current bias circuits and MOS tubes M15-M18, wherein the 7-bit current bias circuits respectively pass through paired switch control signals V1 and +.>
Figure QLYQS_17
V2 and->
Figure QLYQS_5
V3 and->
Figure QLYQS_10
V4 and->
Figure QLYQS_4
V5 and->
Figure QLYQS_12
V6 and->
Figure QLYQS_7
V7 and->
Figure QLYQS_13
Controlling the current flowing through M15, M17, M16 and M18, wherein the source electrodes of the MOS tubes M15 and M16 are grounded, the grid electrodes and the drain electrodes are respectively short-circuited and then respectively connected to voltage bias ends VB2 and VB4, the source electrodes of the MOS tubes M17 and M18 are respectively short-circuited, the grid electrodes and the drain electrodes of the MOS tubes M17 and M18 are respectively short-circuited and respectively connected to voltage bias ends VB1 and VB3, and then respectively connected to V1-V7 and V #>
Figure QLYQS_2
Controlled switches, V1 and->
Figure QLYQS_11
V2 and->
Figure QLYQS_1
V3 and->
Figure QLYQS_15
V4 and
Figure QLYQS_8
v5 and->
Figure QLYQS_16
V6 and->
Figure QLYQS_3
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