CN104375413A - Time synchronization system and method based on GPS/BD dual-mode time service - Google Patents

Abstract

The invention provides a time synchronization system and method based on GPS/BD dual-mode time service. The system comprises a GPS/BD dual-mode receiver with an antenna. The pulse per second G1pps output end and the pulse per second B1pps output end of the GPS/BD dual-mode receiver with the antenna are connected with a moment sequence extraction and confirmation module. The output end of a rubidium atomic clock is connected with the input end of an AND gate. The output end of the AND gate is connected with an IO pin of a complex programmable logic device CPLD. Pulses per second R1pps output by the complex programmable logic device (CPLD) are connected with the moment sequence extraction and confirmation module. The input end of the rubidium atomic clock is connected with the output end of a computer. The output end of the CPLD is connected with the input end of the computer. The invention further provides a time synchronization method for the system. Three ways of pulses per second can be measured at the same time through one GP2 chip, and the system has the advantages of being simple in structure, low in cost, high in time synchronization precision and the like.

Description

A kind of clock synchronization system based on the time service of GPS/BD bimodulus and method

Technical field

The present invention relates to Time synchronization technique field, be specifically related to a kind of clock synchronization system based on the time service of GPS/BD bimodulus and method.

Background technology

Time is physical basic parameter, and be also the citation form that material exists, the measurement of time, the transmission of temporal information and application are vital for our life, the development of national economy, particularly national defense construction.And time synchronized is exactly make the time of various places have identical time measurement value at synchronization.Along with social productive forces and scientific and technical develop rapidly, the application of time synchronized is also more and more extensive, and some specific areas require also more and more higher to the timing tracking accuracy of time dissemination system.As in the navigation of rocket launching, Satellite Tracking, Ocean Surveying, geodetic surveying, aircraft and boats and ships, scientific and technical research, the field such as earthquake prediction and national defense construction, require that time service precision is up to microsecond even tens nanoseconds.

In clock synchronization system, widely use GP2 chip at present as time interval measurement chip, but GP2 there are clear and definite service regeulations in the process used: start signal must arrive prior to stop1, stop2 signal.Such time interval could measured between start signal and stop1, stop2 signal.In GPS/BD bimodulus clock synchronization system, GPS1pps, BD1pps, these three pulse per second (PPS)s of R1pps which first to arrive be uncertain, this just makes the time interval measurement module based on GP2 be difficult to be applicable in GPS/BD bimodulus clock synchronization system, if use 2 GP2 chips, can cost be increased, and the software and hardware structure of system also can become very complicated.

The achievement based on the Big Dipper/GPS dual-mode Service of Timing research published at present mainly comprises: Hunan University Guo Bin shows " the electric system Time synchronization technique research based on the Big Dipper/GPS dual-mode time service " master's degree opinion, the design of many reference time sources " in the timing system " that the people such as National University of Defense technology Huang Fei deliver on war industry's journal the 29th volume 11 phase in 2008.All solution is not proposed to above-mentioned technical matters in above-mentioned achievement in research.

Summary of the invention

In order to solve above-mentioned prior art Problems existing, the object of the present invention is to provide a kind of clock synchronization system based on the time service of GPS/BD bimodulus and method, by a slice GP2 chip, measure three tunnel pulse per second (PPS)s simultaneously, there is structure simple, with low cost, timing tracking accuracy advantages of higher.

For reaching above object, the present invention adopts following technical scheme:

A kind of clock synchronization system based on the time service of GPS/BD bimodulus, comprise the GPS/BD dual mode receiver 1 with antenna, pulse per second (PPS) G1pps output terminal and pulse per second (PPS) B1pps output terminal and the moment order of the described GPS/BD dual mode receiver 1 with antenna are extracted and are connected with confirmation module 2, the output terminal of rubidium atomic clock 4 and being connected with the input end of door 5, be connected with the IO pin of complex programmable logic device (CPLD) 6 with the output terminal of door 5, pulse per second (PPS) R1pps output terminal and the moment order of complex programmable logic device (CPLD) 6 are extracted and are connected with confirmation module 2, the input end of described rubidium atomic clock 4 is connected with the output terminal of computing machine 7, the output terminal of described complex programmable logic device (CPLD) 6 is connected with the input end of computing machine 7,

Described moment order is extracted and is confirmed that module 2 comprises moment order extraction module 9 and moment order confirms module 10, the pulse per second (PPS) R1pps output terminal of described complex programmable logic device (CPLD) 6 is all connected with the input end of moment order extraction module 9 with pulse per second (PPS) B1pps output terminal with the pulse per second (PPS) G1pps output terminal of the GPS/BD dual mode receiver 1 with antenna, the pulse F1pps that arrives at first of moment order extraction module 9 is directly connected with the start pin based on GP2 time interval measurement module 3, pulse M1pps is arrived with the last pulse L1pps that arrives by being connected with stop1 with the stop2 pin based on GP2 time interval measurement module 3 respectively after the time delay of two 30ns lag lines 8 in the middle of moment order extraction module 9, the described output terminal based on GP2 time interval measurement module 3 is connected with the input end of computing machine 7, described moment order confirm module 10 by pulse per second (PPS) R1pps, G1pps and B1pps with arrives pulse F1pps at first, centre arrives pulse M1pps and finally arrive pulse L1pps and be mapped,

The inner connecting structure of described moment order extraction module 9 is: pulse per second (PPS) R1pps, G1pps with B1pps is connected with the input end of door 11 with first simultaneously, first exports the pulse L1pps for finally arriving with door 11, pulse per second (PPS) R1pps, G1pps with B1pps is connected with the input end of first or door 14 simultaneously, first or door 14 export as arriving pulse F1pps at first, pulse per second (PPS) G1pps with B1pps is connected with the input end of XOR gate 16 simultaneously, the output signal of XOR gate 16 is connected with the input end of door 12 with second with pulse per second (PPS) R1pps more simultaneously, pulse per second (PPS) G1pps with B1pps is connected with the input end of door 13 with the 3rd simultaneously, second is connected with the input end of second or door 15 with the output terminal of door 13 with the 3rd with the output terminal of door 12 simultaneously, second or door 15 export and arrive pulse M1pps for middle,

Described moment order confirms that the inner connecting structure of module 10 is: pulse per second (PPS) R1pps is connected with the trigger pin of the first D-latch 17 with the second latch 18 respectively, pulse per second (PPS) G1pps is connected with the trigger pin of 4 d latch 20 with the 3rd D-latch 19 respectively, pulse per second (PPS) B1pps is connected with the trigger pin of the 5th D-latch 21 with the 6th D-latch 22 respectively, pulse per second (PPS) G1pps is connected with the input pin of the first D-latch 17 with the 5th D-latch 21 respectively, pulse per second (PPS) R1pps is connected with the input pin of the 3rd D-latch 19 with the 6th D-latch 22 respectively, pulse per second (PPS) B1pps is connected with the input pin of 4 d latch 20 with the second D-latch 19 respectively, first D-latch 17, second latch 18, the 3rd D-latch 19,4 d latch 20, the 5th D-latch 21 IO pin different from complex programmable logic device (CPLD) 6 respectively with the output terminal of the 6th D-latch 22 is connected.

The method for synchronizing time of the clock synchronization system based on the time service of GPS/BD bimodulus described above, the sine wave signal that described rubidium atomic clock 4 sends obtains the identical square-wave signal of frequency after processing with door 5, by this square-wave signal by exporting pulse per second (PPS) R1pps after complex programmable logic device (CPLD) 6 frequency division, GPS/BD dual mode receiver 1 simultaneously with antenna exports pulse per second (PPS) G1pps and B1pps, as the reference time regulating the rubidium clock time, pulse per second (PPS) R1pps and pulse per second (PPS) G1pps and B1pps is accessed simultaneously moment order extract and confirm module 2, extracted by moment order and confirm that three tunnel pulse per second (PPS)s are successively sorted as to arrive pulse F1pps at first by time of arrival by the moment order extraction module 9 of module 2, the middle pulse M1pps that arrives arrives pulse L1pps with last, extracted by moment order and confirm that the moment order of module 2 confirms which pulse per second (PPS) the pulse that module 10 confirms to arrive at first is, which pulse per second (PPS) the middle pulse arrived is, which pulse per second (PPS) the pulse finally arrived is, moment order extraction module 9 exports and arrives pulse F1pps at first to the start pin based on GP2 time interval measurement module 3, in the middle of moment order extraction module 9 output, arrival pulse M1pps and last arrival pulse L1pps arrives stop1 and the stop2 pin based on GP2 time interval measurement module 3 respectively after two 30ns lag lines 8 postpone, moment order confirms that the moment sequence of module 10 output is by being extracted by computing machine 7 after complex programmable logic device (CPLD) 6, for follow-up frequency control, three pulse per second (PPS) R1pps are measured based on GP2 time interval measurement module 3, mistiming between G1pps and B1pps, computing machine 7 reads three pulse per second (PPS) R1pps from based on GP2 time interval measurement module 3, mistiming between G1pps and B1pps, mistiming of reading is utilized to estimate atomic clock relative to the drift velocity of reference time and mistiming, computing machine obtains atomic clock relative to the drift velocity of reference time with after the mistiming, the control algolithm of recycling classics calculates the controlled quentity controlled variable to atomic frequency, by serial ports, the controlled quentity controlled variable calculating gained is sent to rubidium atomic clock 4, feedback regulation is carried out to rubidium atomic clock 4, make it to be consistent with time reference, to realize accurately regulating in real time rubidium clock.

Described moment order is extracted and is confirmed that the moment order of module 2 confirms which pulse per second (PPS) the pulse that module 10 confirms to arrive at first is, which pulse per second (PPS) the middle pulse arrived is, the pulse finally arrived is the concrete grammar of which pulse per second (PPS): when pulse per second (PPS) R1pps rising edge arrives, the state latch of pulse per second (PPS) G1pps and pulse per second (PPS) B1pps exports by the first D-latch 17 and the second latch 18 respectively, complex programmable logic device (CPLD) 6 can be known by the state of inquiry IO pin, relative to pulse per second (PPS) R1pps, the time sequencing that G1pps and B1pps arrives, when pulse per second (PPS) G1pps arrives, the state latch of pulse per second (PPS) R1pps and pulse per second (PPS) B1pps exports by the 3rd D-latch 19 and 4 d latch 20 respectively, complex programmable logic device (CPLD) 6 can be known by the state of inquiry IO pin, relative to order time of arrival of pulse per second (PPS) G1pps, R1pps and G1pps, when pulse per second (PPS) B1pps arrives, 5th D-latch 21 and the 6th D-latch 22 are by the state latch of pulse per second (PPS) R1pps and pulse per second (PPS) G1pps and export, complex programmable logic device (CPLD) 6 can be known by the state of inquiry IO pin, relative to order time of arrival of pulse per second (PPS) B1pps, R1pps and G1pps, last question blank 1 just can confirm, order time of arrival of three tunnel pulses:

Table 1. moment confirms block truth table

Num	A0	A1	A2	A3	A4	A5	Pulse order of arrival
								0	1	1	0	0	1	0	G1pps、B1pps、R1pps
1	1	1	0	1	0	0	B1pps、G1pps、R1pps
								2	1	0	0	0	1	1	G1pps、R1pps、B1pps
3	0	1	1	1	0	0	B1pps、R1pps、G1pps
								4	0	0	1	1	0	1	R1pps、B1pps、G1pps
5	0	0	1	0	1	1	R1pps、G1pps、B1pps
								6	X	X	X	X	X	X	Disarmed state

Described computing machine 7 utilizes the mistiming read to estimate atomic clock relative to the drift velocity of reference time and mistiming, and the concrete formula estimated is as follows:

ΔT＝(ΔT _G+ΔT _B)/2

${\mathrm{\ΔT}}^{\·}=K_G{{\mathrm{\ΔT}}^{\·}}_G+K_B{{\mathrm{\ΔT}}^{\·}}_B$

Wherein: Δ T is the mistiming of pulse per second (PPS) R1pps relative to reference time of atomic clock, Δ T ^.the drift velocity of pulse per second (PPS) R1pps relative to reference time of atomic clock, Δ T _gthe mistiming of pulse per second (PPS) R1pps relative to GPS pulse per second (PPS) G1pps of atomic clock, Δ T _bthe mistiming of pulse per second (PPS) R1pps relative to BD pulse per second (PPS) B1pps of atomic clock, Δ T ^. _gbe the pulse per second (PPS) R1pps of atomic clock relative to GPS pulse per second (PPS) G1pps drift velocity, Δ T ^. _bbe the pulse per second (PPS) R1pps of atomic clock relative to BD pulse per second (PPS) B1pps drift velocity, Δ T _g, Δ T _b, Δ T ^. _g, Δ T ^. _bobtained by least square method;

K _gintegration percentage coefficient, k _bit is integration percentage coefficient the variance of GPS pulse per second (PPS) G1pps relative to R1pps pps pulse per second signal, the variance of BD pulse per second (PPS) relative to R1pps pps pulse per second signal.

Compared to the prior art, advantage of the present invention is as follows:

The present invention can realize utilizing a slice GP2 to measure time interval between three tunnel pulse per second (PPS)s simultaneously, moment wherein extracts and confirms that module can realize in CPLD inside programming, compared with traditional bimodulus time dissemination system, technical scheme that the present invention carries, enormously simplify the complexity of hardware system, reduce production cost, improve the reliability of system.

Secondly, the present invention proposes the clock bias estimation method based on data fusion, the measurement data of the method GPS pulse per second (PPS) and BD pulse per second (PPS) by making full use of, achieves high precision clock bias estimation.Experiment shows, method of the present invention is compared with traditional method, and pulse per second (PPS) estimated accuracy improves 20%.

Accompanying drawing explanation

Fig. 1 is the clock synchronization system structural representation of GPS/BD bimodulus of the present invention time service.

Fig. 2 is moment order extraction module and GP2 connection layout.

Fig. 3 is that moment order extracts cut-away view.

Fig. 4 moment confirm inner structure and with CPLD connection layout.

Embodiment

Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.

As depicted in figs. 1 and 2, a kind of clock synchronization system based on the time service of GPS/BD bimodulus of the present invention, comprise the GPS/BD dual mode receiver 1 with antenna, pulse per second (PPS) G1pps output terminal and pulse per second (PPS) B1pps output terminal and the moment order of the described GPS/BD dual mode receiver 1 with antenna are extracted and are connected with confirmation module 2, the output terminal of rubidium atomic clock 4 and being connected with the input end of door 5, be connected with the IO pin of complex programmable logic device (CPLD) 6 with the output terminal of door 5, pulse per second (PPS) R1pps output terminal and the moment order of complex programmable logic device (CPLD) 6 are extracted and are connected with confirmation module 2, the input end of described rubidium atomic clock 4 is connected with the output terminal of computing machine 7, the output terminal of described complex programmable logic device (CPLD) 6 is connected with the input end of computing machine 7, described moment order is extracted and is confirmed that module 2 comprises moment order extraction module 9 and moment order confirms module 10, the pulse per second (PPS) R1pps output terminal of described complex programmable logic device (CPLD) 6 is all connected with the input end of moment order extraction module 9 with pulse per second (PPS) B1pps output terminal with the pulse per second (PPS) G1pps output terminal of the GPS/BD dual mode receiver 1 with antenna, the pulse F1pps that arrives at first of moment order extraction module 9 is directly connected with the start pin based on GP2 time interval measurement module 3, pulse M1pps is arrived with the last pulse L1pps that arrives by being connected with stop1 with the stop2 pin based on GP2 time interval measurement module 3 respectively after the time delay of two 30ns lag lines 8 in the middle of moment order extraction module 9, the described output terminal based on GP2 time interval measurement module 3 is connected with the input end of computing machine 7, described moment order confirm module 10 by pulse per second (PPS) R1pps, G1pps and B1pps with arrives pulse F1pps at first, centre arrives pulse M1pps and finally arrive pulse L1pps and be mapped.

As shown in Figure 3, the inner connecting structure of described moment order extraction module 9 is: pulse per second (PPS) R1pps, G1pps with B1pps is connected with the input end of door 11 with first simultaneously, first exports the pulse L1pps for finally arriving with door 11, pulse per second (PPS) R1pps, G1pps with B1pps is connected with the input end of first or door 14 simultaneously, first or door 14 export as arriving pulse F1pps at first, pulse per second (PPS) G1pps with B1pps is connected with the input end of XOR gate 16 simultaneously, the output signal of XOR gate 16 is connected with the input end of door 12 with second with pulse per second (PPS) R1pps more simultaneously, pulse per second (PPS) G1pps with B1pps is connected with the input end of door 13 with the 3rd simultaneously, second is connected with the input end of second or door 15 with the output terminal of door 13 with the 3rd with the output terminal of door 12 simultaneously, second or door 15 export and arrive pulse M1pps for middle.

As shown in Figure 4, described moment order confirms that the inner connecting structure of module 10 is: pulse per second (PPS) R1pps is connected with the trigger pin of the first D-latch 17 with the second latch 18 respectively, pulse per second (PPS) G1pps is connected with the trigger pin of 4 d latch 20 with the 3rd D-latch 19 respectively, pulse per second (PPS) B1pps is connected with the trigger pin of the 5th D-latch 21 with the 6th D-latch 22 respectively, pulse per second (PPS) G1pps is connected with the input pin of the first D-latch 17 with the 5th D-latch 21 respectively, pulse per second (PPS) R1pps is connected with the input pin of the 3rd D-latch 19 with the 6th D-latch 22 respectively, pulse per second (PPS) B1pps is connected with the input pin of 4 d latch 20 with the second D-latch 19 respectively, first D-latch 17, second latch 18, the 3rd D-latch 19,4 d latch 20, the 5th D-latch 21 IO pin different from complex programmable logic device (CPLD) 6 respectively with the output terminal of the 6th D-latch 22 is connected.

As shown in Figure 1, the method for synchronizing time of the clock synchronization system based on the time service of GPS/BD bimodulus of the present invention, the sine wave signal that described rubidium atomic clock 4 sends obtains the identical square-wave signal of frequency after processing with door 5, by this square-wave signal by exporting pulse per second (PPS) R1pps after complex programmable logic device (CPLD) 6 frequency division, GPS/BD dual mode receiver 1 simultaneously with antenna exports pulse per second (PPS) G1pps and B1pps, as the reference time regulating the rubidium clock time, pulse per second (PPS) R1pps and pulse per second (PPS) G1pps and B1pps is accessed simultaneously moment order extract and confirm module 2, extracted by moment order and confirm that three tunnel pulse per second (PPS)s are successively sorted as to arrive pulse F1pps at first by time of arrival by the moment order extraction module 9 of module 2, the middle pulse M1pps that arrives arrives pulse L1pps with last, extracted by moment order and confirm that the moment order of module 2 confirms which pulse per second (PPS) the pulse that module 10 confirms to arrive at first is, which pulse per second (PPS) the middle pulse arrived is, which pulse per second (PPS) the pulse finally arrived is, moment order extraction module 9 exports and arrives pulse F1pps at first to the start pin based on GP2 time interval measurement module 3, in the middle of moment order extraction module 9 output, arrival pulse M1pps and last arrival pulse L1pps arrives stop1 and the stop2 pin based on GP2 time interval measurement module 3 respectively after two 30ns lag lines 8 postpone, moment order confirms that the moment sequence of module 10 output is by being extracted by computing machine 7 after complex programmable logic device (CPLD) 6, for follow-up frequency control, the mistiming between three pulse per second (PPS)s R1pps, G1pps and B1pps is measured based on GP2 time interval measurement module 3, computing machine 7 is from the mistiming of reading based on GP2 time interval measurement module 3 between three pulse per second (PPS)s R1pps, G1pps and B1pps, utilize mistiming of reading to estimate atomic clock relative to the drift velocity of reference time and mistiming, the concrete formula estimated is as follows:

ΔT＝(ΔT _G+ΔT _B)/2

${\mathrm{\ΔT}}^{\·}=K_G{{\mathrm{\ΔT}}^{\·}}_G+K_B{{\mathrm{\ΔT}}^{\·}}_B$

Wherein: Δ T is the mistiming of pulse per second (PPS) R1pps relative to reference time of atomic clock, Δ T ^.the drift velocity of pulse per second (PPS) R1pps relative to reference time of atomic clock, Δ T _gthe mistiming of pulse per second (PPS) R1pps relative to GPS pulse per second (PPS) G1pps of atomic clock, Δ T _bthe mistiming of pulse per second (PPS) R1pps relative to BD pulse per second (PPS) B1pps of atomic clock, Δ T ^. _gbe the pulse per second (PPS) R1pps of atomic clock relative to GPS pulse per second (PPS) G1pps drift velocity, Δ T ^. _bthat the pulse per second (PPS) R1pps of atomic clock is relative to BD pulse per second (PPS) B1pps drift velocity. Δ T _g, Δ T _b, Δ T ^. _g, Δ T ^. _bcan be obtained by least square method.

K _gintegration percentage coefficient, k _bit is integration percentage coefficient

the variance of GPS pulse per second (PPS) G1pps relative to R1pps pps pulse per second signal, the variance of BD pulse per second (PPS) relative to R1pps pps pulse per second signal.

After obtaining clock correction and clock correction drift velocity, PID (the being not limited to PID) control algolithm of recycling classics calculates the controlled quentity controlled variable to atomic frequency, by serial ports, the controlled quentity controlled variable calculating gained is sent to rubidium atomic clock 4, feedback regulation is carried out to rubidium atomic clock 4, make it to be consistent with time reference, to realize accurately regulating in real time rubidium clock.

As shown in Figure 4, described moment order is extracted and is confirmed that the moment order of module 2 confirms which pulse per second (PPS) the pulse that module 10 confirms to arrive at first is, which pulse per second (PPS) the middle pulse arrived is, the pulse finally arrived is the concrete grammar of which pulse per second (PPS): when pulse per second (PPS) R1pps rising edge arrives, the state latch of pulse per second (PPS) G1pps and pulse per second (PPS) B1pps exports by the first D-latch 17 and the second latch 18 respectively, complex programmable logic device (CPLD) 6 can be known by the state of inquiry IO pin, relative to pulse per second (PPS) R1pps, the time sequencing that G1pps and B1pps arrives, when pulse per second (PPS) G1pps arrives, the state latch of pulse per second (PPS) R1pps and pulse per second (PPS) B1pps exports by the 3rd D-latch 19 and 4 d latch 20 respectively, complex programmable logic device (CPLD) 6 can be known by the state of inquiry IO pin, relative to order time of arrival of pulse per second (PPS) G1pps, R1pps and G1pps, when pulse per second (PPS) B1pps arrives, 5th D-latch 21 and the 6th D-latch 22 are by the state latch of pulse per second (PPS) R1pps and pulse per second (PPS) G1pps and export, complex programmable logic device (CPLD) 6 can be known by the state of inquiry IO pin, relative to order time of arrival of pulse per second (PPS) B1pps, R1pps and G1pps, last question blank 1 just can confirm, order time of arrival of three tunnel pulses.

Claims (4)

1. the clock synchronization system based on the time service of GPS/BD bimodulus, it is characterized in that: comprise the GPS/BD dual mode receiver (1) with antenna, pulse per second (PPS) G1pps output terminal and pulse per second (PPS) B1pps output terminal and the moment order of the described GPS/BD dual mode receiver (1) with antenna are extracted and are connected with confirmation module (2), the output terminal of rubidium atomic clock (4) and being connected with the input end of door (5), be connected with the IO pin of complex programmable logic device (CPLD) (6) with the output terminal of door (5), pulse per second (PPS) R1pps output terminal and the moment order of complex programmable logic device (CPLD) (6) are extracted and are connected with confirmation module (2), the input end of described rubidium atomic clock (4) is connected with the output terminal of computing machine (7), the output terminal of described complex programmable logic device (CPLD) (6) is connected with the input end of computing machine (7),

Described moment order is extracted and is confirmed that module (2) comprises moment order extraction module (9) and moment order confirms module (10), the pulse per second (PPS) R1pps output terminal of described complex programmable logic device (CPLD) (6) is all connected with the input end in moment order extraction module (9) with pulse per second (PPS) B1pps output terminal with the pulse per second (PPS) G1pps output terminal of the GPS/BD dual mode receiver (1) with antenna, the pulse of the arrival at first F1pps in moment order extraction module (9) is directly connected with the start pin based on GP2 time interval measurement module (3), pulse M1pps is arrived with the last pulse L1pps that arrives by being connected with stop1 with the stop2 pin based on GP2 time interval measurement module (3) respectively after the time delay of two 30ns lag lines (8) in the middle of moment order extraction module (9), the described output terminal based on GP2 time interval measurement module (3) is connected with the input end of computing machine (7), described moment order confirm module (10) by pulse per second (PPS) R1pps, G1pps and B1pps with arrives pulse F1pps at first, centre arrives pulse M1pps and finally arrive pulse L1pps and be mapped,

The inner connecting structure of described moment order extraction module (9) is: pulse per second (PPS) R1pps, G1pps with B1pps is connected with the input end of door (11) with first simultaneously, first exports the pulse L1pps for finally arriving with door (11), pulse per second (PPS) R1pps, G1pps with B1pps is connected with the input end of first or door (14) simultaneously, first or door (14) export as arriving pulse F1pps at first, pulse per second (PPS) G1pps with B1pps is connected with the input end of XOR gate (16) simultaneously, the output signal of XOR gate (16) is connected with the input end of door (12) with second with pulse per second (PPS) R1pps more simultaneously, pulse per second (PPS) G1pps with B1pps is connected with the input end of door (13) with the 3rd simultaneously, second is connected with the input end of second or door (15) with the output terminal of door (13) with the 3rd with the output terminal of door (12) simultaneously, second or door (15) export and arrive pulse M1pps for middle,

Described moment order confirms that the inner connecting structure of module (10) is: pulse per second (PPS) R1pps is connected with the trigger pin of the first D-latch (17) with the second latch (18) respectively, pulse per second (PPS) G1pps is connected with the trigger pin of 4 d latch (20) with the 3rd D-latch (19) respectively, pulse per second (PPS) B1pps is connected with the trigger pin of the 5th D-latch (21) with the 6th D-latch (22) respectively, pulse per second (PPS) G1pps is connected with the input pin of the first D-latch (17) with the 5th D-latch (21) respectively, pulse per second (PPS) R1pps is connected with the input pin of the 3rd D-latch (19) with the 6th D-latch (22) respectively, pulse per second (PPS) B1pps is connected with the input pin of 4 d latch (20) with the 3rd D-latch (19) respectively, first D-latch (17), the second latch (18), the 3rd D-latch (19), 4 d latch (20), the 5th D-latch (21) the IO pin different from complex programmable logic device (CPLD) (6) respectively with the output terminal of the 6th D-latch (22) is connected.

2. described in claim 1 based on the method for synchronizing time of the clock synchronization system of GPS/BD bimodulus time service, it is characterized in that: the sine wave signal that described rubidium atomic clock (4) sends obtains the identical square-wave signal of frequency after processing with door (5), this square-wave signal is exported pulse per second (PPS) R1pps by after complex programmable logic device (CPLD) (6) frequency division, GPS/BD dual mode receiver (1) simultaneously with antenna exports pulse per second (PPS) G1pps and B1pps, as the reference time regulating the rubidium clock time, pulse per second (PPS) R1pps and pulse per second (PPS) G1pps and B1pps is accessed simultaneously moment order extract and confirm module (2), extracted by moment order and confirm that three tunnel pulse per second (PPS)s are successively sorted as to arrive pulse F1pps at first by time of arrival by moment order extraction module (9) of module (2), the middle pulse M1pps that arrives arrives pulse L1pps with last, extracted by moment order and confirm that the moment order of module (2) confirms that module (10) confirms which pulse per second (PPS) the pulse arrived at first is, which pulse per second (PPS) the middle pulse arrived is, which pulse per second (PPS) the pulse finally arrived is, moment order extraction module (9) exports and arrives pulse F1pps at first to the start pin based on GP2 time interval measurement module (3), moment order extraction module (9) export in the middle of arrive pulse M1pps and the last pulse L1pps that arrives arrives stop1 and stop2 pin based on GP2 time interval measurement module (3) respectively after two 30ns lag lines (8) postpone, moment order confirms that moment sequence that module (10) exports is by being extracted by computing machine (7) after complex programmable logic device (CPLD) (6), for follow-up frequency control, three pulse per second (PPS) R1pps are measured based on GP2 time interval measurement module (3), mistiming between G1pps and B1pps, computing machine (7) reads three pulse per second (PPS) R1pps from based on GP2 time interval measurement module (3), mistiming between G1pps and B1pps, mistiming of reading is utilized to estimate atomic clock relative to the drift velocity of reference time and mistiming, computing machine (7) obtains atomic clock relative to the drift velocity of reference time with after the mistiming, the control algolithm of recycling classics calculates the controlled quentity controlled variable to atomic frequency, by serial ports, the controlled quentity controlled variable calculating gained is sent to rubidium atomic clock (4), feedback regulation is carried out to rubidium atomic clock (4), make it to be consistent with time reference, to realize accurately regulating in real time rubidium clock.

3. method for synchronizing time according to claim 2, it is characterized in that: described moment order is extracted and confirmed that the moment order of module (2) confirms that module (10) confirms which pulse per second (PPS) the pulse arrived at first is, which pulse per second (PPS) the middle pulse arrived is, the pulse finally arrived is the concrete grammar of which pulse per second (PPS): when pulse per second (PPS) R1pps rising edge arrives, the state latch of pulse per second (PPS) G1pps and pulse per second (PPS) B1pps exports by the first D-latch (17) and the second latch (18) respectively, complex programmable logic device (CPLD) (6) can be known by the state of inquiry IO pin, relative to pulse per second (PPS) R1pps, the time sequencing that G1pps and B1pps arrives, when pulse per second (PPS) G1pps arrives, the state latch of pulse per second (PPS) R1pps and pulse per second (PPS) B1pps exports by the 3rd D-latch (19) and 4 d latch (20) respectively, complex programmable logic device (CPLD) (6) can be known by the state of inquiry IO pin, relative to order time of arrival of pulse per second (PPS) G1pps, R1pps and G1pps, when pulse per second (PPS) B1pps arrives, 5th D-latch (21) and the 6th D-latch (22) are by the state latch of pulse per second (PPS) R1pps and pulse per second (PPS) G1pps and export, complex programmable logic device (CPLD) (6) can be known by the state of inquiry IO pin, relative to order time of arrival of pulse per second (PPS) B1pps, R1pps and G1pps, last question blank 1 just can confirm, order time of arrival of three tunnel pulses:

Table 1. moment confirms block truth table

Num A0 A1 A2 A3 A4 A5 Pulse order of arrival 0 1 1 0 0 1 0 G1pps、B1pps、R1pps 1 1 1 0 1 0 0 B1pps、G1pps、R1pps 2 1 0 0 0 1 1 G1pps、R1pps、B1pps 3 0 1 1 1 0 0 B1pps、R1pps、G1pps 4 0 0 1 1 0 1 R1pps、B1pps、G1pps 5 0 0 1 0 1 1 R1pps、G1pps、B1pps 6 X X X X X X Disarmed state

4. method for synchronizing time according to claim 2, is characterized in that: described computing machine (7) utilizes the mistiming read to estimate atomic clock relative to the drift velocity of reference time and mistiming, and the concrete formula estimated is as follows:

ΔT＝(ΔT _G+ΔT _B)/2

$\mathrm{\Δ}\stackrel{\·}{T}=K_G\mathrm{\Δ}{\stackrel{\·}{T}}_G+K_B\mathrm{\Δ}{\stackrel{\·}{T}}_B$

Wherein: Δ T is the mistiming of pulse per second (PPS) R1pps relative to reference time of atomic clock, the drift velocity of pulse per second (PPS) R1pps relative to reference time of atomic clock, Δ T _gthe mistiming of pulse per second (PPS) R1pps relative to GPS pulse per second (PPS) G1pps of atomic clock, Δ T _bthe mistiming of pulse per second (PPS) R1pps relative to BD pulse per second (PPS) B1pps of atomic clock, be the pulse per second (PPS) R1pps of atomic clock relative to GPS pulse per second (PPS) G1pps drift velocity, be the pulse per second (PPS) R1pps of atomic clock relative to BD pulse per second (PPS) B1pps drift velocity, Δ T _g, Δ T _b, obtained by least square method;

K _gintegration percentage coefficient, k _bit is integration percentage coefficient the variance of GPS pulse per second (PPS) G1pps relative to R1pps pps pulse per second signal, the variance of BD pulse per second (PPS) relative to R1pps pps pulse per second signal.