CN102136022A

CN102136022A - Automatic placement and routing method

Info

Publication number: CN102136022A
Application number: CN2011101027614A
Authority: CN
Inventors: 张翼; 陈曦; 程玉华
Original assignee: Shanghai Research Institute of Microelectronics of Peking University
Current assignee: Shanghai Research Institute of Microelectronics of Peking University
Priority date: 2011-04-22
Filing date: 2011-04-22
Publication date: 2011-07-27

Abstract

The invention provides an automatic placement and routing method for a testing structure for a plurality of transistor module units. The transistor module units introducing parameters form the testing structure by a plurality of transistors. In the automatic method, the tested transistors are connected with corresponding pads to finish placement and routing. By the automatic method, the complexity of realizing a transistor testing circuit and the testing structure by a novel process is greatly reduced, finishing time is shortened and reliability is improved.

Description

Robotization placement-and-routing method

Technical field

The present invention relates to the Analogous Integrated Electronic Circuits design back, especially about the automatic placement and routing of device detection structure.

Background technology

Integrated circuit (IC) design comprises Front-end Design and two stages of back end design, and Front-end Design is responsible for logic realization, typically uses the speech like sound of Verilog/VHDL, carries out the description of behavioral scaling.Back end design is meant that the gate level netlist that Front-end Design is produced carries out placement-and-routing by the EDA design tool and carries out physical verification and the final process that produces for the GDS file of making usefulness, and its main responsibility has: chip physical structure analysis, logic analysis, set up back end design flow process, laying out pattern wiring, layout editing, domain physical verification, contact wafer factory and submit production data to.So-called GDS file is a kind of patterned file, is a kind of form of integrated circuit diagram.

Along with the increase day by day of mixed-signal designs complicacy, development technology design tool bag (PDK, ProcessDesign Kit) is also set up and is verified that reference flowchart is very important for the market risk that the design that reduces costliness is brought repeatedly.In general, wafer factory can customize the design component of PDK according to the requirement of technology, and each technology all can have the corresponding PDK of a cover.

PDK is the complete process file set that provides for analog IC circuit design, is the data platform that connects IC design and the manufacturing of IC technology.The content of PDK comprises: device model (Device Model); Symbol and view (Symbols﹠amp; View); Component description form (CDF, Component DescriptionFormat) and Callback function; Parameterized units (Pcell, Parameterized Cell); Technological document (Technology File); Physical verification rule (PV Rule) file etc.

What wherein the parameter in the parameterized units (Pcell) referred to is exactly the CDF parameter, and their combination can realize all functions of customization, is the core of PDK.In fact, the storehouse of PDK just is meant the intersection of all parameterized units.

In a word, if had the PDK that optimizes set through parameterized units structure, symbol and the rule etc. of checking, IC designer's work just can free from the task of loaded down with trivial details fallibility and the high-quality and be rich in efficient of becoming.

In traditional domain cell library, only there is the MOS transistor elementary cell, the layout drawing personnel are when drawing the coupling MOS transistor, call the MOS transistor of band parameter earlier, and then according to the MOS transistor dimensional parameters of required measurement, domain unit to each MOS transistor carries out the parameter setting, then carries out placement-and-routing according to the principle of coupling.Whole process is carried out the parameter setting from adding MOS transistor to them, and the location layout in domain is linked liner to wiring, and each link is all finished by hand by the drafting personnel.If MOS transistor quantity is very huge or size changes to some extent, then the change operation is very loaded down with trivial details, but also makes a mistake in careless easily.

Summary of the invention

The invention provides a kind of robotization placement-and-routing method of a plurality of transistor modular unit testing structures, to call in the transistorized data of required measurement and to generate domain, reduce the area of domain, improve and draw the test structure efficiency of layout, improve stability of structure.

According to embodiments of the invention, a kind of robotization placement-and-routing method of a plurality of transistor modular unit testing structures is provided, include: several tested transistors and liner and the metal connecting line between them.

Optionally, the quantity of described transistor modular unit generates MOS transistor and automatically by vertical arrangement.

Optionally, the grid of described transistor modular unit length, grid width and interdigital number allow area according to actual domain, arrange by the proper spacing left-justify.

Optionally, the layout method of described test structure: liner is vertically arranged in the domain left side, and its spacing meets technology minimum dimension or tested MOS transistor width.

Optionally, the layout method of described test structure: liner becomes symmetric offset spread up and down, and the centre is the liner of corresponding grid and substrate, up and down the liner of corresponding source of symmetric offset spread and leakage.

Optionally, the wiring method of described test structure: regardless of tested MOS transistor parameter, the grid of various piece, source, leakage all merge draws, and it seems that externally a MOS transistor has only four outputs.

Optionally, the wiring method of described test structure: the liner of corresponding one group of source of tested MOS transistor and leakage, its pairing source liner is linked in this transistorized institute active area unification, and its pairing leakage liner is linked in all drain region unifications.The liner of corresponding one group of grid of all tested MOS transistor and substrate, unique grid liner is linked in the grid unification of all crystals pipe, and unique substrate pads is linked in all substrate unifications.So N source liner of N transistor correspondence, N leakage liner, 1 grid liner and 1 substrate pads.

Description of drawings

Fig. 1 is for generating MOS transistor parameterized module cellular construction synoptic diagram by parameter.

Fig. 2 is for arranging behind the liner symmetric configuration structural representation up and down.

Fig. 3 finishes synoptic diagram for the robotization placement-and-routing of a plurality of transistor modular unit testing structures.

Embodiment

Further specify the present invention below in conjunction with accompanying drawing table and specific embodiment, present embodiment only is used to explain ultimate principle, is not to be used to limit the present invention, and scope of the present invention should be as the criterion with claim institute restricted portion.Read hereinafter for the accompanying drawing table detailed description of the illustrated embodiment after, the present invention for the person of ordinary skill in the field with obviously.

As shown in table 1, embodiments of the invention contain 4 tested MOS transistor.

The tested MOS transistor quantity of table 1 parameter list

Become the parameterized module unit after the parameter importing with 4 tested MOS transistor and generate domain, as shown in Figure 1, No. 1 metal-oxide-semiconductor 101 is canonical parameter W1, L1 and 1 interdigital number (Finger); The grid width of No. 2 metal-oxide-semiconductors 102 and interdigital number are canonical parameter W1,1, and the long long L2 that is of grid; The grid length and the interdigital number of No. 3 metal-oxide-semiconductors 103 are canonical parameter L1,1, and the grid width broad is W3; The grid width of No. 4 metal-oxide-semiconductors 104 and grid are long to be canonical parameter W1, L1, and interdigital number mostly is 2.So when the described requirement of right generates domain according to the present invention 4 vertical left-justifys of MOS transistor are arranged, and because its laterally zygomorphic structure is with 101,102 are divided into one group is placed on domain the first half, 103,104 are divided into one group is placed on domain the latter half, the centre leave a blank for after will layout grid and substrate pads stay the position.

Tested MOS transistor quantity is indefinite in the practical application, may be far more than 4, and the parameter of each pipe also is not quite similar.But it is constant that the parameterized module unit generates the principle of domain: the vertical left-justify of MOS transistor is arranged, and places domain half side up and down respectively by half of quantity, leaves a blank in the centre.

Figure 2 shows that the layout structure that adds behind the liner (PAD), according to the present invention right described require liner in the domain left side vertical symmetric offset spread up and down, symcenter is pairing liner 205 of common gate (G) and the pairing liner 206 of common substrate (Sub).Generally speaking, the spacing between the substrate satisfies the technology minimum dimension, as the spacing between liner 201,202 and the liner 207,208.And at the MOS transistor grid of liner correspondence long bigger 102 or have at how interdigital several 104 o'clock, the distance that can correspondingly relax between the liner has satisfied placement-and-routing's demand, as the spacing between liner 203,204 and the liner 209,210.

Tested liner quantity is indefinite in the practical application, may be far more than 10.

(formula 1):

Liner quantity=tested MOS transistor quantity * 2+2

And the spacing between each liner also is not quite similar.But the liner principle for layout is constant: liner is positioned at the domain left side vertically to be arranged, and by middle G, the corresponding liner of Sub institute is symmetric configuration up and down.

Figure 3 shows that the MOS transistor beta version graph structure after cloth finishes line, for the tested MOS transistor 104 beyond the how interdigital number, source and leakage are by metal wire 301,302 directly link the left side liner corresponding with it, grid and substrate are by overall grid bus 303 and substrate bus 304 unified being connected on unique the grid liner and substrate pads, saved chip area like this, also convenient simultaneously wiring management.And for the MOS transistor 104 of how interdigital number, grid, source and the leakage of plural number will be passed through metal 305 earlier, 306,307 couple together, form an integral body, the described requirement of right it seems that externally a transistor has only four outputs according to the present invention, and wire laying mode equally is connected with other regular transistor then.

Robotization placement-and-routing by a plurality of transistor modular unit testing of the present invention structure, the metal-oxide-semiconductor measurement domain of new technology only need be imported parameter list as shown in table 1 and can generate automatically, reduced the area of domain, improve and draw the test structure efficiency of layout, improve stability of structure, reduce human cost, shortened test period.

Patent of the present invention not only is confined to above-mentioned embodiment, and one of ordinary skill in the art can adopt other multiple embodiments to implement the present invention according to content disclosed by the invention.Therefore, every employing project organization of the present invention and thinking are done some simple designs that change or change, and all fall into protection scope of the present invention.Feedback circuit can be very fast stable.

Claims

1. a transistor parameter modular unit is made up of several transistors, it is characterized in that, described modular unit provides the parameter of oxide-semiconductor control transistors number, revises described parameter, can adjust transistorized number, inside will be made corresponding adjustment automatically, and transistor is pressed direction arrangement longitudinally.

2. modular unit as claimed in claim 1, it is characterized in that, described modular unit provides the parameter of long (L), grid width (W) and interdigital number (Finger) of oxide-semiconductor control transistors grid, revise described parameter, can adjust transistorized size, inside will be made corresponding adjustment automatically, still keep the coupling annexation, and the left-justify mode is arranged between each transistor, and the spacing when grid length is big between the liner can change thereupon.

3. modular unit as claimed in claim 1 is characterized in that each transistor is drawn the n metal line in the described modular unit, is connected with external circuit for modular unit.Wherein metal wire comprises that substrate draws metal wire (1); Grid are drawn metal wire (quantity is this transistorized interdigital number); Metal wire (quantity is this transistorized interdigital number) is drawn in the source; Metal wire (quantity subtracts one for this transistorized interdigital number) is drawn in leakage.

4. the layout method of a test structure is characterized in that, all crystals Guan Jun laterally places grid in the modular unit as claimed in claim 1, and source and leakage branch are thereon down; Vertically arrange between the transistor, and all align, as the basic disposing way of test structure by the leftmost side of grid.

5. test structure layout method as claimed in claim 4 is characterized in that, vertical one domain structure that is listed as is adopted in putting of liner, meets the technology minimum spacing in survey transistor gate length and interdigital number than the spacing between hour liner; At the survey transistor gate long and interdigital number greatly the time or other layouts when needing pad spacings can suitably amplify.

6. test structure layout method as claimed in claim 4 is characterized in that, laterally zygomorphic domain structure is adopted in putting of liner, and symcenter is a liner and a liner of drawing as substrate of drawing as grid; Liner in the symmetrical structure drawing as source and leakage respectively up and down.

7. the wiring method of a test structure is characterized in that, is connected by metal as each transistorized source, leakage, grid and substrate unification in the layout method as described in the claim 4; For many interdigital structures, all sources are connected together, and all misses together, and all grid also are connected together, and it seems that externally a transistor has only four outputs.

8. test structure wiring method as claimed in claim 7 is characterized in that, the liner of corresponding one group of source of transistor and leakage, and its pairing source liner is linked in this transistorized institute active area unification, and its pairing leakage liner is linked in all drain region unifications.

9. test structure wiring method as claimed in claim 7 is characterized in that, the liner of corresponding one group of grid of all crystals pipe and substrate, and its pairing grid liner is linked in the grid unification of all crystals pipe, and its pairing substrate pads is linked in all substrate unifications.