CN101320707B - Integrated circuit setting and production method especially for structuration - Google Patents
Integrated circuit setting and production method especially for structuration Download PDFInfo
- Publication number
- CN101320707B CN101320707B CN200810067180XA CN200810067180A CN101320707B CN 101320707 B CN101320707 B CN 101320707B CN 200810067180X A CN200810067180X A CN 200810067180XA CN 200810067180 A CN200810067180 A CN 200810067180A CN 101320707 B CN101320707 B CN 101320707B
- Authority
- CN
- China
- Prior art keywords
- master slice
- macrocell
- setting
- production
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 26
- 230000006870 function Effects 0.000 claims description 21
- 238000013507 mapping Methods 0.000 claims description 5
- 238000012360 testing method Methods 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 abstract description 17
- 238000011161 development Methods 0.000 abstract description 5
- 238000013461 design Methods 0.000 description 22
- 101100096342 Mus musculus Spdef gene Proteins 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 239000008187 granular material Substances 0.000 description 3
- 238000003786 synthesis reaction Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000011960 computer-aided design Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 101000711466 Homo sapiens SAM pointed domain-containing Ets transcription factor Proteins 0.000 description 1
- 102100034018 SAM pointed domain-containing Ets transcription factor Human genes 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses arrangement of a structured special integrated circuit, and a manufacturing method thereof, to solve the technical problem of saving development cost and reducing development period. The method of the invention comprises the following steps of: 1, undergoing arrangement and manufacturing on a master slice, for arranging a universal function module and a cell library of a special integrated circuit, and producing universal level for the master slice; 2, arranging and producing the special chip, for arrangement of the special integrated circuit and production of residuallevel based on the master slice. Compared with current technology, the invention takes full advantage of current tool based on establishment of the cell library, and implements structured ASIC technology, with great flexibility and high utility ratio of small-grained macro cell. Any product implemented by the structured technology has a digital function part decomposed into macro cell array physically. A new product can be implemented conveniently and fast on the master slice through generation of ohm contact, a through hole and a metal layer.
Description
Technical field
The present invention relates to a kind of setting and production method of setting and production method, particularly a kind of structured application-specific integrated circuits of integrated circuit.
Background technology
After integrated circuit technology entered deep-submicron, cost, reliability problems became the bottleneck of application-specific integrated circuit ASIC (Application Specific Integrated Circuit) development.Connect up not only costliness but also have risk of the standard cell ASIC of 90nm node for example.Adopt littler process along with trend is set, comprise that the non-repeatability of mask set cost drops into NRE, and engineerings such as cloth version and checking are provided with input all in continuous increase.Therefore for the first time can realize that just correct device function is extremely important.On-site programmable gate array FPGA (FieldProgrammable Gate Array) has the characteristic of instant reprogrammable and online verification, makes it obtain the development of advancing by leaps and bounds in the past few years.Meanwhile, it is also by increasing the door number and improving device performance, the market share of constantly nibbling ASIC.Although FPGA has obtained progress in every respect, even the FPGA of most significant end does not possess density, the performance of ASIC yet, particularly medium batch and large batch of cost.The power consumption of FPGA also is a defective.Many transistors among the FPGA are used for buffering, look-up table and exchange, and are not only logic, and the static power consumption of leaking is quite big.
Summary of the invention
The setting and the production method that the purpose of this invention is to provide a kind of structured application-specific integrated circuits, the technical problem that solve are to save development cost, shortening construction cycle.
The present invention is by the following technical solutions: a kind of setting of structured application-specific integrated circuits and production method, may further comprise the steps: one, master slice setting and production are used for that general utility functions module, cell library to application-specific integrated circuit (ASIC) is provided with and the production of the general level of master slice; Two, special chip setting and production are used for application-specific integrated circuit (ASIC) is provided with and finishes the production of residue level on the master slice basis.
Master slice setting of the present invention and production may further comprise the steps: one, the small grain size macrocell is set; Two, set up cell library; Three, the array of being made up of the small grain size macrocell is set, on master slice, marks off the zone that needs scale, the horizontal vertical both direction small grain size macrocell that gathers; Four, the required general utility functions module of circuit is set; Five, physical layer pre-layout; Six, prewiring; Seven, master slice is produced in preceding road light shield and production.
Small grain size macrocell of the present invention is made up of a PMOS pipe and a NMOS pipe, and length and width are the integral multiple of grid.
Element circuit in the cell library of the present invention is to be spliced by metal connecting line by several same small grain size macrocell.
Mounting hardware resource of the present invention is a structurized module, refers to the general utility functions module that master slice provides, and comprising: input-output unit (IO), SRAM (SRAM), phase-locked loop (PLL) and intellectual property macroblock.
Physical layer pre-layout of the present invention is that physically arrangement is carried out by structure, integrated mode and combined density in the position of each type of structured unit.
Prewiring of the present invention is aspect physical structure, and the line of determining is carried out manual wiring, for connecting with metal wire inner the connection in advance of clear and definite power supply and unit.
Time production of special chip setting of the present invention and rest layers may further comprise the steps: one, the application-specific integrated circuit (ASIC) logic module is provided with; Two, use eda tool to carry out the comprehensive of application-specific integrated circuit (ASIC) and gate leve checking; Three, back wiring, the placement-and-routing that finishes physical structure; Four, special chip is produced in road light shield and production behind the chip; Five, chip testing.
Application-specific integrated circuit (ASIC) logic of the present invention setting is to whole special integrated circuit, carries out the setting and the emulation of logical circuit, the checking of function sequential.
Back of the present invention wiring may further comprise the steps: one, special chip net table and the position constraint process that is provided with according to customer requirements shone upon, and merges the practical layout wiring information of master slice, and the net table is made an amendment, and produces special chip net table and constraint; Two, placement-and-routing; Three, on master slice, exist and partially filled small grain size macrocell that special chip is not used, obtain the net table of complete circuit.
The present invention compared with prior art, setting up on the basis of cell library, make full use of existing eda tool, realized the structuring asic technology, the small grain size macrocell has very big flexibility and than high usage, with any product that this structured ASIC technology realizes, the digital function part all can resolve into macrocell GCELL array on physical level, by producing ohmic contact contact, through hole via, metal metal layer, can convenient, fast realization new product on master slice.
Description of drawings
Fig. 1-the 1st, the circuit diagram of the small grain size macrocell of the embodiment of the invention.
Fig. 1-2 is the small grain size macrocell physical structure vertical view of the embodiment of the invention.
Fig. 1-the 3rd, the small grain size macrocell physical structure sectional view of the embodiment of the invention.
Fig. 2 is that the cell library of the embodiment of the invention is provided with flow chart.
Fig. 3-the 1st, the circuit diagram of embodiment of the invention INVX1.
Fig. 3-the 2nd, the physical structure figure of embodiment of the invention INVX1.
Fig. 4-the 1st, the circuit diagram of embodiment of the invention INVX2.
Fig. 4-the 2nd, the physical structure figure of embodiment of the invention INVX2.
Fig. 5 is prior art ASIC wiring and manufacture method flow chart.
Fig. 6 is the method flow diagram of the embodiment of the invention.
Fig. 7 is the back wiring flow chart of the embodiment of the invention.
Fig. 8 is embodiment of the invention master slice figure.
Fig. 9 is embodiment of the invention special chip figure.
Figure 10 is the wire distribution distance schematic diagram.
Embodiment
Below in conjunction with drawings and Examples the present invention is described in further detail.Shown in Fig. 1-1, Fig. 1-2 and Fig. 1-3, in the method for the present invention, the setting of small grain size macrocell GCELL, on P type silicon substrate P-sub, set up N channel metal-oxide-semiconductor field NMOS, and set up P channel metal-oxide-semiconductor field PMOS in N well region N-well the inside, drain terminal D, source end S, the grid G of NMOS pipe and PMOS pipe are all unsettled, and the CELL length and width are the integral multiple of grid (is the grid of unit with minimum wiring spacing pitch).PMOS pipe, NMOS pipe are connected with other circuit parts in the external world by leakage D, source S, grid G on the circuit structure, to realize complete circuit; On the physical structure, polysilicon poly, high concentration P type ion doped region P
+District and high concentration N type ion doped region N
+The district is connected with outside other circuit parts by ohmic contact contact, through hole via, metal connecting line metal, and concrete annexation is determined by its driving force and function.
As shown in Figure 2, in the method for the present invention, some small grain size macrocell GCELL is set obtains cell library, may further comprise the steps: one, according to the logic function of standard cell needs realization and the Capability Requirement of driving load thereof, determine the number of desired small grain size macrocell GCELL, be generally several to dozens of; Two, determine the inside annexation of small grain size macrocell GCELL circuit, the annexation between the macrocell to realize required logic, obtains element circuit structure storehouse and unit symbol storehouse; Three, according to circuit connecting relation, on physical structure, realize connecting, obtain the standard cell of cell library, obtain the domain storehouse.Standard cell: generally preestablish and provide, adopt full customization mode to be provided with, have the various basic logic functions modules of equal altitudes by technology manufacturer.These functional modules can realize various basic logic functions, and can realize the logic of any complexity in theory by combination.As inverter INV, buffer BUFFER, with door, or door, AND, trigger, latch, triple gate etc.Four, use the logic parameter extracting tool, the circuit performance parameters storehouse of extracting standard cell, i.e. logic parameter storehouse; Wherein also comprised the functional description storehouse.Five, obtain design rule and device parameter storehouse from technology manufacturer, thereby set up complete cell library; Comprise the required unit symbol of integrated circuit (IC) design storehouse, element circuit structure storehouse, domain storehouse, circuit performance parameters storehouse, functional description storehouse, design rule and device parameter storehouse.
Be that example specifies wiring method with the driving force inverter INVX1 of unit, 2 times of driving force inverter INVX2 respectively below, the standard cell that this method obtains is compared with standard cell in the traditional handicraft storehouse, physical structure is neat, and the various standard cells in the standard cell lib all can be decomposed into the GCELL of some at poly, active, N-Well layer.
Shown in Fig. 3-1,, realize the wiring process of INVX1 by small grain size macrocell GCELL is set.INVX1 is a unit driving force inverter, only needs 1 small grain size macrocell GCELL just can realize.Unit driving force inverter need link to each other source end S ground connection, the PMOS pipe that the source end S of PMOS pipe is connected to power supply, NMOS pipe with the drain terminal D of NMOS pipe, PMOS manages and links to each other with the grid G of NMOS pipe, just can obtain inverter, grid G is exported as input, drain terminal D, realized inverter and outside being connected.
Shown in Fig. 3-2, after the connection that the unit's of finishing driving force inverter circuit is provided with, in the kit virtuoso of Kai Dengsi cadence company, finish the connection of physical structure.Ohmic contact contact is abbreviated as CT in the unit driving force inverter physical structure, ground floor metal metal1 is abbreviated as M1, corresponding annexation:
1, the source end S of PMOS is connected to power supply: one of them P of PMOS pipe
+Link to each other with power supply by CT, M1;
2, the source end S ground connection of NMOS pipe: one of them N of NMOS pipe
+Link to each other with power supply by CT, M1;
3, the PMOS pipe links to each other with the drain terminal D of NMOS pipe: another P of PMOS
+Another N with NMOS
+Link to each other by CT, M1;
4, the PMOS pipe links to each other with the grid G of NMOS pipe: the PMOS pipe links to each other by CT, M1 with the grid G of NMOS pipe.
Shown in Fig. 4-1,, realize the wiring process of INVX2 by programming small grain size macrocell GCELL.INVX2 is 2 times of driving force inverters, can by and meet two small grain size macrocell GCELL and realize.2 times of driving force inverters need earlier two small grain size macrocell GCELL to be embodied as INVX1 respectively, link to each other the input of two INVX1, export continuous then, be specially: source end S ground connection, all PMOS pipe that the source end S of PMOS pipe is connected to power supply, NMOS pipe links to each other with the drain terminal D of NMOS pipe, all PMOS manage and link to each other with the grid G of NMOS pipe, grid G is exported as input, drain terminal D, realized inverter and outside being connected.
Shown in Fig. 4-2, after finishing 2 times of driving force inverter circuits connections, in the kit virtuoso of Kai Dengsi cadence company, finish the connection of physical structure.CT is that contact, M1 are metal1 in 2 times of driving force inverter physical structures, and corresponding annexation is as follows:
1, the source end S of PMOS pipe is connected to power supply: one of them P of PMOS pipe
+Link to each other with power supply by CT, M1;
2, the source end S ground connection of NMOS pipe: one of them N of NMOS pipe
+Link to each other with power supply by CT, M1;
3, the PMOS pipe links to each other with the drain terminal D of NMOS pipe: another P of all PMOS pipes
+Another N with the NMOS pipe
+Link to each other by CT, M1; G1 realizes that by V1, M2 drain terminal D links to each other with G2;
4, the PMOS pipe links to each other with the grid G of NMOS pipe: all PMOS pipes link to each other by CT, M1 with the grid G of NMOS pipe; G1 realizes that by V1, M2 grid G links to each other with G2.
After the circuit structure storehouse of having set up standard cell and domain storehouse, use Library Construction Kit [Microsoft FoxPro], as the logic parameter storehouse that library software siliconsmart obtains standard cell of building of MAGMA company, and then set up complete standard cell lib.
As shown in Figure 5, prior art ASIC is provided with and manufacture method, may further comprise the steps: one, application-specific integrated circuit (ASIC) setting and emulation: the concrete function that will realize according to circuit, with hardware setting language register transfer and design language RTL code description hardware effort process, and carry out code emulation; Two, application-specific integrated circuit (ASIC) comprehensively reaches emulation: comprehensively be meant and use the electric design automation eda tool, the RTL code is become the process of the domain of representing bottom side circuit physical connection structure, use synthesis tool, logic synthesis tool Design Compiler (DC) as new think of Synopsys, the RTL code is carried out comprehensively, and the net table that comprehensive back is produced carries out emulation; Net table: describe the file of whole logic in the circuit level, wherein transistor kind, size, the interconnection situation used have been made concrete description, can be by identifications such as emulation tools; Emulation: in computer, utilize software environment, the ruuning situation of simulation side circuit; Three, placement-and-routing and emulation: use placement-and-routing's instrument, the instrument ENCOUNTER of placement-and-routing as Kai Dengsi Cadance company, net table after calling comprehensively carries out placement-and-routing, on physical layer, each circuit part is arranged in place, spatially rationally arrange various lines, and the net table that produces carried out emulation, technology manufacturer manufactures to can directly giving of producing, and represents the graphics description file domain of side circuit physical structure to be Design Rule Checking DRC (Design Ruler Check), domain and logical circuit consistency check LVS (LayoutVS Schematic); Four, chip light shield and production: finish the production and the flow of whole masks; Five, chip testing: chip is tested.
Prior art adopt the ASIC wiring of standard cell design to have the problem of the following aspects and the production that can not realize master slice in advance to save cost: 1, each standard logical unit of standard cell lib technology library that is used for designing that is provided by technology factory is at poly, P
+/ N
+Physical layer enough not regular so that it can be split as the granule of same structure; 2, in above-mentioned steps three, except that the specific design project needs, without any restriction, each macrocell SRAM SRAM, phase-locked loop pll particular location do not have any restriction on the space yet in concrete locus in the placement-and-routing zone on whole chips; 3, in above-mentioned steps four, whenever finish and arrange a new integrated circuit project, need produce whole masks again, also need to finish all processes of flow, as injecting N-Well, growth Poly.
As shown in Figure 6, the structured ASIC implementation method based on the small grain size macrocell of the present invention based on the structuring realization of small grain size macrocell, is divided into time production of master slice setting and general layer, special chip setting and rest layers time production.General level is meant the confirmable physical level of being determined by the bottom domain to realizing that different chips all are suitable for; The residue level is meant in order to finish the production of complete chip, the level that also need continue to produce on general layer.
Time production of master slice setting and general layer may further comprise the steps: one, small grain size macrocell GCELL is set, as shown in Figure 1, is made up of a PMOS pipe and a NMOS pipe, length and width are the integral multiple of grid; Two, cell library is set, shown in Fig. 2, Fig. 3-1, Fig. 3-2, Fig. 4-1 and 4-2, all standard logical units are programmed by metal wire by small grain size macrocell GCELL in the cell library, arrange that suitable line builds; Three, the array of being made up of small grain size macrocell GCELL is set, on master slice, marks off the zone that needs scale (as the 50W door), the horizontal vertical both direction GCELL unit that gathers; Four, other required general utility functions modules that realized of circuit are set, it is structurized module, comprise input-output unit IO, SRAM SRAM, phase-locked loop pll, required various intellectual property macroblocks, and set up the comprehensive storehouse of general utility functions module; Five, physical layer pre-layout is carried out physically arrangement with the position of each type of structured unit by structure, integrated mode and combined density; Six, prewiring aspect physical structure, carries out manual wiring to the line of determining, for connecting with metal wire inner the connection in advance of clear and definite power supply, interconnection resource and unit; Seven, preceding road light shield and production are transferred to the manufacturer with fixed circuit bottom domain and are produced, and produce master slice.
Time production of special chip setting and rest layers may further comprise the steps: one, the special chip logic is provided with, the setting of logical circuit and emulation, the checking of function sequential.Special chip logic herein is provided with, and is the chip setting of complete circuit function, comprises general module and variable logic.Two, use eda tool to carry out the comprehensive of special chip, it becomes the variable logic circuit synthesis by the circuit that the unit connected in the standard cell lib, and general module is corresponded to corresponding module in the comprehensive storehouse of general module; And gate leve checking.Three, back wiring, net table that obtains after comprehensive and constraint are handled through mapping, both used assistant software, the unit that comprehensively obtains is corresponded to standard cell in the cell library, again placement-and-routing's information of master slice is imported layout tool layout together, finish the placement-and-routing of physical structure.Four, special chip is produced in road light shield and production behind the chip.Five, chip testing.
As shown in Figure 7, the back wiring may further comprise the steps: one, special chip net table and the mapping of constraint process that is provided with according to customer requirements, merge the practical layout wiring information of master slice, the net table is made specific aim revise, at the new net table and the constraint of net table generation of actual master slice; Constraint is mainly position constraint, tells which space of wiring tool to have the unit, can not be used for connecting up; And the device resource that provides on the various actual master slice of not using in user's design comprises the SRAM that does not use, PLL, and IP, PAD etc. are supplied it by tool software, even user's part net table extends to the complete net table on the actual master slice; Two, be the logical block of basic building owing to having adopted with GCELL in the net table, new net table in order to prevent dislocation, is provided with the integral multiple that cell gap is the GCELL width, placement-and-routing under the support of cell library; Three, do not use in the domain that the user comprehensively obtains, but exist the place of GCELL to fill small grain size macrocell GCELL on the actual master slice, domain that obtains and actual master slice correspondence produce domain.
Structured ASIC implementation method based on the small grain size macrocell of the present invention, compare based on the ASIC design of standard cell with prior art, main difference is that prior art ASIC is resolved into twice based on the light shield in the ASIC of the standard cell design to be finished, and its characteristics are: 1, in the cell library each unit at poly, P
+/ N
+Physical layer regular structure is arranged, can resolve into the granule of same structure; 2, the contrast prior art is based on the ASIC design procedure three of standard cell, except that project needs, the placement-and-routing zone is spatially restricted, each macrocell, as SRAM, PLL, particular location is also restricted, because defined the particular location of placement-and-routing zone and each macrocell on the master slice; 3, a new special chip is produced in each design, only need to produce again the mask of layers such as contact, Via, Metal, and the operation that master slice has been finished is omitted, and can directly continue to produce on the basis of master slice, can save cost, the shortening construction cycle of part mask and operation.
Present other structured ASIC implementation method compared to existing technology, the main distinction is that other structured ASIC generally adopts coarse granule (approximately also will comprise 3-4 gate circuit in the most fine grain logic module, great majority then are 20-40 gate circuit), the mode of look-up table is so that by the quick conversion of FPGA to ASIC; It realizes that density is lower, and needs special design tool and flow process.And the present invention has adopted short grained macrocell, can realize higher functional density, and compatible tradition is based on the IC design cycle and the eda tool of standard cell, various IC design experiences before can utilizing, higher reliability is arranged, and save tool software cost and manpower learning cost again.
Structured gate array technology compared to existing technology, the present invention has adopted Structured Design, and has partly adopted the mode of sea of gates at variable logic; But the wiring of structured gate array adopts CAD (computer-aided design) software to carry out, can only be communicated with each several part and can not sequential be optimized, can not make full use of present various advanced persons' EDA wiring tool, be difficult to realize chip functions, be on the verge of to be eliminated in the wiring step.The present invention is then by setting up based on the small grain size macrocell, complete standard cell lib, and the control by when wiring, each standard cell that comprehensively obtains is mapped on each small grain size macrocell of master slice just, thereby compatible ASIC design cycle and various corresponding tool software based on standard cell, realize the wiring process that temporal constraint drives, its wiring is optimized very much, can well realize chip functions.
Embodiment, as Fig. 8 and shown in Figure 9, present embodiment is at the instrument ENCOUTER of Cadance placement-and-routing environment, file designation: master slice associated documents called after asic.xxx, special chip associated documents called after fifo.xxx, the file designation that back wiring mapping produces is eda.xxx.
Step 1: the structuring unit is provided with, various IP is provided with.Master slice concrete application under the main consideration certain scale is set, accomplish to satisfy the most of demand under this kind scale as far as possible.This is provided with scale is the 50W gate, and the SRAM and the PLL of configuration some.
Resource: comprise small grain size macrocell GCELL array, SRAM, PLL, four parts of I0, wherein 4 PLL, 264kbit dual-port SRAM, 160 two-way IO, 20 couples of VDD/GND.
The door number:
Die size core size 4200 * 4200um * um=17.6mm * mm
Static memory sram 1213.7 * 907.9 * 4um * um=4.4mm * mm
250.5×216.7×32um×um＝1.7mm×mm
Phase-locked loop pll 621 * 265 * 4um * um=0.7mm * mm
Macrocell gcell (17.6-4.4-1.7-0.7)/(5.22 * 1.74 * 10e-6)=1.19 * 10e6
So according to 85% utilance, master slice can provide 100W small grain size macrocell GCELL, i.e. 50W door.
Arrange: as shown in Figure 8, PLL splits four corners, and SRAM is symmetrically distributed, and VDD/GND distributes according to current driving ability.
Step 2: pre-layout wiring:
(1), analyzes layout macrocell position, small grain size macrocell GCELL array region in ENCOUNTER by the master slice designer according to step 1;
(2) on the domain of master slice, finish being connected of VDD/GNDPAD and power ring;
(3) use ENCOUNTER to derive physical layout information asic.pdef.The concrete operations language is: Design-＞Save-＞PDEF;
(4) fill small grain size macrocell GCELL, derive GDS.The concrete operations language is: Design-＞Save-＞GDS.
Step 3: master slice preceding road light shield and production:
(1) submits to GDS to give mask factory, finish and determine N-Well, Active, P
+/ N
+, the needed mask of Poly layer;
(2) submit the mask manufacturer to, finish N-Well, Active, P
+/ N
+, the needed operation of Poly layer;
(3) preserve the silicon chip of finishing the part operation in the step (2).
Step 4: special chip setting and emulation, finish the setting of FIFO:
(1) determines the designing requirement SPEC of special chip;
(2) algorithm is set;
(3) write code;
(4) use Modelsim/NC verilog emulation.
Step 5: special chip comprehensively reaches emulation:
(1) integrated environment is set;
(2) write comprehensive constraint;
(3) call Design Compile and carry out comprehensively, and produce net table (.v), constraint (.sdc) and time-delay file (.sdf);
(4) use Modelsim/NC verilog emulation, and reactionary slogan, anti-communist poster delayed data SDF.
Step 6: the back wiring, earlier the information of the information of master slice and special chip is merged, tool using software produces new net table, placement-and-routing's information, controls the LAYOUT instrument then and finishes placement-and-routing.
(1) net table mapping (.v); In the top layer of fifo_pad.v additional untapped PAD, SRAM, PLL module, generate new net table eda.v;
(2) placement-and-routing's information (.pdef) according to the call level of special chip to SRAM, is revised the path of SRAM among the asic.pdef, generates the new information eda.pdef of placement-and-routing.
(3) as shown in Figure 9, net table eda.v is read in placement-and-routing, and calls in the information eda.pdef of placement-and-routing, finishes layout cloth;
(4) fill small grain size macrocell GCELL, and derive GDS.
Step 7: back road light shield and production:
(1) submits to GDS to give mask factory, finish and determine Contact, Via, the needed mask of Metal layer;
(2) submit mask to, on the master slice basis, finish Contact, Via, the needed operation of Metal layer;
(3) obtain special chip.
Step 8: test, chip is tested.
Promptly finish total ASIC setting up procedure.
Method embodiment of the present invention is based on layout layout instrument placement-and-routing the time, and standard cell all is to be arranged on the grid point, if: (1) all standard cells all can cut into the minimum unit of same structure level; (2) the minimum unit length and width are the grid integral multiple; (3) the standard unit interval is the minimum unit integral multiple during placement-and-routing; Then behind placement-and-routing, filling minimum unit, can on the grid in placement-and-routing zone, form compact arranged minimum unit array.Therefore, based on the result of placement-and-routing of said method, most of physical layer can be general in the different product exploitation.
Above-mentioned minimum unit is defined as the small grain size macrocell in the method for the present invention, is designated as GCELL.It is made up of a NMOS pipe and a PMOS pipe, and the drain-source grid are all unsettled.Length and width all are the integral multiples of grid.Its poly, P
+/ N
+Layer is connected with outside the realization by contact, via, metal.
All standard cells all are the small grain size macrocell GCELL by some in the cell library, obtain different driving, difference in functionality by programming contact, via, metal.Because each standard cell is by integer transversely arranged forming of small grain size macrocell GCELL, and the length and width of small grain size macrocell GCELL all are the integral multiples of grid, therefore, the length and width of each standard cell also are the integral multiples of grid.They are connected with outside the realization by via, metal.
The support of cell library has been arranged, when placement-and-routing,, revises by technical papers as long as being carried out part, the integral multiple that is spaced apart small grain size macrocell GCELL between the standard cell, after placement-and-routing is intact, fill small grain size macrocell GCELL, form a small grain size macrocell GCELL and closely arrange the array that forms, additional contact, via, metal just can get the specific product that needs to the end.If the placement-and-routing zone is certain, in any case operation, the small grain size macrocell GCELL array of Huo Deing is in full accord at last.
Method of the present invention utilizes the structuring of small grain size macrocell to realize ASIC, and the application-specific integrated circuit (ASIC) product is resolved into two stages: be provided with and produce general level, promptly be provided with and produce master slice earlier; At certain concrete setting, under the support of cell library, finish comprehensive and automatic placement and routing, obtain contact, via, the metal layer of special chip, light shield and production on the basis of master slice obtain special chip.The master slice setting comprises (1) small grain size macrocell GCELL array, (2) phase-locked loop pll/AD conversion unit ADC analog module setting, the setting of (3) SRAM memory module, (4) PAD, promptly all confirmable parts can be included in during master slice is provided with, and can produce the physical layer that GCELL determines in advance.Wiring after the setting of dedicated IC chip is finished, concrete operation method is that master slice information is called in layout (layout) instrument, placement-and-routing is finished in the constrained layout zone.
As shown in figure 10, aspect physics, it is that coordinate carries out that the setting of actual domain is based on the network lattice point, and the unit of network lattice point is decided by the wire distribution distance pitch of technology decision.Among the last figure, two wire frames are two parallel metal connecting lines, and its width is determined by technology; Need to satisfy the minimum spacing that rule request is set between two metal line, so in order to realize correct wiring, the center line of two metal line needs the width at a distance of a pitch.This point is identical with whole standard cell ASIC design cycle.The following metal wire of layer 6 metal uses identical pitch, and the layer 6 metal wire uses 2 times pitch.
Claims (3)
1. the setting of a structured application-specific integrated circuits and production method may further comprise the steps: one, master slice setting and production are used for that general utility functions module, cell library to application-specific integrated circuit (ASIC) is provided with and the production of the general level of master slice; Two, special chip setting and production are used for application-specific integrated circuit (ASIC) is provided with and finishes the production of residue level on the master slice basis;
Described master slice setting and production may further comprise the steps: one, the small grain size macrocell is set; Two, set up cell library; Three, the array of being made up of the small grain size macrocell is set, on master slice, marks off the zone that needs scale, the horizontal vertical both direction small grain size macrocell that gathers; Four, the required general utility functions module of circuit is set; Five, physical layer pre-layout; Six, prewiring; Seven, master slice is produced in preceding road light shield and production; Described small grain size macrocell is made up of a PMOS pipe and a NMOS pipe, and length and width are the integral multiple of grid;
Element circuit in the described cell library is to be spliced by metal connecting line by several same small grain size macrocell;
Described general utility functions module comprises: input-output unit (IO), SRAM (SRAM), phase-locked loop (PLL) and intellectual property macroblock;
Described physical layer pre-layout is that physically arrangement is carried out by structure, integrated mode and combined density in the position of each type of structured unit;
Described prewiring is aspect physical structure, and the line of determining is carried out manual wiring, for connecting with metal wire inner the connection in advance of clear and definite power supply and unit;
Time production of described special chip setting and rest layers may further comprise the steps: one, the application-specific integrated circuit (ASIC) logic module is provided with; Two, use eda tool to carry out the comprehensive of application-specific integrated circuit (ASIC) and gate leve checking; Three, back wiring, the placement-and-routing that finishes physical structure; Four, special chip is produced in road light shield and production behind the chip; Five, chip testing.
2. the setting of structured application-specific integrated circuits according to claim 1 and production method, it is characterized in that: the setting of described application-specific integrated circuit (ASIC) logic is to whole special integrated circuit, carries out the setting and the emulation of logical circuit, the checking of function sequential.
3. the setting of structured application-specific integrated circuits according to claim 2 and production method, it is characterized in that: the wiring of described back may further comprise the steps: one, special chip net table and the mapping of position constraint process that is provided with according to customer requirements, merge the practical layout wiring information of master slice, the net table is made an amendment, produce special chip net table and constraint; Two, placement-and-routing; Three, on master slice, exist and partially filled small grain size macrocell that special chip is not used, obtain the net table of complete circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810067180XA CN101320707B (en) | 2008-05-19 | 2008-05-19 | Integrated circuit setting and production method especially for structuration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810067180XA CN101320707B (en) | 2008-05-19 | 2008-05-19 | Integrated circuit setting and production method especially for structuration |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101320707A CN101320707A (en) | 2008-12-10 |
| CN101320707B true CN101320707B (en) | 2010-06-09 |
Family
ID=40180676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810067180XA Expired - Fee Related CN101320707B (en) | 2008-05-19 | 2008-05-19 | Integrated circuit setting and production method especially for structuration |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101320707B (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102314531B (en) * | 2010-07-02 | 2013-04-17 | 北京华大九天软件有限公司 | Automatic hierarchy construction method for integrated circuit layout |
| CN101945518B (en) * | 2010-09-16 | 2013-07-10 | 张国鹏 | Method for producing energy-saving dimming integrated circuit adaptable to light sources |
| US8607172B2 (en) * | 2011-10-06 | 2013-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods of designing the same |
| US8902625B2 (en) * | 2011-11-22 | 2014-12-02 | Marvell World Trade Ltd. | Layouts for memory and logic circuits in a system-on-chip |
| US20150356232A1 (en) * | 2014-06-06 | 2015-12-10 | Synopsys, Inc. | Method and System for Generating a Circuit Design, Method for Calibration of an Inspection Apparatus and Method for Process Control and Yield Management |
| CN105760558B (en) * | 2014-12-16 | 2019-04-09 | 京微雅格（北京）科技有限公司 | The layout method of multi input look-up table in fpga chip |
| CN106529043A (en) * | 2016-11-14 | 2017-03-22 | 无锡华润矽科微电子有限公司 | Method for carrying out sub-module comprehensive design on circuit on basis of computer software |
| TWI674823B (en) * | 2017-06-16 | 2019-10-11 | 矽品精密工業股份有限公司 | System and method for automatic layout |
| CN110660792B (en) * | 2019-09-30 | 2022-03-18 | 上海华力微电子有限公司 | Method for generating filling pattern of FDSOI standard cell and layout method |
| CN111766840B (en) * | 2020-06-09 | 2022-05-31 | 深圳创维－Rgb电子有限公司 | Manufacturing and implementing method of production master slice and storage medium |
| CN113128142B (en) * | 2021-04-27 | 2022-04-01 | 北京智芯仿真科技有限公司 | Integrated circuit electromagnetic simulation coarse grain parallel method and device based on file lock |
| CN116736061A (en) * | 2023-05-09 | 2023-09-12 | 珠海妙存科技有限公司 | Triode matching precision detection method, controller and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1347566A (en) * | 1999-04-16 | 2002-05-01 | 东京电子株式会社 | Method of mfg. semiconductor device and mfg. line thereof |
| CN1520565A (en) * | 2000-12-07 | 2004-08-11 | 凯登斯设计系统有限公司 | Routing method and appts. |
| CN1770448A (en) * | 2004-11-05 | 2006-05-10 | 富士通株式会社 | Semiconductor integrated circuit and design method therefor |
| CN101145169A (en) * | 2007-06-14 | 2008-03-19 | 上海芯域微电子有限公司 | Module group, macrocell, standard unit synchronous layout convergence method and system for SoC integrated circuit automatic layout design |
-
2008
- 2008-05-19 CN CN200810067180XA patent/CN101320707B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1347566A (en) * | 1999-04-16 | 2002-05-01 | 东京电子株式会社 | Method of mfg. semiconductor device and mfg. line thereof |
| CN1520565A (en) * | 2000-12-07 | 2004-08-11 | 凯登斯设计系统有限公司 | Routing method and appts. |
| CN1770448A (en) * | 2004-11-05 | 2006-05-10 | 富士通株式会社 | Semiconductor integrated circuit and design method therefor |
| CN101145169A (en) * | 2007-06-14 | 2008-03-19 | 上海芯域微电子有限公司 | Module group, macrocell, standard unit synchronous layout convergence method and system for SoC integrated circuit automatic layout design |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101320707A (en) | 2008-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101320707B (en) | Integrated circuit setting and production method especially for structuration | |
| US10268793B2 (en) | System and method for designing cell rows | |
| Weste et al. | CMOS VLSI design: a circuits and systems perspective | |
| Liu et al. | Power consumption estimation in CMOS VLSI chips | |
| US9536035B2 (en) | Wide pin for improved circuit routing | |
| US20160085898A1 (en) | Automated layout for integrated circuits with nonstandard cells | |
| US7614020B2 (en) | Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems | |
| US11030380B2 (en) | Synergistic design method for fabricating integrated circuit | |
| CN101351886A (en) | ASIC design using clock and power grid standard cell | |
| WO2005119441A2 (en) | Methods and systems for structured asic eletronic design automation | |
| US20090293035A1 (en) | Increased effective flip-flop density in a structured asic | |
| CN103793547B (en) | The method with the hierarchic design of the integrated circuit that many patternings require | |
| CN102637217B (en) | Large-scale integrated circuit wiring system based on cloud computing platform | |
| Kim et al. | Chiplet/interposer co-design for power delivery network optimization in heterogeneous 2.5-D ICs | |
| CN106339532B (en) | Base unit, standard block, standard cell lib, rear end Full-custom design method, chip | |
| US6240543B1 (en) | Integration of manufacturing test of multiple system on a chip without substantial simulation | |
| CN107967372A (en) | A kind of FPGA total arrangements legalize method | |
| US20220171912A1 (en) | Poly-bit cells | |
| US11159163B2 (en) | Single phase clock-gating circuit | |
| Harter et al. | Three-dimensional integrated circuit layout | |
| Stringfellow et al. | Decoupling capacitance estimation, implementation, and verification: A practical approach for deep submicron SoCs | |
| CN1046822C (en) | Method for manufacturing MOS transistor IC with 10,000 gates | |
| Toyonaga et al. | A practical clock tree synthesis for semi-synchronous circuits | |
| Karna et al. | Impact on the Performance of North Bridge I/O Peripheral Component Interconnect Express Block in Physical Design Flow Considering Two Different Synthesis Corners at below 10nm Technology Node | |
| Reinhardt et al. | Integrating Automatic Layout Modification and Physical Design Reuse into Existing Design Flows |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: GUOWEI ELECTRONICS CO., LTD., SHENZHEN Free format text: FORMER OWNER: SHENZHEN STATE MICRO TECHNOLOGY CO., LTD. Effective date: 20120917 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| C56 | Change in the name or address of the patentee |
Owner name: SHENZHEN STATE MICRO TECHNOLOGY CO., LTD. Free format text: FORMER NAME: SHENZHEN STATE MICRO HOLDINGS CO., LTD. Owner name: SHENZHEN STATE MICRO HOLDINGS CO., LTD. Free format text: FORMER NAME: GUOWEI ELECTRONICS CO., LTD., SHENZHEN |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park South high SSMEC building six floor Patentee after: Shenzhen State Micro Electronics Holding Co.,Ltd. Address before: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park South high SSMEC building six floor Patentee before: Shenzhen State Micro Electronics Holding Co.,Ltd. Address after: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park South high SSMEC building six floor Patentee after: Shenzhen State Micro Electronics Holding Co.,Ltd. Address before: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park South high SSMEC building six floor Patentee before: SHENZHEN STATE MICROELECTRONICS Co.,Ltd. |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20120917 Address after: 6, 518057 floor, state micro building, Southern District of Shenzhen hi tech Industrial Park, Guangdong, China Patentee after: SHENZHEN STATE MICROELECTRONICS Co.,Ltd. Address before: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park South high SSMEC building six floor Patentee before: Shenzhen State Micro Electronics Holding Co.,Ltd. |
|
| C56 | Change in the name or address of the patentee |
Owner name: SHENZHEN STATEMICRO ELECTRONICS CO., LTD. Free format text: FORMER NAME: GUOWEI ELECTRONICS CO., LTD., SHENZHEN |
|
| CP03 | Change of name, title or address |
Address after: 518000 Guangdong city of Shenzhen province Nanshan District Gao Xin Road No. 015 building six layer A in micro research Patentee after: SHENZHEN STATE MICROELECTRONICS Co.,Ltd. Address before: 6, 518057 floor, state micro building, Southern District of Shenzhen hi tech Industrial Park, Guangdong, China Patentee before: SHENZHEN STATE MICROELECTRONICS Co.,Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100609 Termination date: 20210519 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |