CN114943200B

CN114943200B - Automatic layout method and device for MOSFET

Info

Publication number: CN114943200B
Application number: CN202210587410.5A
Authority: CN
Inventors: 叶佐昌; 王燕; 郝晶磊
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2022-05-26
Filing date: 2022-05-26
Publication date: 2023-04-28
Anticipated expiration: 2042-05-26
Also published as: CN114943200A

Abstract

The present disclosure relates to the field of integrated circuit technologies, and in particular, to an automatic layout method and apparatus for a MOSFET. The automatic layout method of the MOSFET comprises the following steps: acquiring at least one MOS parameter set of a metal oxide semiconductor field effect transistor; constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout modules; and according to the MOS Array modules, laying out at least two MOS modules to obtain circuit layouts corresponding to the at least two MOS modules. The layout cost and error rate of the MOSFET can be reduced, the layout efficiency of the MOSFET is improved, and the layout standard of the MOSFET is unified.

Description

Automatic layout method and device for MOSFET

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to an automatic layout method and apparatus for a MOSFET.

Background

An integrated circuit (Integrated Circuit, IC) is a microelectronic device or component with specific functions that integrates a number of commonly used electronic components, such as resistors, capacitors, transistors, etc., and the wiring between these components, through semiconductor processing. Therefore, the integrated circuit has the advantages of small volume, light weight, few pins, long service life, high reliability, low cost, good performance and the like, and is convenient for mass production.

With the rapid development of integrated circuits, the number of Metal-Oxide-semiconductor field effect transistors (MOSFETs, MOS) contained in a single chip is increasing. However, in the related art, MOSFET layout needs to be manually performed by a person in the design process of an analog circuit in a chip. However, the manual MOSFET layout requires a large amount of layout knowledge to be understood by the operator, and the layout cost is high. Meanwhile, the connection of each MOSFET needs to be controlled manually, so that the efficiency is low and the error rate is high. In addition, the placement standard adopted when MOSFET layout is manually performed is personalized, and under the condition that the same function is realized, layouts obtained by different operators are different.

Disclosure of Invention

The present application aims to solve, at least to some extent, one of the technical problems in the related art.

Therefore, a first objective of the present application is to provide an automatic layout method of MOSFETs, so as to reduce layout cost and error rate of MOSFETs, improve layout efficiency of MOSFETs, and unify placement criteria of MOSFETs during layout.

A second object of the present application is to propose an automatic layout device of a MOSFET.

To achieve the above object, an automatic layout method of a MOSFET according to an embodiment of a first aspect of the present application includes:

acquiring at least one MOS parameter set of a metal oxide semiconductor field effect transistor;

constructing at least two MOS modules based on the at least one MOS parameter set according to the MOS Layout module;

and according to the MOS Array modules, the at least two MOS modules are laid out to obtain circuit layouts corresponding to the at least two MOS modules.

Optionally, in an embodiment of the present application, the MOS parameter set includes a drain node parameter, a gate node parameter, a source node parameter, a drain source offset parameter, a drain source pitch parameter, and a via layer minimum width parameter, a via layer corresponding to the via layer minimum parameter is used to connect the first metal layer and the second metal layer, and the constructing at least two MOS modules according to the MOS Layout and based on the at least one MOS parameter set includes:

generating a drain node, a gate node, and a source node based on the drain node parameter, the gate node parameter, and the source node parameter;

constructing a drain rectangle, wherein the drain rectangle comprises a first active area layer rectangle and a first metal layer rectangle which are the same in size, the first active area layer rectangle and the first metal layer rectangle are connected to the drain node, and the first metal layer rectangle is a source port of an MOS module;

Constructing a source electrode rectangle, wherein the source electrode rectangle comprises a second active area layer rectangle and a second first metal layer rectangle which are the same in size, the second active area layer rectangle and the second first metal layer rectangle are both connected to the source electrode node, and the second first metal layer rectangle is a drain electrode port of the MOS module;

constructing a grid rectangle, wherein the grid rectangle is a polysilicon layer rectangle, the polysilicon layer rectangle is connected to the grid node, and the polysilicon layer rectangle is a grid port of the MOS module;

constructing a third active region layer rectangle according to the drain-source offset parameter, the drain-source spacing parameter and the minimum width parameter of the via layer;

and determining an MOS module according to the drain electrode rectangle, the source electrode rectangle, the grid electrode rectangle and the third active region layer rectangle.

Optionally, in one embodiment of the present application, the MOS parameter set further includes a length parameter, a width parameter, and a first metal layer minimum pitch parameter; wherein,,

the length of the first active area layer rectangle, the length of the first metal layer rectangle, the length of the second active area layer rectangle and the length of the second first metal layer rectangle are the minimum width parameters of the via hole layer;

The width of the first active area layer rectangle, the width of the first metal layer rectangle, the width of the second active area layer rectangle and the width of the second first metal layer rectangle are the width parameters;

the length of the polysilicon layer rectangle is the length parameter, and the width of the polysilicon layer rectangle is determined by the minimum distance parameter of the first metal layer and the width parameter.

Optionally, in an embodiment of the present application, the MOS parameter set further includes a length parameter, and constructing a MOS module according to the drain rectangle, the source rectangle, the gate rectangle, and the third active region layer rectangle includes:

controlling the drain rectangle and the source rectangle to be horizontally aligned to obtain a drain-source rectangle, wherein the distance between the drain rectangle and the source rectangle is determined by the length parameter and the drain-source distance parameter;

and controlling the third active region layer rectangle, the drain electrode source electrode rectangle and the grid electrode rectangle to be aligned in the middle to obtain the MOS module.

Optionally, in an embodiment of the present application, the layout of the at least two MOS modules according to the MOS Array module includes:

Controlling the at least two MOS modules to be horizontally aligned and placed, and controlling the at least two MOS modules to be placed in parallel;

ports of the at least two MOS modules after being placed are constructed;

determining the MOS type of each MOS module in the at least two MOS modules based on the module parameter information set;

and controlling the at least two MOS modules to be converted into MOS modules corresponding to the MOS types so as to obtain MOSArray.

Optionally, in an embodiment of the present application, the ports include a mosapray source port, a mosapray drain port, and a mosapray gate port, and the ports of the at least two MOS modules after the constructing and placing include:

if a construction instruction aiming at the third first metal layer rectangle is obtained, expanding the at least two MOS modules based on the expansion direction parameter, and constructing at least two third first metal layer rectangles so as to control the at least two MOS modules to be connected to the same node;

determining the port based on node type information;

and if the construction instruction aiming at the third first metal layer rectangle is not acquired, setting a source port, a drain port and a gate port of each MOS module in the at least two MOS modules as the MOSArray source port, the MOSArray drain port and the MOSArray gate port.

Optionally, in one embodiment of the present application, the node type information includes first node type information and second node type information, and determining the port based on the node type information includes:

if the node type information is first node type information, setting the third first metal layer rectangle as the MOSArray gate port, and setting a source port and a drain port of each MOS module of the at least two MOS modules as the MOSArray source port and the MOSArray drain port;

if the node type information is second node type information, constructing a grid second metal layer rectangle, a source second metal layer rectangle and a drain second metal layer rectangle, wherein the grid second metal layer rectangle is connected to a grid port of each MOS module in the at least two MOS modules, the source second metal layer rectangle is connected to a source port of each MOS module in the at least two MOS modules, and the drain second metal layer rectangle and the third first metal layer rectangle are connected to the same node;

setting the grid second metal layer rectangle as the MOSArray grid port, setting the source second metal layer rectangle as the MOSArray source port, and setting the drain second metal layer rectangle as the MOSArray drain port.

Optionally, in an embodiment of the present application, the layout of the at least two MOS modules according to the MOS Array module is performed to obtain a circuit layout corresponding to the at least two MOS modules, and further includes:

if the at least two MOS modules are laid out according to the MOSArray module to obtain at least two MOSArray modules, controlling the at least two MOSArray modules to be vertically aligned and placed;

constructing a grid third metal layer rectangle, a source third metal layer rectangle and a drain third metal layer rectangle to obtain circuit layouts corresponding to the at least two MOS modules, wherein the grid third metal layer rectangle is connected to a MOSArray gate port of each of the at least two MOSArray, the source third metal layer rectangle is connected to a MOSArray source port of each of the at least two MOSArray, and the drain third metal layer rectangle is connected to a MOSArray drain port of each of the at least two MOSArray;

setting the grid electrode third metal layer rectangle as the grid electrode of the circuit layout, setting the source electrode third metal layer rectangle as the source electrode of the circuit layout, and setting the drain electrode third metal layer rectangle as the drain electrode of the circuit layout.

Optionally, in one embodiment of the present application, after said controlling the vertical alignment of the at least two mosapray, the method further includes:

and if an adding instruction aiming at the guard ring is obtained, adding the guard ring for the at least two MOSArray.

In summary, in the method provided in the embodiments of the present application, a set of MOS parameters of at least one mosfet is obtained; constructing at least two MOS modules based on the at least one MOS parameter set according to the MOS Layout module; and according to the MOS Array modules, the at least two MOS modules are laid out to obtain circuit layouts corresponding to the at least two MOS modules. Therefore, by adopting the MOSLayout module to construct the MOS module and adopting the MOSArray module to layout the MOS module, the layout cost and error rate of the MOSFET can be reduced, the layout efficiency of the MOSFET can be improved, and the layout standard of the MOSFET in the layout process can be unified.

To achieve the above object, an automatic layout device for a MOSFET according to an embodiment of a second aspect of the present application includes:

a set acquisition unit for acquiring at least one MOS parameter set of the metal oxide semiconductor field effect transistor;

The module construction unit is used for constructing at least two MOS modules based on the at least one MOS parameter set according to MOS Layout modules;

and the module layout unit is used for carrying out layout on the at least two MOS modules according to the MOS Array modules so as to obtain circuit layouts corresponding to the at least two MOS modules.

In summary, in the device provided in the embodiments of the present application, at least one MOS parameter set of the mosfet is obtained by the set obtaining unit; the module construction unit constructs at least two MOS modules based on the at least one MOS parameter set according to the MOS Layout modules; and the module layout unit performs layout on the at least two MOS modules according to the MOS Array modules so as to obtain circuit layouts corresponding to the at least two MOS modules. Therefore, by adopting the MOSLayout module to construct the MOS module and adopting the MOSArray module to layout the MOS module, the layout cost and error rate of the MOSFET can be reduced, the layout efficiency of the MOSFET can be improved, and the layout standard of the MOSFET in the layout process can be unified.

Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

fig. 1 is a flowchart of a first automatic layout method of MOSFETs according to an embodiment of the present disclosure;

fig. 2 is a schematic flow chart of an automatic layout method of a second MOSFET according to an embodiment of the present application;

fig. 3 shows a layout schematic diagram of a MOS module according to an embodiment of the present application;

fig. 4 is a schematic flow chart of an automatic layout method of a third MOSFET according to an embodiment of the present disclosure;

FIG. 5 shows a layout diagram of a first MOSArray provided by an embodiment of the present application;

FIG. 6 shows a layout diagram of a second MOSArray provided by an embodiment of the present application;

FIG. 7 is a schematic diagram of a layout of a second MOSArray according to an embodiment of the present application;

fig. 8 is a flowchart illustrating a fourth automatic layout method of MOSFETs according to an embodiment of the present disclosure;

FIG. 9 shows a layout diagram of a first circuit layout provided by an embodiment of the present application;

FIG. 10 shows a layout diagram of a second circuit layout provided by an embodiment of the present application;

fig. 11 is a schematic structural diagram of an automatic layout device of a MOSFET according to an embodiment of the present application.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application. On the contrary, the embodiments of the present application include all alternatives, modifications, and equivalents as may be included within the spirit and scope of the appended claims.

The present application is described in detail with reference to specific examples.

Fig. 1 shows a flow diagram of a first method for automatically laying out MOSFETs according to an embodiment of the present application, which may be implemented in dependence on a computer program and may be run on a device for performing the automatic layout of MOSFETs. The computer program may be integrated in the application or may run as a stand-alone tool class application.

The automatic layout device of the MOSFET may be a terminal having an automatic layout function of the MOSFET, including but not limited to: wearable devices, handheld devices, personal computers, tablet computers, vehicle-mounted devices, smart phones, computing devices, or other processing devices connected to a wireless modem, etc. Terminals may be called different names in different networks, for example: a user equipment, an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent or user equipment, a cellular telephone, a cordless telephone, a personal digital assistant (personal digital assistant, PDA), a fifth Generation mobile communication technology (5th Generation Mobile Communication Technology,5G) network, a fourth Generation mobile communication technology (the 4th Generation mobile communication technology,4G) network, a third Generation mobile communication technology (3 rd-Generation, 3G) network, or a terminal in a future evolution network, etc.

Specifically, the automatic layout method of the MOSFET comprises the following steps:

step 110, obtaining at least one MOS parameter set of a metal oxide semiconductor field effect transistor;

according to some embodiments, the MOS parameters refer to parameters that are needed when the terminal constructs the MOS module. The MOS parameter is not particularly limited to a fixed parameter. The MOS parameters include, but are not limited to, MOS module number parameters, drain node parameters, gate node parameters, source node parameters, drain-source offset parameters, drain-source pitch parameters, length parameters, width parameters, via layer minimum width parameters and first metal layer M1 minimum pitch parameters, extension direction parameters, via number parameters, module type parameters, and the like.

In some embodiments, a VIA1 layer corresponding to the VIA layer minimum width parameter and the VIA quantity parameter is used to connect the first metal M1 layer and the second metal M2 layer.

In some embodiments, a set of MOS parameters refers to a set of at least one MOS parameter that is aggregated. The MOS parameter set does not refer specifically to a fixed set. For example, the set of MOS parameters may change when the number of MOS parameters changes. The set of MOS parameters may also change when the content of the MOS parameters changes.

It will be readily appreciated that the terminal may obtain at least one set of MOS parameters when the terminal automatically lays out the MOSFETs.

Step 120, constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout Layout module;

according to some embodiments, a moslay module refers to a module employed when a terminal builds a MOS module.

In some embodiments, the MOS module refers to a module corresponding to a single MOSFET layout constructed by the terminal according to the MOS parameter set.

In some embodiments, the mosla yout module may construct, according to the MOS parameter set, a number of MOS modules corresponding to the number of MOS modules in the MOS parameter set.

It is easy to understand that when the terminal acquires at least one MOS parameter set, the terminal may construct at least two MOS modules based on the at least one MOS parameter set according to the MOS Layout module.

And 130, according to the MOS Array module, laying out at least two MOS modules to obtain a circuit layout corresponding to the at least two MOS modules.

According to some embodiments, the mosarory module refers to a module employed when the terminal lays out at least two MOS modules.

It is easy to understand that when the terminal constructs at least two MOS modules, the terminal may layout the at least two MOS modules according to the MOS Array module, so as to obtain a circuit layout corresponding to the at least two MOS modules.

In summary, the method provided by the embodiments of the present application includes obtaining at least one MOS parameter set of a metal oxide semiconductor field effect transistor; constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout modules; and according to the MOS Array modules, laying out at least two MOS modules to obtain circuit layouts corresponding to the at least two MOS modules. Therefore, by adopting the MOSLayout module to construct the MOS module and adopting the MOSArray module to layout the MOS module, the layout cost and error rate of the MOSFET can be reduced, the layout efficiency of the MOSFET can be improved, and the layout standard of the MOSFET in the layout process can be unified.

Referring to fig. 2, fig. 2 is a flow chart illustrating a second automatic layout method of MOSFETs according to an embodiment of the present application. Specifically, the automatic layout method of the MOSFET comprises the following steps:

step 210, obtaining at least one MOS parameter set;

according to some embodiments, when the terminal acquires at least one MOS parameter set, the terminal may acquire the at least one MOS parameter set by means of parameter transfer.

Step 220, generating a drain node, a gate node and a source node based on the drain node parameter, the gate node parameter and the source node parameter;

Step 230, constructing a drain rectangle, wherein the drain rectangle comprises a first active area layer rectangle and a first metal layer rectangle which are the same in size, the first active area layer rectangle and the first metal layer rectangle are connected to a drain node, and the first metal layer rectangle is a source port of the MOS module;

according to some embodiments, the length of the first active region layer rectangle, the length of the first metal layer rectangle is a via layer minimum width parameter. The width of the first active region layer rectangle and the width of the first metal layer rectangle are width parameters.

In some embodiments, when the terminal builds the drain rectangle, the terminal may control the first active region layer rectangle and the first metal layer rectangle to be placed in lower left corner alignment.

Step 240, constructing a source rectangle, wherein the source rectangle comprises a second active area layer rectangle and a second first metal layer rectangle which are the same in size, the second active area layer rectangle and the second first metal layer rectangle are both connected to a source node, and the second first metal layer rectangle is a drain port of the MOS module;

according to some embodiments, the length of the second active region layer rectangle and the length of the second first metal layer rectangle are via layer minimum width parameters. The width of the second active region layer rectangle and the width of the second first metal layer rectangle are width parameters.

In some embodiments, when the terminal builds the drain rectangle, the terminal may control the second active region layer rectangle and the second first metal layer rectangle to be placed in lower left corner alignment.

Step 250, constructing a grid rectangle, wherein the grid rectangle is a polysilicon layer rectangle, the polysilicon layer rectangle is connected to a grid node, and the polysilicon layer rectangle is a grid port of the MOS module;

according to some embodiments, the length of the polysilicon layer rectangle is a length parameter, and the width of the polysilicon layer rectangle is determined by the first metal layer minimum pitch parameter and the width parameter.

In some embodiments, the width of the polysilicon layer rectangle may be determined according to the following equation:

M1.min_spacing*2+w

wherein, M1.min_spacing is the minimum spacing parameter of the first metal layer, and w is the width parameter.

Step 260, constructing a third active region layer rectangle according to the drain-source offset parameter, the drain-source spacing parameter and the minimum width parameter of the via layer;

according to some embodiments, the length of the third active region layer rectangle may be determined according to the following equation:

2*ds_l+2*ds_spacing+ds_offset

where ds_l is the minimum width parameter of the via layer, ds_spacing is the drain-source spacing parameter, and ds_offset is the drain-source offset parameter.

Step 270, determining a MOS module according to the drain rectangle, the source rectangle, the gate rectangle, and the third active region layer rectangle;

According to some embodiments, fig. 3 shows a layout schematic of a MOS module according to an embodiment of the present application. As shown in fig. 3, when the terminal determines the MOS module according to the drain rectangle, the source rectangle, the gate rectangle, and the third active region layer rectangle, the terminal may control the drain rectangle and the source rectangle to be horizontally aligned to obtain the drain-source rectangle. Further, the terminal may control the third active region layer rectangle, the drain source rectangle, and the gate rectangle to be centered in alignment to obtain the MOS module.

In some embodiments, as shown in fig. 3, the gate rectangle is a polysilicon PO layer rectangle, and the drain rectangle and the source rectangle each include two active area AA layer rectangles and a first metal M1 layer rectangle of the same size. The active area AA layer rectangle is located below the first metal M1 layer rectangle.

In some embodiments, as shown in fig. 3, the third active area AA layer rectangle is located below the polysilicon PO layer rectangle and in the middle of the drain rectangle and the source rectangle.

In some embodiments, the spacing between the drain rectangle and the source rectangle is determined by a length parameter and a drain-source spacing parameter.

In some embodiments, the spacing between the drain rectangle and the source rectangle may be determined according to the following equation:

2*ds_spacing+l

Where ds_spacing is the drain-source spacing parameter.

According to some embodiments, when the termination determines the MOS module according to the drain rectangle, the source rectangle, the gate rectangle, and the third active region layer rectangle, the termination may further generate MOSFET netlist information corresponding to the MOS module.

According to some embodiments, when the terminal constructs the MOS module, if the terminal obtains the module type parameter from the module parameter information set, the terminal may control the module type of the MOS module to be converted into the MOS type corresponding to the module type parameter;

in some embodiments, when the module type parameter is PMOS, the terminal may construct an N-well layer rectangle and a p+ layer rectangle to cover the entire MOS module to obtain the PMOS module.

In some embodiments, when the module type parameter is NMOS, the terminal may construct an n+ layer rectangle covering the entire MOS module to obtain the NMOS module.

And 280, laying out at least two MOS modules according to the MOS Array modules to obtain circuit layouts corresponding to the at least two MOS modules.

In summary, the method provided by the embodiments of the present application includes obtaining at least one MOS parameter set of a metal oxide semiconductor field effect transistor; generating a drain node, a gate node, and a source node based on the drain node parameter, the gate node parameter, and the source node parameter; constructing a drain electrode rectangle, wherein the drain electrode rectangle comprises a first active region layer rectangle and a first metal layer rectangle which are the same in size, the first active region layer rectangle and the first metal layer rectangle are connected to a drain electrode node, and the first metal layer rectangle is a source electrode port of an MOS module; constructing a source electrode rectangle, wherein the source electrode rectangle comprises a second active area layer rectangle and a second first metal layer rectangle which are the same in size, the second active area layer rectangle and the second first metal layer rectangle are connected to a source electrode node, and the second first metal layer rectangle is a drain electrode port of the MOS module; constructing a grid rectangle, wherein the grid rectangle is a polysilicon layer rectangle, the polysilicon layer rectangle is connected to a grid node, and the polysilicon layer rectangle is a grid port of the MOS module; constructing a third active region layer rectangle according to the drain-source offset parameter, the drain-source spacing parameter and the minimum width parameter of the via layer; determining an MOS module according to the drain electrode rectangle, the source electrode rectangle, the grid electrode rectangle and the third active area layer rectangle; and according to the MOS Array modules, laying out at least two MOS modules to obtain circuit layouts corresponding to the at least two MOS modules. Therefore, by adopting the MOSLayout module to construct the MOS module and adopting the MOSArray module to layout the MOS module, the layout cost and error rate of the MOSFET can be reduced, the layout efficiency of the MOSFET can be improved, and the layout standard of the MOSFET in the layout process can be unified.

Referring to fig. 4, fig. 4 is a flowchart illustrating a third automatic layout method of MOSFETs according to an embodiment of the present application. Specifically, the automatic layout method of the MOSFET comprises the following steps:

step 310, obtaining at least one MOS parameter set;

step 320, constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout Layout module;

step 330, controlling at least two MOS modules to be horizontally aligned and placed, and controlling at least two MOS modules to be placed in parallel;

according to some embodiments, when the terminal controls the at least two MOS modules to be placed in parallel, the terminal may label the at least two MOS modules according to a placement order, and turn the MOS modules labeled as even numbers left and right. And then controlling the at least two MOS modules to be placed in a partially overlapped mode. The overlapping part is the source rectangle and the drain rectangle of the MOS module.

Step 340, constructing ports of at least two put MOS modules;

according to some embodiments, the ports of the at least two MOS modules after placement include a mosapray source port, a mosapray drain port, and a mosapray gate port.

According to some embodiments, when the terminal constructs the port of the at least two MOS modules after being put, if the terminal obtains a construction instruction for the third first metal layer rectangle, the terminal may expand the at least two MOS modules based on the expansion direction parameter, and construct a third first metal layer rectangle to control the at least two MOS modules to be connected to the same node. Furthermore, the terminal can determine the ports of at least two MOS modules after placement based on the node type information;

In some embodiments, the extension direction parameters include an up-extension parameter and a down-extension parameter. When the extension direction parameter is an upward extension parameter, the terminal may extend at least two MOS modules upward. When the extension direction parameter is a downward extension parameter, the terminal may perform downward extension on at least two MOS modules.

In some embodiments, when the terminal can expand the at least two MOS modules based on the expansion direction parameter, the terminal can expand the polysilicon layer rectangle of each of the at least two MOS modules, and further, the terminal can construct a third first metal layer rectangle connecting all the expanded polysilicon layer rectangles.

In some embodiments, the node type information includes first node type information and second node type information.

In some embodiments, if the node type information is the first node type information, the terminal may set the third first metal layer rectangle to be a mosapray gate port, and set a source port and a drain port of each of the at least two MOS modules to be a mosapray source port and a mosapray drain port;

in some embodiments, if the node type information is the second node type information, the terminal may construct a gate second metal layer rectangle, a source second metal layer rectangle, and a drain second metal layer rectangle. The grid electrode second metal layer rectangle is connected to the grid electrode port of each MOS module in the at least two MOS modules, the source electrode second metal layer rectangle is connected to the source electrode port of each MOS module in the at least two MOS modules, and the drain electrode second metal layer rectangle and the third first metal layer rectangle are connected to the same node. Furthermore, the terminal may set the gate second metal layer rectangle to be a mosapray gate port, set the source second metal layer rectangle to be a mosapray source port, and set the drain second metal layer rectangle to be a mosapray drain port.

In some embodiments, the terminal may obtain the first metal layer rectangle and the second first metal layer rectangle for each of the at least two MOS modules when the terminal builds the source second metal layer rectangle and the drain second metal layer rectangle. Furthermore, the terminal may construct a drain second metal layer rectangle connecting all the first metal layer rectangles, and a source second metal layer rectangle connecting all the second first metal layer rectangles.

In some embodiments, when the terminal builds a gate second metal layer rectangle, the terminal may obtain a third first metal layer rectangle built. Furthermore, the terminal can construct a grid second metal layer rectangle with the same size as the third first metal layer rectangle, and control the grid second metal layer rectangle and the third first metal layer rectangle to be connected to the same node.

In some embodiments, the width of the gate second metal layer rectangle, the width of the source second metal layer rectangle, and the width of the drain second metal layer rectangle are determined by via quantity parameters.

According to some embodiments, when the terminal constructs the ports of the at least two MOS modules after being put, if the terminal does not obtain a construction instruction for the third first metal layer rectangle, the terminal may set the source port, the drain port, and the gate port of each of the at least two MOS modules to be a mosarory source port, a mosarory drain port, and a mosarory gate port.

Step 350, determining the MOS type of each MOS module in at least two MOS modules based on the module parameter information set;

according to some embodiments, the module type parameters include PMOS type and NMOS type.

In step 360, at least two MOS modules are controlled to be converted into MOS modules corresponding to the MOS types, so as to obtain mosapray.

According to some embodiments, when the module type parameter is PMOS, the terminal may construct an N-well layer rectangle and a p+ layer rectangle to cover the entire mosaroray.

In some embodiments, when the module type parameter corresponding to the MOS module is NMOS, the terminal may construct an n+ layer rectangle to cover the entire mosaroray.

In some embodiments, fig. 5 shows a layout diagram of a first mosapray provided in an embodiment of the present application. As shown in fig. 5, the mosaroray includes three MOS modules connected in parallel, and these three MOS modules are not extended.

In some embodiments, fig. 6 shows a layout diagram of a second mosapray provided in an embodiment of the present application. As shown in fig. 6, the mosaroray includes three MOS modules connected in parallel, and the three MOS modules are extended upward, but the node type information is first node type information, that is, only one third first metal M1 layer rectangle is constructed to connect all the extended polysilicon PO layer rectangles.

In some embodiments, fig. 7 shows a layout diagram of a second mosapray provided in an embodiment of the present application. As shown in fig. 7, the mosaroray includes three MOS modules connected in parallel, and the three MOS modules are extended upward, but the node type information is second node type information, that is, three second metal M2 layer rectangles are constructed on the basis of fig. 6, where one second metal M2 layer rectangle is located above the third first metal M1 layer rectangle and has the same size as the third first metal M1 layer rectangle, one second metal M2 layer rectangle is connected to the gate port of each MOS module, and one second metal M2 layer rectangle is connected to the source port of each MOS module.

In summary, the method provided by the embodiment of the application includes obtaining at least one MOS parameter set of the mosfet; constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout modules; controlling at least two MOS modules to be horizontally aligned and placed, and controlling at least two MOS modules to be placed in parallel; ports of at least two MOS modules after being placed are constructed; determining the MOS type of each MOS module in at least two MOS modules based on the module parameter information set; and controlling at least two MOS modules to be converted into MOS modules corresponding to the MOS types so as to obtain MOSArray. Therefore, by adopting the MOSLayout module to construct the MOS module and adopting the MOSArray module to layout the MOS module, the layout cost and error rate of the MOSFET can be reduced, the layout efficiency of the MOSFET can be improved, and the layout standard of the MOSFET in the layout process can be unified.

Referring to fig. 8, fig. 8 is a flowchart illustrating a fourth method for automatic layout of MOSFETs according to an embodiment of the present application. Specifically, the automatic layout method of the MOSFET comprises the following steps:

step 410, obtaining at least one MOS parameter set;

step 420, constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout Layout module;

step 430, if at least two MOS modules are laid out according to the mosapray modules to obtain at least two mosapray modules, controlling the at least two mosapray modules to be vertically aligned;

according to some embodiments, at least two MOS modules are laid out, and each MOS module is extended upward in the obtained at least two mosapray, and the corresponding node type information is the second node type information.

Step 440, if an adding instruction for the guard ring is obtained, adding the guard ring to at least two mosapray;

according to some embodiments, when the terminal adds a guard ring for at least two mosapray, the terminal may set every two mosapray as one mosapray group in a vertically aligned arrangement order. Furthermore, the terminal may add a guard ring to each mosapray group.

And 450, constructing a grid third metal layer rectangle, a source electrode third metal layer rectangle and a drain electrode third metal layer rectangle to obtain a circuit layout corresponding to at least two MOS modules.

According to some embodiments, the gate third metal layer rectangle is connected to a mosaroray gate port of each of the at least two mosarorays, the source third metal layer rectangle is connected to a mosaroray source port of each of the at least two mosarorays, and the drain third metal layer rectangle is connected to a mosaroray drain port of each of the at least two mosarorays.

According to some embodiments, when the terminal builds the gate third metal layer rectangle, the terminal may obtain the gate second metal layer rectangle, the source second metal layer rectangle, and the drain second metal layer rectangle for each mosaroray. Further, the terminal may construct a gate third metal layer rectangle connected to gate second metal layer rectangles of all mosapray, a source third metal layer rectangle connected to source second metal layer rectangles of all mosapray, and a drain third metal layer rectangle connected to drain second metal layer rectangles of all mosapray.

In some embodiments, the rectangular directions of the gate second metal layer rectangle, the source second metal layer rectangle, and the drain second metal layer rectangle are perpendicular to the rectangular directions of the gate third metal layer rectangle, the source third metal layer rectangle, and the drain third metal layer rectangle. For example, when the gate, source, and drain second metal layer rectangles are lateral rectangles, the gate, source, and drain third metal layer rectangles are longitudinal rectangles. Alternatively, when the gate second metal layer rectangle, the source second metal layer rectangle, and the drain second metal layer rectangle are longitudinal rectangles, the gate third metal layer rectangle, the source third metal layer rectangle, and the drain third metal layer rectangle are lateral rectangles.

In some embodiments, when the terminal builds the gate third metal layer rectangle, the source third metal layer rectangle, and the drain third metal layer rectangle, the terminal may control the gate third metal layer rectangle, the source third metal layer rectangle, and the drain third metal layer rectangle to be centered in alignment with the circuit layout.

In some embodiments, when the terminal constructs the gate third metal layer rectangle, the source third metal layer rectangle, and the drain third metal layer rectangle, the terminal may set the gate third metal layer rectangle as a gate of the circuit layout, set the source third metal layer rectangle as a source of the circuit layout, and set the drain third metal layer rectangle as a drain of the circuit layout.

In some embodiments, fig. 9 shows a schematic layout diagram of a first circuit layout provided in an embodiment of the present application. As shown in fig. 9, the circuit layout includes two mosapray, each mosapray includes three MOS modules connected in parallel, and each MOS module is extended upward, and the node type information is second node type information. At least two first VIA1 layer rectangles are arranged in the overlapping area of the first metal M1 layer rectangle and the second metal M2 layer rectangle. At least two second VIA2 layer rectangles are arranged in the overlapping area of the second metal M2 layer rectangle and the third metal M3 layer rectangle. But no instruction to add to the guard ring was reached, that is to say no guard ring was added for mosaroray.

In some embodiments, the first VIA1 layer rectangle refers to a rectangle for connecting the first metal M1 layer rectangle and the second metal M2 layer rectangle. The second VIA2 layer rectangle refers to a rectangle for connecting the second metal M2 layer rectangle with the third metal M3 layer rectangle.

In some embodiments, fig. 10 shows a layout diagram of a second type of circuit layout provided in an embodiment of the present application. As shown in fig. 10, the circuit layout includes two mosapray, each mosapray includes three MOS modules connected in parallel, and each MOS module is extended upward, and the node type information is second node type information. Meanwhile, an adding instruction aiming at the guard ring is obtained, and the guard ring is added for MOSArray.

In summary, in the method provided in the embodiments of the present application, a set of MOS parameters of at least one mosfet is obtained; constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout modules; if at least two MOS modules are laid out according to the MOSArray modules to obtain at least two MOSArray modules, controlling the at least two MOSArray modules to be vertically aligned and placed; if an adding instruction aiming at the guard ring is obtained, adding the guard ring for at least two MOSArray; and constructing a grid third metal layer rectangle, a source electrode third metal layer rectangle and a drain electrode third metal layer rectangle to obtain a circuit layout corresponding to at least two MOS modules. Therefore, by adopting the MOSLayout module to construct the MOS module and adopting the MOSArray module to layout the MOS module, the layout cost and error rate of the MOSFET can be reduced, the layout efficiency of the MOSFET can be improved, and the layout standard of the MOSFET in the layout process can be unified.

In order to implement the above embodiment, the present application also proposes an automatic layout device for a MOSFET.

As shown in fig. 11, an automatic layout device of a MOSFET includes:

a set acquisition unit 1110 for acquiring at least one MOS parameter set of the mosfet;

the module construction unit 1120 is configured to construct at least two MOS modules based on at least one MOS parameter set according to the MOS Layout module;

and the module layout unit 1130 is configured to layout at least two MOS modules according to the MOS Array module, so as to obtain circuit layouts corresponding to the at least two MOS modules.

In summary, in the device provided in the embodiments of the present application, at least one MOS parameter set of the mosfet is obtained by the set obtaining unit; the module construction unit constructs at least two MOS modules based on at least one MOS parameter set according to the MOS Layout Layout modules; and the module layout unit performs layout on at least two MOS modules according to the MOS Array modules so as to obtain circuit layouts corresponding to the at least two MOS modules. Therefore, by adopting the MOSLayout module to construct the MOS module and adopting the MOSArray module to layout the MOS module, the layout cost and error rate of the MOSFET can be reduced, the layout efficiency of the MOSFET can be improved, and the layout standard of the MOSFET in the layout process can be unified.

It should be noted that in the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present application.

It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.

Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.

The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives, and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.

Claims

1. An automatic layout method of a MOSFET, comprising:

constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout modules;

according to the MOS Array modules, the at least two MOS modules are laid out to obtain circuit layouts corresponding to the at least two MOS modules;

the MOS parameter set includes a drain node parameter, a gate node parameter, a source node parameter, a drain source offset parameter, a drain source spacing parameter, and a via layer minimum width parameter, the via layer corresponding to the via layer minimum width parameter is used for connecting a first metal layer and a second metal layer, and the at least two MOS modules are constructed based on the at least one MOS parameter set according to MOS Layout, and the MOS parameter set includes:

constructing an MOS module according to the drain electrode rectangle, the source electrode rectangle, the grid electrode rectangle and the third active region layer rectangle;

The MOS parameter set further includes a length parameter, and the constructing a MOS module according to the drain rectangle, the source rectangle, the gate rectangle, and the third active region layer rectangle includes:

2. The method of claim 1, wherein the set of MOS parameters further comprises a length parameter, a width parameter, and a first metal layer minimum pitch parameter; wherein,,

3. The method of claim 1, wherein the laying out the at least two MOS modules according to a MOS Array module comprises:

ports of the at least two MOS modules after being placed are constructed;

4. The method of claim 3, wherein the ports comprise a mosarory source port, a mosarory drain port, and a mosarory gate port, the ports of the at least two MOS modules after the build and place comprising:

if a construction instruction aiming at the third first metal layer rectangle is obtained, expanding the at least two MOS modules based on the expansion direction parameter, and constructing a third first metal layer rectangle so as to control the at least two MOS modules to be connected to the same node;

Determining the port based on node type information;

5. The method of claim 4, wherein the node type information comprises first node type information and second node type information, the determining the port based on the node type information comprising:

6. The method of claim 3, wherein the layout of the at least two MOS modules according to the MOS Array module to obtain circuit layouts corresponding to the at least two MOS modules further comprises:

7. The method of claim 6, further comprising, after said controlling said at least two mosaroray vertically aligned positions:

8. An automatic layout apparatus for a MOSFET, comprising:

the module construction unit is used for constructing at least two MOS modules based on at least one MOS parameter set according to MOS Layout Layout modules;

the module layout unit is used for carrying out layout on the at least two MOS modules according to the MOS Array module so as to obtain circuit layouts corresponding to the at least two MOS modules;