CN114943200A

CN114943200A - Automatic layout method and device of MOSFET

Info

Publication number: CN114943200A
Application number: CN202210587410.5A
Authority: CN
Inventors: 叶佐昌; 王燕; 郝晶磊
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2022-05-26
Filing date: 2022-05-26
Publication date: 2022-08-26
Anticipated expiration: 2042-05-26
Also published as: CN114943200B

Abstract

The present disclosure relates to the field of integrated circuit technologies, and in particular, to an automatic layout method and apparatus for MOSFETs. The automatic layout method of the MOSFET comprises the following steps: acquiring at least one metal oxide semiconductor field effect transistor (MOS) parameter set; constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout module; and according to the MOS Array modules, at least two MOS modules are arranged to obtain circuit layouts corresponding to the at least two MOS modules. By adopting the scheme, the layout cost and the error rate of the MOSFET can be reduced, the layout efficiency of the MOSFET is improved, and the placement standard during the layout of the MOSFET is unified.

Description

Automatic layout method and device of MOSFET

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to an automatic layout method and apparatus for MOSFETs.

Background

Integrated Circuits (ICs) are miniature electronic devices or components with specific functions that integrate a certain number of commonly used electronic components, such as resistors, capacitors, transistors, etc., and the interconnections between these components, through semiconductor processes. Therefore, the integrated circuit has the advantages of small volume, light weight, few pins, long service life, high reliability, low cost, good performance and the like, and is convenient for large-scale production.

With the rapid development of integrated circuits, the number of Metal-Oxide-Semiconductor Field-Effect transistors (MOSFETs, MOS) included in a single chip is increasing. However, in the related art, the MOSFET layout needs to be manually performed in the design process of the analog circuit in the chip. However, the manual MOSFET layout requires high requirements for operators, and requires the operators to understand a lot of layout knowledge, which results in high layout cost. Meanwhile, the connection of each MOSFET needs to be controlled manually, so that the efficiency is low and the error rate is high. In addition, the placement standards adopted when the MOSFET layout is manually performed are individualized, and layouts obtained by different operators are different under the condition of realizing the same function.

Disclosure of Invention

The present application is directed to solving, at least to some extent, one of the technical problems in the related art.

Therefore, a first objective of the present application is to provide an automatic layout method for MOSFETs, so as to reduce the layout cost and error rate of MOSFETs, improve the layout efficiency of MOSFETs, and unify the placement standards when MOSFETs are laid out.

A second object of the present application is to provide an automatic layout apparatus of MOSFETs.

In order to achieve the above object, an embodiment of the first aspect of the present application provides an automatic layout method of a MOSFET, including:

acquiring at least one metal oxide semiconductor field effect transistor (MOS) parameter set;

constructing at least two MOS modules based on the at least one MOS parameter set according to the MOS Layout module;

and according to the MOS Array modules, the at least two MOS modules are arranged to obtain circuit layouts corresponding to the at least two MOS modules.

Optionally, in an embodiment of the present application, the MOS parameter sets include a drain node parameter, a gate node parameter, a source node parameter, a drain-source offset parameter, a drain-source spacing parameter, and a via layer minimum width parameter, where a via layer corresponding to the via layer minimum parameter is used to connect the first metal layer and the second metal layer, and the building at least two MOS modules according to the MOS Layout module based on the at least one MOS parameter set includes:

generating a drain node, a gate node and a source node based on the drain node parameter, the gate node parameter and the source node parameter;

constructing a drain electrode rectangle, wherein the drain electrode rectangle comprises a first active region layer rectangle and a first metal layer rectangle which are the same in size, the first active region layer rectangle and the first metal layer rectangle are connected to the drain electrode node, and the first metal layer rectangle is a source electrode port of the MOS module;

constructing a source electrode rectangle, wherein the source electrode rectangle comprises a second active region layer rectangle and a second first metal layer rectangle which are the same in size, the second active region layer rectangle and the second first metal layer rectangle are both connected to the source electrode node, and the second first metal layer rectangle is a drain electrode port of the MOS module;

constructing a grid rectangle which is a polysilicon layer rectangle connected to the grid node and is a grid port of the MOS module;

constructing a third active region layer rectangle according to the drain-source offset parameter, the drain-source spacing parameter and the minimum width parameter of the via hole layer;

and determining the MOS module according to the drain electrode rectangle, the source electrode rectangle, the grid electrode rectangle and the third active region layer rectangle.

Optionally, in an embodiment of the present application, the MOS parameter set further includes a length parameter, a width parameter, and a first metal layer minimum spacing parameter; wherein the content of the first and second substances,

the length of the first active region layer rectangle, the length of the first metal layer rectangle, the length of the second active region layer rectangle and the length of the second first metal layer rectangle are parameters of the minimum width of the via hole layer;

the width of the first active region layer rectangle, the width of the first metal layer rectangle, the width of the second active region layer rectangle and the width of the second first metal layer rectangle are the width parameters;

the length of the polysilicon layer rectangle is the length parameter, and the width of the polysilicon layer rectangle is determined by the minimum spacing parameter of the first metal layer and the width parameter.

Optionally, in an embodiment of the present application, the MOS parameter set further includes a length parameter, and the constructing a MOS module according to the drain rectangle, the source rectangle, the gate rectangle, and the third active region layer rectangle includes:

controlling the drain rectangle and the source rectangle to be horizontally aligned to obtain a drain-source rectangle, wherein the distance between the drain rectangle and the source rectangle is determined by the length parameter and the drain-source distance parameter;

and controlling the third active region layer rectangle, the drain source rectangle and the gate rectangle to be aligned in the middle to obtain the MOS module.

Optionally, in an embodiment of the application, the laying out the at least two MOS modules according to a MOS Array module includes:

controlling the at least two MOS modules to be horizontally aligned and placed, and controlling the at least two MOS modules to be placed in parallel;

constructing ports of the at least two placed MOS modules;

determining the MOS type of each of the at least two MOS modules based on the module parameter information set;

and controlling the at least two MOS modules to be converted into MOS modules corresponding to the MOS type so as to obtain the MOSArray.

Optionally, in an embodiment of the present application, the ports include a MOSArray source port, a MOSArray drain port, and a MOSArray gate port, and the building the placed ports of the at least two MOS modules includes:

if a construction instruction for the third first metal layer rectangle is obtained, expanding the at least two MOS modules based on the expansion direction parameter, and constructing the at least two third first metal layer rectangles to control the at least two MOS modules to be connected to the same node;

determining the port based on node type information;

if no build instructions for the third first metal layer rectangle are obtained, setting a source port, a drain port, and a gate port of each of the at least two MOS modules to be the MOSArray source port, the MOSArray drain port, and the MOSArray gate port.

Optionally, in an embodiment of the present application, the node type information includes first node type information and second node type information, and the determining the port based on the node type information includes:

if the node type information is first node type information, setting the third first metal layer rectangle as the MOSArray gate port, and setting a source port and a drain port of each of the at least two MOS modules as the MOSArray source port and the MOSArray drain port;

if the node type information is second node type information, constructing a grid second metal layer rectangle, a source second metal layer rectangle and a drain second metal layer rectangle, wherein the grid second metal layer rectangle is connected to the grid port of each of the at least two MOS modules, the source second metal layer rectangle is connected to the source port of each of the at least two MOS modules, and the drain second metal layer rectangle and the third first metal layer rectangle are connected to the same node;

setting the gate second metal layer rectangle to the MOSArray gate port, the source second metal layer rectangle to the MOSArray source port, and the drain second metal layer rectangle to the MOSArray drain port.

Optionally, in an embodiment of the present application, the laying out the at least two MOS modules according to an MOS Array module to obtain a circuit layout corresponding to the at least two MOS modules further includes:

if the at least two MOS modules are distributed according to the MOSArray modules to obtain at least two MOSArray modules, controlling the at least two MOSArray modules to be vertically aligned;

constructing a gate third metal layer rectangle connected to the MOSArray gate port of each of the at least two mosarrays, a source third metal layer rectangle connected to the MOSArray source port of each of the at least two mosarrays, and a drain third metal layer rectangle connected to the MOSArray drain port of each of the at least two mosarrays, to obtain circuit layouts corresponding to the at least two MOS modules;

and setting the grid third metal layer rectangle as the grid of the circuit layout, setting the source third metal layer rectangle as the source of the circuit layout, and setting the drain third metal layer rectangle as the drain of the circuit layout.

Optionally, in an embodiment of the present application, after the controlling the at least two mosarrray vertically aligned positions, the method further includes:

if an add instruction for a guard ring guard is fetched, the guard ring guard is added for the at least two mosarrays.

In summary, in the method provided in the embodiment of the present application, at least one MOS parameter set of a mosfet is obtained; constructing at least two MOS modules based on the at least one MOS parameter set according to the MOS Layout module; and according to the MOS Array modules, the at least two MOS modules are arranged to obtain circuit layouts corresponding to the at least two MOS modules. Therefore, the MOS module is constructed by the MOSLayout module, and the MOS module is distributed by the MOSArray module, so that the distribution cost and the error rate of the MOSFET can be reduced, the distribution efficiency of the MOSFET can be improved, and the placement standard in the MOSFET distribution can be unified.

In order to achieve the above object, an automatic layout apparatus for MOSFETs according to an embodiment of the second aspect of the present application includes:

the device comprises a set acquisition unit, a parameter setting unit and a parameter setting unit, wherein the set acquisition unit is used for acquiring at least one metal oxide semiconductor field effect transistor (MOS) parameter set;

the module construction unit is used for constructing at least two MOS modules based on the at least one MOS parameter set according to the MOS Layout module;

and the module layout unit is used for laying out the at least two MOS modules according to the MOS Array modules so as to obtain the circuit layouts corresponding to the at least two MOS modules.

In summary, in the apparatus provided in the embodiment of the present application, at least one MOS parameter set of a mosfet is obtained through a set obtaining unit; the module construction unit constructs at least two MOS modules based on the at least one MOS parameter set according to the MOS Layout module; and the module layout unit is used for laying out the at least two MOS modules according to the MOS Array module so as to obtain the circuit layouts corresponding to the at least two MOS modules. Therefore, the MOS module is constructed by the MOSLayout module, and the MOS module is distributed by the MOSArray module, so that the distribution cost and the error rate of the MOSFET can be reduced, the distribution efficiency of the MOSFET can be improved, and the placement standard in the MOSFET distribution can be unified.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic flowchart illustrating a first method for automatically laying out MOSFETs according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart illustrating a second automatic layout method of MOSFETs according to an embodiment of the present application;

fig. 3 illustrates a layout diagram of a MOS module provided in an embodiment of the present application;

fig. 4 is a schematic flow chart illustrating an automatic layout method of a third MOSFET according to an embodiment of the present application;

fig. 5 shows a layout diagram of a first MOSArray provided in an embodiment of the present application;

fig. 6 illustrates a layout diagram of a second MOSArray provided in an embodiment of the present application;

fig. 7 shows a layout diagram of a second MOSArray provided in an embodiment of the present application;

fig. 8 is a schematic flow chart illustrating a fourth method for automatically laying out MOSFETs according to an embodiment of the present disclosure;

fig. 9 shows a layout schematic diagram of a first circuit layout provided in an embodiment of the present application;

fig. 10 illustrates a layout diagram of a second circuit layout provided in the embodiment of the present application;

fig. 11 is a schematic structural diagram of an automatic layout apparatus for MOSFETs according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application. On the contrary, the embodiments of the application include all changes, modifications and equivalents coming within the spirit and terms of the claims appended hereto.

The present application will be described in detail with reference to specific examples.

Fig. 1 shows a schematic flow chart of a first automatic layout method for MOSFETs according to an embodiment of the present application, which may be implemented by relying on a computer program and may be run on an apparatus for performing automatic layout of MOSFETs. The computer program may be integrated into the application or may run as a separate tool-like application.

Wherein, the automatic layout device of the MOSFET may be a terminal having an automatic layout function of the MOSFET, the terminal including but not limited to: wearable devices, handheld devices, personal computers, tablet computers, in-vehicle devices, smart phones, computing devices or other processing devices connected to a wireless modem, and the like. Terminals can be called different names in different networks, for example: user equipment, access terminal, subscriber unit, subscriber station, Mobile station, remote terminal, Mobile device, user terminal, wireless Communication device, user agent or user equipment, cellular telephone, cordless telephone, Personal Digital Assistant (PDA), fifth Generation Mobile Communication Technology (5G) network, the 4th Generation Mobile Communication Technology (4G) network, a terminal in a 3rd-Generation, 3G or future evolution network, and the like.

Specifically, the automatic layout method of the MOSFET comprises the following steps:

step 110, obtaining at least one metal oxide semiconductor field effect transistor (MOS) parameter set;

according to some embodiments, the MOS parameters refer to parameters that the terminal needs to use when building the MOS module. The MOS parameter does not refer to a fixed parameter. The MOS parameters include, but are not limited to, a MOS module number parameter, a drain node parameter, a gate node parameter, a source node parameter, a drain-source offset parameter, a drain-source spacing parameter, a length parameter, a width parameter, a via layer minimum width parameter, and a first metal layer M1 minimum spacing parameter, an extension direction parameter, a via number parameter, a module type parameter, and the like.

In some embodiments, a VIA1 layer corresponding to the VIA layer minimum width parameter and the VIA number parameter is used to connect the first metal M1 layer and the second metal M2 layer.

In some embodiments, a MOS parameter set refers to a set aggregated by at least one MOS parameter. The MOS parameter set does not refer to a fixed set. For example, when the number of MOS parameters changes, the set of MOS parameters may change. When the content of a MOS parameter changes, the set of MOS parameters may also change.

It is easy to understand that when the terminal performs automatic layout of the MOSFET, the terminal can acquire at least one MOS parameter set.

Step 120, constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout modules;

according to some embodiments, the MOSLayout module refers to a module employed when the terminal constructs a MOS module.

In some embodiments, the MOS module refers to a module corresponding to a single MOSFET layout that is constructed by the terminal according to the MOS parameter set.

In some embodiments, the MOSLayout module may construct a number of MOS modules corresponding to the number parameter of MOS modules in the MOS parameter set according to the MOS parameter set.

It is easy to understand that when the terminal acquires the at least one MOS parameter set, the terminal may construct at least two MOS modules based on the at least one MOS parameter set according to the MOS Layout module.

And step 130, according to the MOS Array modules, arranging at least two MOS modules to obtain circuit layouts corresponding to the at least two MOS modules.

According to some embodiments, the MOSArray module refers to a module employed when the terminal lays out at least two MOS modules.

It is easy to understand that, when the terminal constructs at least two MOS modules, the terminal may lay out the at least two MOS modules according to the MOS Array module to obtain the circuit layouts corresponding to the at least two MOS modules.

In summary, the method provided by the embodiment of the present application obtains at least one MOS parameter set of a mosfet; constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout module; and according to the MOS Array modules, at least two MOS modules are arranged to obtain circuit layouts corresponding to the at least two MOS modules. Therefore, the MOS module is constructed by the MOSLayout module, and the MOS module is distributed by the MOSArray module, so that the distribution cost and the error rate of the MOSFET can be reduced, the distribution efficiency of the MOSFET can be improved, and the placement standard in the MOSFET distribution can be unified.

Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a second automatic layout method of MOSFETs according to an embodiment of the present disclosure. Specifically, the automatic layout method of the MOSFET comprises the following steps:

step 210, obtaining at least one metal oxide semiconductor field effect transistor (MOS) parameter set;

according to some embodiments, when the terminal acquires the at least one MOS parameter set, the terminal may acquire the at least one MOS parameter set by means of parameter delivery.

Step 220, generating a drain node, a gate node and a source node based on the drain node parameter, the gate node parameter and the source node parameter;

step 230, constructing a drain rectangle, wherein the drain rectangle comprises a first active region layer rectangle and a first metal layer rectangle which are the same in size, the first active region layer rectangle and the first metal layer rectangle are connected to a drain node, and the first metal layer rectangle is a source electrode port of the MOS module;

according to some embodiments, the length of the first active region layer rectangle and the length of the first metal layer rectangle are parameters of the minimum width of the via hole layer. The width of the first active region layer rectangle and the width of the first metal layer rectangle are width parameters.

In some embodiments, when the terminal forms a drain rectangle, the terminal may control the first active region layer rectangle and the first metal layer rectangle to be placed in lower left corner alignment.

Step 240, constructing a source rectangle, wherein the source rectangle comprises a second active region layer rectangle and a second first metal layer rectangle which are the same in size, the second active region layer rectangle and the second first metal layer rectangle are both connected to a source node, and the second first metal layer rectangle is a drain port of the MOS module;

according to some embodiments, a length of the second active region layer rectangle and a length of the second first metal layer rectangle are via layer minimum width parameters. The width of the second active region layer rectangle and the width of the second first metal layer rectangle are width parameters.

In some embodiments, when the terminal forms a drain rectangle, the terminal may control the second active region layer rectangle and the second first metal layer rectangle to be placed in lower left corner alignment.

Step 250, constructing a grid rectangle, wherein the grid rectangle is a polysilicon layer rectangle, the polysilicon layer rectangle is connected to a grid node, and the polysilicon layer rectangle is a grid port of the MOS module;

according to some embodiments, the length of the rectangle of polysilicon layer is a length parameter, and the width of the rectangle of polysilicon layer is determined by a first metal layer minimum spacing parameter and a width parameter.

In some embodiments, the width of the polysilicon layer rectangle may be determined according to the following equation:

M1.min_spacing*2+w

wherein, m1.min _ spacing is the minimum spacing parameter of the first metal layer, and w is the width parameter.

Step 260, constructing a third active region layer rectangle according to the drain-source offset parameter, the drain-source spacing parameter and the minimum width parameter of the via hole layer;

according to some embodiments, the length of the third active region layer rectangle may be determined according to the following equation:

2*ds_l+2*ds_spacing+ds_offset

wherein ds _ l is a via layer minimum width parameter, ds _ spacing is a drain-source spacing parameter, and ds _ offset is a drain-source offset parameter.

Step 270, determining an MOS module according to the drain electrode rectangle, the source electrode rectangle, the grid electrode rectangle and the third active region layer rectangle;

according to some embodiments, fig. 3 illustrates a layout diagram of a MOS module provided in an embodiment of the present application. As shown in fig. 3, when the terminal determines the MOS module according to the drain rectangle, the source rectangle, the gate rectangle, and the third active region layer rectangle, the terminal may control the drain rectangle and the source rectangle to be horizontally aligned to obtain the drain-source rectangle. Furthermore, the terminal may control the third active region layer rectangle, the drain source rectangle, and the gate rectangle to be aligned in the center to obtain the MOS module.

In some embodiments, as shown in fig. 3, the gate rectangle is a polysilicon PO layer rectangle, and the drain rectangle and the source rectangle each include two active area AA layer rectangles of the same size and a first metal M1 layer rectangle. Wherein the active area AA layer rectangle is located below the first metal M1 layer rectangle.

In some embodiments, as shown in fig. 3, the third active area AA layer rectangle is located below the polysilicon PO layer rectangle and in the middle of the drain rectangle and the source rectangle.

In some embodiments, the spacing between the drain rectangle and the source rectangle is determined by a length parameter and a drain-source spacing parameter.

In some embodiments, the spacing between the drain rectangle and the source rectangle may be determined according to:

2*ds_spacing+l

wherein ds _ spacing is a drain-source spacing parameter.

According to some embodiments, when the terminal determines the MOS module according to the drain rectangle, the source rectangle, the gate rectangle, and the third active region layer rectangle, the terminal may further generate MOSFET netlist information corresponding to the MOS module.

According to some embodiments, when the terminal constructs the MOS module, if the terminal acquires the module type parameter from the module parameter information set, the terminal may control the module type of the MOS module to be converted into the MOS type corresponding to the module type parameter;

in some embodiments, when the module type parameter is PMOS, the termination may construct an N-well layer rectangle and a P + layer rectangle covering the entire MOS module to obtain a PMOS module.

In some embodiments, when the module type parameter is NMOS, the terminal may construct an N + layer rectangle covering the entire MOS module to obtain an NMOS module.

And 280, laying out at least two MOS modules according to the MOS Array modules to obtain circuit layouts corresponding to the at least two MOS modules.

In summary, the method provided by the embodiment of the present application obtains at least one MOS parameter set of a mosfet; generating a drain node, a gate node and a source node based on the drain node parameter, the gate node parameter and the source node parameter; constructing a drain electrode rectangle, wherein the drain electrode rectangle comprises a first active region layer rectangle and a first metal layer rectangle which are the same in size, the first active region layer rectangle and the first metal layer rectangle are connected to a drain electrode node, and the first metal layer rectangle is a source electrode port of the MOS module; constructing a source electrode rectangle, wherein the source electrode rectangle comprises a second active region layer rectangle and a second first metal layer rectangle which are the same in size, the second active region layer rectangle and the second first metal layer rectangle are both connected to a source electrode node, and the second first metal layer rectangle is a drain electrode port of the MOS module; constructing a grid rectangle, wherein the grid rectangle is a polysilicon layer rectangle which is connected to a grid node and is a grid port of the MOS module; constructing a third active region layer rectangle according to the drain-source electrode offset parameter, the drain-source electrode spacing parameter and the minimum width parameter of the via hole layer; determining an MOS module according to the drain electrode rectangle, the source electrode rectangle, the grid electrode rectangle and the third active region layer rectangle; and according to the MOS Array modules, at least two MOS modules are arranged to obtain circuit layouts corresponding to the at least two MOS modules. Therefore, the MOS module is constructed by the MOSLayout module, and the MOS module is distributed by the MOSArray module, so that the distribution cost and the error rate of the MOSFET can be reduced, the distribution efficiency of the MOSFET can be improved, and the placement standard in the MOSFET distribution can be unified.

Referring to fig. 4, fig. 4 is a flow chart illustrating a third automatic layout method of MOSFETs according to an embodiment of the present application. Specifically, the automatic layout method of the MOSFET comprises the following steps:

step 310, acquiring at least one metal oxide semiconductor field effect transistor (MOS) parameter set;

step 320, constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout modules;

step 330, controlling at least two MOS modules to be horizontally aligned and placed, and controlling at least two MOS modules to be placed in parallel;

according to some embodiments, when the terminal controls at least two MOS modules to be placed in parallel, the terminal may label the at least two MOS modules in the placing order, and turn the MOS module with the even label left and right. And then controlling the at least two MOS modules to be partially overlapped. The overlapped parts are a source electrode rectangle and a drain electrode rectangle of the MOS module.

Step 340, constructing ports of at least two placed MOS modules;

according to some embodiments, the ports of the at least two MOS modules after placement include a MOSArray source port, a MOSArray drain port, and a MOSArray gate port.

According to some embodiments, when the terminal constructs the ports of the at least two placed MOS modules, if the terminal obtains a construct instruction for a third first metal layer rectangle, the terminal may expand the at least two MOS modules based on the expansion direction parameter and construct a third first metal layer rectangle to control the at least two MOS modules to be connected to the same node. Furthermore, the terminal can determine the ports of the at least two placed MOS modules based on the node type information;

in some embodiments, the expansion direction parameter includes an upward expansion parameter and a downward expansion parameter. When the extension direction parameter is an upward extension parameter, the terminal may perform upward extension on at least two MOS modules. When the extension direction parameter is a downward extension parameter, the terminal may extend at least two MOS modules downward.

In some embodiments, when the terminal may extend the at least two MOS modules based on the extension direction parameter, the terminal may extend the polysilicon layer rectangle of each of the at least two MOS modules, and further, the terminal may construct a third first metal layer rectangle connecting all the extended polysilicon layer rectangles.

In some embodiments, the node type information includes first node type information and second node type information.

In some embodiments, if the node type information is the first node type information, the terminal may set the third first metal layer rectangle as a MOSArray gate port, and set the source port and the drain port of each of the at least two MOS modules as a MOSArray source port and a MOSArray drain port;

in some embodiments, if the node type information is the second node type information, the terminal may construct a gate second metal layer rectangle, a source second metal layer rectangle, and a drain second metal layer rectangle. The grid second metal layer rectangle is connected to the grid port of each of the at least two MOS modules, the source second metal layer rectangle is connected to the source port of each of the at least two MOS modules, and the drain second metal layer rectangle and the third first metal layer rectangle are connected to the same node. Further, the termination may set the gate second metal layer rectangle to the MOSArray gate port, the source second metal layer rectangle to the MOSArray source port, and the drain second metal layer rectangle to the MOSArray drain port.

In some embodiments, when the terminal constructs the source second metal layer rectangle and the drain second metal layer rectangle, the terminal may obtain the first metal layer rectangle and the second first metal layer rectangle for each of the at least two MOS modules. Further, the terminal may construct a drain second metal layer rectangle connecting all first metal layer rectangles, and a source second metal layer rectangle connecting all second first metal layer rectangles.

In some embodiments, when the terminal builds the gate second metal layer rectangle, the terminal may obtain a built third first metal layer rectangle. Furthermore, the terminal can construct a gate second metal layer rectangle with the same size as the third first metal layer rectangle, and control the gate second metal layer rectangle and the third first metal layer rectangle to be connected to the same node.

In some embodiments, the width of the gate second metal layer rectangle, the width of the source second metal layer rectangle, and the width of the drain second metal layer rectangle are determined by the number of vias parameter.

According to some embodiments, when the terminal constructs the ports of the placed at least two MOS modules, if the terminal does not obtain the construction instruction for the third first metal layer rectangle, the terminal may set the source port, the drain port, and the gate port of each of the at least two MOS modules to be the MOSArray source port, the MOSArray drain port, and the MOSArray gate port.

Step 350, determining the MOS type of each of at least two MOS modules based on the module parameter information set;

according to some embodiments, the module type parameters include a PMOS type and an NMOS type.

And step 360, controlling at least two MOS modules to be converted into MOS modules corresponding to the MOS types so as to obtain the MOSArray.

According to some embodiments, when the module type parameter is PMOS, the termination may construct an N-well layer rectangle and a P + layer rectangle covering the entire MOSArray.

In some embodiments, when the module type parameter corresponding to the MOS module is NMOS, the termination may construct an N + layer rectangle covering the entire MOSArray.

In some embodiments, fig. 5 illustrates a layout diagram of a first MOSArray provided in an embodiment of the present application. As shown in fig. 5, the MOSArray includes three MOS modules connected in parallel, and the three MOS modules are not expanded.

In some embodiments, fig. 6 illustrates a layout diagram of a second MOSArray provided in an embodiment of the present application. As shown in fig. 6, the MOSArray includes three MOS modules connected in parallel, and the three MOS modules are expanded upward, but the node type information is the first node type information, that is, only one third first metal M1 layer rectangle is constructed to connect all expanded polysilicon PO layer rectangles.

In some embodiments, fig. 7 illustrates a layout diagram of a second MOSArray provided in an embodiment of the present application. As shown in fig. 7, the MOSArray includes three MOS modules connected in parallel and expands the three MOS modules upward, but the node type information is second node type information, that is, on the basis of fig. 6, three second metal M2 layer rectangles are constructed, wherein one second metal M2 layer rectangle is located above and has the same size as the third first metal M1 layer rectangle, one second metal M2 layer rectangle is connected to the gate port of each MOS module, and one second metal M2 layer rectangle is connected to the source port of each MOS module.

In summary, the method provided by the embodiment of the present application obtains at least one MOS parameter set of a mosfet; constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout module; controlling at least two MOS modules to be horizontally aligned and placed, and controlling at least two MOS modules to be placed in parallel; constructing ports of at least two placed MOS modules; determining the MOS type of each of at least two MOS modules based on the module parameter information set; and controlling at least two MOS modules to be converted into MOS modules corresponding to the MOS type so as to obtain the MOSArray. Therefore, the MOS module is constructed by the MOSLayout module, and the MOS module is arranged by the MOSArray module, so that the arrangement cost and the error rate of the MOSFET can be reduced, the arrangement efficiency of the MOSFET can be improved, and the arrangement standard of the MOSFET in arrangement can be unified.

Referring to fig. 8, fig. 8 is a schematic flowchart illustrating an automatic layout method of a fourth MOSFET according to an embodiment of the present application. Specifically, the automatic layout method of the MOSFET comprises the following steps:

step 410, obtaining at least one metal oxide semiconductor field effect transistor (MOS) parameter set;

step 420, constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout modules;

step 430, if at least two MOS modules are arranged according to the MOSArray modules to obtain at least two MOSArray modules, controlling the at least two MOSArray modules to be vertically aligned;

according to some embodiments, at least two MOS modules are laid out, and of the at least two mosarrays obtained, each MOSArray extends upward for each MOS module, and the corresponding node type information is the second node type information.

Step 440, if an adding instruction for guard ring guiding is acquired, the guiding is added for at least two mossarray;

according to some embodiments, when the terminal adds a guard dring for at least two mosarrays, the terminal may set every two mosarrays into one MOSArray group in a vertically aligned placing order. Further, the terminal may add a guard to each MOSArray group.

And step 450, constructing a grid third metal layer rectangle, a source third metal layer rectangle and a drain third metal layer rectangle to obtain a circuit layout corresponding to at least two MOS modules.

According to some embodiments, the gate third metal layer is rectangularly connected to the MOSArray gate port of each of the at least two mosarrays, the source third metal layer is rectangularly connected to the MOSArray source port of each of the at least two mosarrays, and the drain third metal layer is rectangularly connected to the MOSArray drain port of each of the at least two mosarrays.

According to some embodiments, when the terminal constructs the gate third metal layer rectangle, the terminal may obtain the gate second metal layer rectangle, the source second metal layer rectangle, and the drain second metal layer rectangle for each mosarry. Further, the termination may construct a gate third metal layer rectangle connected to all of the MOSArray's gate second metal layer rectangles, a source third metal layer rectangle connected to all of the MOSArray's source second metal layer rectangles, and a drain third metal layer rectangle connected to all of the MOSArray's drain second metal layer rectangles.

In some embodiments, the rectangular directions of the gate second metal layer rectangle, the source second metal layer rectangle, and the drain second metal layer rectangle are perpendicular to the rectangular directions of the gate third metal layer rectangle, the source third metal layer rectangle, and the drain third metal layer rectangle. For example, when the gate second metal layer rectangle, the source second metal layer rectangle, and the drain second metal layer rectangle are horizontal rectangles, the gate third metal layer rectangle, the source third metal layer rectangle, and the drain third metal layer rectangle are vertical rectangles. Or when the gate second metal layer rectangle, the source second metal layer rectangle and the drain second metal layer rectangle are longitudinal rectangles, the gate third metal layer rectangle, the source third metal layer rectangle and the drain third metal layer rectangle are transverse rectangles.

In some embodiments, when the terminal implements the gate third metal layer rectangle, the source third metal layer rectangle, and the drain third metal layer rectangle, the terminal may control the gate third metal layer rectangle, the source third metal layer rectangle, and the drain third metal layer rectangle to be centered with the circuit layout.

In some embodiments, when the terminal constructs the gate third metal layer rectangle, the source third metal layer rectangle, and the drain third metal layer rectangle, the terminal may set the gate third metal layer rectangle to be the gate of the circuit layout, the source third metal layer rectangle to be the source of the circuit layout, and the drain third metal layer rectangle to be the drain of the circuit layout.

In some embodiments, fig. 9 shows a layout diagram of a first circuit layout provided in an embodiment of the present application. As shown in fig. 9, the circuit layout includes two mosarrays, each MOSArray includes three MOS modules connected in parallel, and each MOS module is extended upward, and the node type information is the second node type information. At least two rectangles of the first VIA hole VIA1 are arranged in the overlapping area of the rectangle of the first metal M1 layer and the rectangle of the second metal M2 layer. At least two second VIA hole VIA2 layer rectangles are arranged in the overlapping region of the second metal M2 layer rectangle and the third metal M3 layer rectangle. But not to the add instruction for the guardling, that is to say no guardling is added for MOSArray.

In some embodiments, the first VIA1 layer rectangle refers to a rectangle used to connect the first metal M1 layer rectangle and the second metal M2 layer rectangle. The second VIA2 layer rectangle refers to a rectangle used to connect the second metal M2 layer rectangle with the third metal M3 layer rectangle.

In some embodiments, fig. 10 shows a layout diagram of a second circuit layout provided in the embodiments of the present application. As shown in fig. 10, the circuit layout includes two mosarrays, each MOSArray includes three MOS modules connected in parallel, and each MOS module is extended upward, and the node type information is the second node type information. Meanwhile, an adding instruction for guardring is obtained, and the guardring is added to the MOSArray.

In summary, in the method provided in the embodiment of the present application, at least one MOS parameter set of a mosfet is obtained; constructing at least two MOS modules based on at least one MOS parameter set according to the MOS Layout module; if at least two MOS modules are arranged according to the MOSArray modules to obtain at least two MOSArray modules, controlling the at least two MOSArray modules to be vertically aligned; if an adding instruction aiming at the guard ring guard is acquired, the guard ring guard is added for at least two MOSArray; and constructing a grid third metal layer rectangle, a source third metal layer rectangle and a drain third metal layer rectangle to obtain a circuit layout corresponding to at least two MOS modules. Therefore, the MOS module is constructed by the MOSLayout module, and the MOS module is distributed by the MOSArray module, so that the distribution cost and the error rate of the MOSFET can be reduced, the distribution efficiency of the MOSFET can be improved, and the placement standard in the MOSFET distribution can be unified.

In order to implement the above embodiments, the present application further provides an automatic layout apparatus for MOSFETs.

As shown in fig. 11, an automatic layout apparatus of a MOSFET includes:

a set obtaining unit 1110, configured to obtain at least one MOS parameter set of a mosfet;

a module building unit 1120, configured to build at least two MOS modules based on at least one MOS parameter set according to the MOS Layout module;

the module layout unit 1130 is configured to layout at least two MOS modules according to the MOS Array module to obtain a circuit layout corresponding to the at least two MOS modules.

In summary, in the apparatus provided in the embodiment of the present application, at least one MOS parameter set of a mosfet is obtained by a set obtaining unit; the module construction unit constructs at least two MOS modules based on at least one MOS parameter set according to the MOS Layout modules; the module layout unit is used for laying out the at least two MOS modules according to the MOS Array modules so as to obtain circuit layouts corresponding to the at least two MOS modules. Therefore, the MOS module is constructed by the MOSLayout module, and the MOS module is distributed by the MOSArray module, so that the distribution cost and the error rate of the MOSFET can be reduced, the distribution efficiency of the MOSFET can be improved, and the placement standard in the MOSFET distribution can be unified.

It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present application, "a plurality" means two or more unless otherwise specified.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present application includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.

It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.

In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims

1. An automatic layout method of a MOSFET, comprising:

2. The method of claim 1, wherein the set of MOS parameters comprises a drain node parameter, a gate node parameter, a source node parameter, a drain-source offset parameter, a drain-source spacing parameter, and a via layer minimum width parameter, the via layer corresponding to the via layer minimum parameter for connecting a first metal layer and a second metal layer, the constructing at least two MOS modules based on the at least one set of MOS parameters according to a MOS Layout module comprising:

3. The method of claim 2, wherein the set of MOS parameters further includes a length parameter, a width parameter, and a first metal layer minimum spacing parameter; wherein the content of the first and second substances,

4. The method of claim 2, wherein the set of MOS parameters further includes a length parameter, the constructing a MOS module from the drain rectangle, the source rectangle, the gate rectangle, and the third active region layer rectangle, comprising:

5. The method of claim 1, wherein the laying out the at least two MOS modules according to a MOS Array module comprises:

constructing ports of the at least two placed MOS modules;

6. The method of claim 5, wherein the ports comprise a MOSArray source port, a MOSArray drain port, and a MOSArray gate port, the constructing the ports of the at least two MOS modules after tiling comprising:

if a construction instruction for a third first metal layer rectangle is obtained, expanding the at least two MOS modules based on the expansion direction parameter, and constructing a third first metal layer rectangle to control the at least two MOS modules to be connected to the same node;

determining the port based on node type information;

7. The method of claim 6, wherein the node type information comprises first node type information and second node type information, and wherein determining the port based on the node type information comprises:

if the node type information is second node type information, constructing a gate second metal layer rectangle, a source second metal layer rectangle and a drain second metal layer rectangle, wherein the gate second metal layer rectangle is connected to the gate port of each of the at least two MOS modules, the source second metal layer rectangle is connected to the source port of each of the at least two MOS modules, and the drain second metal layer rectangle and the third first metal layer rectangle are connected to the same node;

8. The method of claim 5, wherein the laying out the at least two MOS modules according to the MOS Array module to obtain circuit layouts corresponding to the at least two MOS modules further comprises:

9. The method of claim 8, further comprising, after the controlling the at least two MOSArray vertical alignments pose:

if an add instruction for guard ring guardring is fetched, guardring is added for the at least two mosarrray.

10. An automatic layout apparatus of a MOSFET, comprising: