CN102116806B - ESD (Electro-Static Discharge) test method of chip - Google Patents
ESD (Electro-Static Discharge) test method of chip Download PDFInfo
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- CN102116806B CN102116806B CN200910244499.XA CN200910244499A CN102116806B CN 102116806 B CN102116806 B CN 102116806B CN 200910244499 A CN200910244499 A CN 200910244499A CN 102116806 B CN102116806 B CN 102116806B
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Abstract
The invention provides an ESD (Electro-Static Discharge) test method of a chip, wherein the chip comprises at least two domains; each domain comprises a power pin, a grounding pin and a signal pin. The method comprises the steps of: for each signal pin in each domain, selecting the signal pin as the first signal pin to be tested; selecting and only selecting one signal pin in every other domain as the second signal pin to be tested, wherein the ESD capability between the signal pin and the first signal pin to be tested is worse than the ESD capabilities between the other signal pins in the domain of the signal pin and the first signal pin to be tested; and carrying out ESD test between the first singal pin to be tested and the second signal pin to be tested. Through the test method provided by the invention, not only can the speed of the ESD test between the signal pins be improved, but also the correctness of the ESD test between the signal pins can be effectively improved.
Description
[technical field]
The present invention relates to chip testing field, particularly about a kind of ESD performance test methods of chip.
[background technology]
ESD (Electro-Static discharge) refers to " Electro-static Driven Comb ".Electrostatic is a kind of objectively spontaneous phenomenon, to be non-uniformly distributed on chip itself, human body and on machine and on the chip environment that can exist and surroundings.These static electric charges, all can discharge by certain mode at any time.The feature of Electro-static Driven Comb is that high voltage, low electricity, small area analysis and action time are short.Testing integrated circuits (IC also can be referred to as chip) is very important to the protective capacities of Electro-static Driven Comb.
The ESD test of chip has following several situation: between signal pin and signal pin, between signal pin and power pin, between signal pin and ground pin, between power pin and power pin, between power pin and ground pin and between ground pin and ground pin.Wherein, the part that Measuring Time is the longest is exactly the ESD test between signal pin and signal pin.
Test for the ESD between the signal pin of chip and signal pin, traditional method has two kinds.
The first is traversal, all carries out an ESD test between every two signal pins namely to chip, and as fruit chip has n signal pin, then need test n* (n-1) secondary altogether, this method is the most comprehensive, but also the most time-consuming.Fig. 1 shows the example of the ESD test between signal pin 1 in chip 100 and signal pin 3, when carrying out ESD test, need between signal pin 1 and signal pin 3, to apply instantaneous high pressure to simulate Electro-static Driven Comb, other all pins are all unsettled, described chip 100 has 8 signal pins, i.e. signal 1-signal 8, three groups of power pin and ground pin, namely power supply 1,1, power supply 2,2, power supply 3 and ground 3.When carrying out traversal ESD test to chip 100, an ESD test is all carried out between every two signal pins, that is, not only to carry out ESD test between signal pin 1 and signal pin 3, also need to carry out ESD test between other two signal pins such as signal pin 1 and signal pin 2, signal pin 1 and signal pin 4, signal pin 2 and signal pin 5.
The second is multiple process, be applied on a signal pin by high-tension positive pole, the signal pin that other are all is together in parallel, afterwards high-tension negative pole is applied on the signal pin be connected in parallel, all power pin and ground pin unsettled, this method pendulous frequency is fewer, as fruit chip has n signal pin, only needs n ESD test.Fig. 2 shows the example of the ESD test between signal pin 1 in chip 200 and signal pin 2-8, when carrying out ESD test, signal pin 2-8 is connected in parallel, instantaneous high pressure is applied to simulate Electro-static Driven Comb between signal pin 1 and signal pin 2-8, other all power pin and ground pin all unsettled, described chip 200 has 8 signal pins, i.e. signal 1-signal 8, three groups of power pin and ground pin, namely power supply 1,1, power supply 2,2, power supply 3 and ground 3.When carrying out ESD in parallel to chip 200 and testing, not only to carry out ESD test in parallel to signal pin 1, also need to carry out ESD test in parallel to signal pin 2-8.
But ESD method of testing in parallel can only cover part situation, especially have ignored the test path needing most care.Electrostatic leakage ability between two signal pins is relevant with the resistance on this path, and resistance is less, and allow the electric current that passes through larger, electrostatic leakage ability is stronger, otherwise on the contrary.In the example of the ESD test in parallel shown in Fig. 2, owing to being connected in parallel by signal pin 2-8, the static discharge ability therefore between signal pin 1 and signal pin 2-8 must be greater than the static discharge ability between signal pin 1 and arbitrary other signal pins 2-8.Suppose that the resistance on the path between signal pin 1 and signal pin 5 is maximum, static discharge ability so is between the two just the poorest, even if the ESD test in parallel like this in Fig. 2 is passed through, in actual applications, probably cause chip to be destroyed too due to the Electro-static Driven Comb between signal pin 1 and signal pin 5, that is, the static discharge ability between signal pin 1 and other individual signals pins is still not tested to be arrived.
Therefore, urgently propose a kind of ESD method of testing of improvement, not only can save the test duration, can also cover as much as possible comprehensively.
[summary of the invention]
The object of this part is some aspects of general introduction embodiments of the invention and briefly introduces some preferred embodiments.May do in the specification digest and denomination of invention of this part and the application a little simplify or omit with avoid making this part, specification digest and denomination of invention object fuzzy, and this simplification or omit and can not be used for limiting the scope of the invention.
The object of the present invention is to provide a kind of ESD method of testing of chip, it not only can improve the ESD test speed between signal pin, effectively can also improve the ESD test accuracy between signal pin.
For solving the problem, according to an aspect of the present invention, the present invention proposes a kind of ESD method of testing of chip, described chip comprises at least two territories, each territory includes power pin, ground pin and signal pin, described method comprises: for each signal pin in each territory, selects this signal pin as the first measured signal pin; Select in other territories each and only select a signal pin as the second measured signal pin, the Electro-static Driven Comb ability wherein between the second measured signal pin and the first measured signal pin is compared with the Electro-static Driven Comb ability between other signal pins in the territory at the second measured signal pin place and the first measured signal pin; ESD test is carried out between the first measured signal pin and the second measured signal pin.
Further, described carry out between the first measured signal pin and the second measured signal pin ESD test comprise: the resistance measured between the first measured signal pin and the second measured signal pin obtains the first resistance value; Instantaneous high pressure is applied to simulate Electro-static Driven Comb between the first measured signal pin and the second measured signal pin; The resistance again measured between the first measured signal pin and the second measured signal pin obtains the second resistance value; Relatively whether the first resistance value and the second resistance value change, if not change, then illustrate that the ESD test between the first measured signal pin and the second measured signal pin is passed through, if changed, then illustrate that the ESD test between the first measured signal pin and the second measured signal pin is not passed through.
Further, the Electro-static Driven Comb ability between two signal pins is determined by the resistance on the Electro-static Driven Comb path between them.Further, the resistance on the Electro-static Driven Comb path between two signal pins is corresponding with the distance between them on chip pin is arranged.
According to a further aspect in the invention, the present invention also proposes a kind of ESD method of testing of chip, described chip comprises at least two territories, each territory includes power pin, ground pin and signal pin, described method comprises: for each signal pin in each territory, selects this signal pin as the first measured signal pin; Select in other territories and only select a signal pin as the second measured signal pin, the Electro-static Driven Comb ability wherein between the second measured signal pin and the first measured signal pin is compared with the Electro-static Driven Comb ability between other signal pins and the first measured signal pin; ESD test is carried out between the first measured signal pin and the second measured signal pin.
Further, described carry out between the first measured signal pin and the second measured signal pin ESD test comprise: the resistance measured between the first measured signal pin and the second measured signal pin obtains the first resistance value; Instantaneous high pressure is applied to simulate Electro-static Driven Comb between the first measured signal pin and the second measured signal pin; The resistance again measured between the first measured signal pin and the second measured signal pin obtains the second resistance value; Relatively whether the first resistance value and the second resistance value change, if not change, then illustrate that the ESD test between the first measured signal pin and the second measured signal pin is passed through, if changed, then illustrate that the ESD test between the first measured signal pin and the second measured signal pin is not passed through.
Further, the Electro-static Driven Comb ability between two signal pins is determined by the resistance on the Electro-static Driven Comb path between them.Further, the resistance on the Electro-static Driven Comb path between two signal pins is corresponding with the distance between them on chip pin is arranged.
Compared with prior art, test for ESD by finding out the path that between the signal pin of chip and signal pin, electrostatic leakage ability is poor, this addresses the problem the shortcoming of the test duration length of traditional traversal, also solve not comprehensive, the inaccurate shortcoming of Test coverage of conventional parallel method simultaneously.
[accompanying drawing explanation]
In conjunction with reference accompanying drawing and ensuing detailed description, the present invention will be easier to understand, the structure member that wherein same Reference numeral is corresponding same, wherein:
Fig. 1 is an example of the traversal ESD method of testing of chip of the prior art;
Fig. 2 is an example of the ESD method of testing in parallel of chip of the prior art;
Fig. 3 is the structure block diagram in one embodiment of the segment chip with electrostatic discharge protective circuit in the present invention;
Fig. 4 is the general construction block diagram in one embodiment of the chip with multiple territory in the present invention;
Fig. 5 is the concrete structure block diagram in one embodiment of the chip shown in Fig. 4; With
Fig. 6 is the ESD method of testing process flow diagram in one embodiment in the present invention.
[embodiment]
Detailed description of the present invention carrys out the running of direct or indirect simulation technical solution of the present invention mainly through program, step, logical block, process or other symbolistic descriptions.For thorough understanding the present invention, in ensuing description, set forth a lot of specific detail.And when not having these specific detail, the present invention then may still can realize.Affiliated those of skill in the art use the work that these describe and statement effectively introduces them to the others skilled in the art in affiliated field herein essential.In other words, be object of the present invention of avoiding confusion, because method, program, composition and the circuit known is readily appreciated that, therefore they are not described in detail.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.In addition, represent sequence of modules in the method for one or more embodiment, process flow diagram or functional block diagram and revocablely refer to any particular order, not also being construed as limiting the invention.
Be easier to understand to make the present invention; here the principle of lower electrostatic protection is first introduced; the object of electrostatic protection is: avoid the operating circuit of chip become Electro-static Driven Comb path and damaged; ensure that the Electro-static Driven Comb occurred between any two pins of chip has applicable Electro-static Driven Comb path to be discharged by electrostatic induced current, and can not have an impact to the operating circuit of chip.
In order to understand the principle of the electrostatic protection of chip further, Fig. 3 shows an embodiment of the segment chip 300 with electrostatic discharge protective circuit.Please refer to shown in Fig. 3, described segment chip 300 includes two territories, first territory is analog domain, it includes power pin 311, ground pin 312, signal pin 313, electrostatic discharge protective circuit 314 and internal logic circuit 315, and wherein power pin 311, ground pin 312 and signal pin 313 are connected to internal logic circuit 315 via electrostatic discharge protective circuit 314; Second territory is numeric field; it includes power pin 321, ground pin 322, signal pin 323, electrostatic discharge protective circuit 324 and internal logic circuit 325; wherein signal pin 323 is connected to internal logic circuit 325 via electrostatic discharge protective circuit 324; wherein also comprise the pin that promising internal logic circuit 325 provides VDD-to-VSS in this territory, and not shown herein.Described internal logic circuit 315,325 is the operating circuit in chip.
Described electrostatic discharge protective circuit 314 includes Electro-static Driven Comb power lead ESDVDD1, Electro-static Driven Comb ground wire ESDVSS1 and multiple Electro-static Driven Comb device (ESD device).Described power pin 311 was connected with Electro-static Driven Comb power lead ESDVDD1 before being connected to internal logic circuit 315, and both tie points are connected with Electro-static Driven Comb ground wire ESDVSS1 via an ESD device.Described signal pin 313 is connected with Electro-static Driven Comb ground wire ESDVSS1 via an ESD device, is connected with Electro-static Driven Comb power lead ESDVDD1 via an ESD device.Described ground pin 312 is connected with Electro-static Driven Comb ground wire ESDVSS1 via an ESD device, is connected with Electro-static Driven Comb power lead ESDVDD1 via an ESD device.
Described electrostatic discharge protective circuit 324 includes Electro-static Driven Comb power lead ESDVDD2, Electro-static Driven Comb ground wire ESDVSS2 and multiple Electro-static Driven Comb device (ESD device).Described power pin 321 is being connected to Electro-static Driven Comb power lead ESDVDD2, and both tie points are connected with Electro-static Driven Comb ground wire ESDVSS2 via an ESD device.Described signal pin 323 is connected with Electro-static Driven Comb ground wire ESDVSS2 via an ESD device, is connected with Electro-static Driven Comb power lead ESDVDD2 via an ESD device.Described ground pin 322 is being connected to Electro-static Driven Comb ground wire ESDVSS2, and both tie points are connected with Electro-static Driven Comb power lead ESDVDD2 via an ESD device.Can find out, described power pin 321 is for providing power supply for Electro-static Driven Comb power lead, described ground pin 322 is for providing ground connection for Electro-static Driven Comb ground wire, and the VDD-to-VSS of internal logic circuit 325 then can be provided by other pin (not shown).Electrostatic protection technology comparative maturity, also has many kinds of ESD device, therefore about the concrete structure of ESD device, does not introduce here in prior art.
Described segment chip 300 also includes power supply and cuts off device 330, Electro-static Driven Comb ground wire ESDVSS2 in Electro-static Driven Comb ground wire ESDVSS1 and second territory in first territory for cutting off the Electro-static Driven Comb power lead ESDVDD2 in Electro-static Driven Comb power lead ESDVDD1 and second territory in first territory, and links together by it.Because analog domain requires that VDD-to-VSS is all very stable, numeric field is then much lower to VDD-to-VSS stability requirement, and Electro-static Driven Comb ground wire ESDVSS1 and Electro-static Driven Comb ground wire ESDVSS2 links together, therefore, in order to prevent the noise dither of numeric field from channeling to analog domain, described ground pin 312 is not connected directly to Electro-static Driven Comb ground wire ESDVSS1.
It should be noted that, shown in Fig. 3 is only an embodiment of described segment chip 300, in other embodiments, described segment chip 300 can also include other territories, and the first territory also can change to numeric field, only needs the connected mode changing ground pin 312 according to the ground pin 324 in the second territory just passable, certainly, second territory also can change to analog domain, and in addition, fine setting also may appear in the annexation of each pin.
Regardless of in which territory, when chip normally works, the voltage of each signal pin can be between VDD-to-VSS, when high-pressure electrostatic positive pole is got on this signal pin, electrostatic can by ESD device bleed off on Electro-static Driven Comb power lead, by ESD device, bleed off is on Electro-static Driven Comb ground wire more afterwards, and when high-pressure electrostatic negative pole is got on this signal pin, electrostatic can by the direct bleed off of ESD device on Electro-static Driven Comb ground wire.Therefore, if high-pressure electrostatic is applied between two signal pins in not same area, signal pin 313 in such as the first territory and the signal pin 323 in the second territory, so Electro-static Driven Comb path is exactly: electrostatic positive signal pin, Electro-static Driven Comb power lead, Electro-static Driven Comb ground wire, power supply cut off device, Electro-static Driven Comb ground wire, electrostatic negative signal pin.Can find by analyzing: the Electro-static Driven Comb path between every two signal pins not in same area is the same substantially, maximum difference is the length of Electro-static Driven Comb path, and the length of Electro-static Driven Comb path is directly connected to its electrostatic leakage ability, path is longer, resistance is larger, and the electric current that can release is less; Path is shorter, and resistance is less, and the electric current that can release is larger.
In the present invention, in order to reduce testing time, and ensure test accuracy as far as possible, the Electro-static Driven Comb path can finding out electrostatic leakage ability between the signal pin not between same area of chip and signal pin poor carries out ESD test, if the poor Electro-static Driven Comb path of relieving capacity can be tested pass through, so other relieving capacities good Electro-static Driven Comb path is also certainly no problem.It should be noted that, ESD test for chip comprises several situation below: between signal pin and signal pin, between signal pin and power pin, between signal pin and ground pin, between power pin and power pin, between power pin and ground pin and between ground pin and ground pin, and main ESD between attention signal pin and signal pin tests in the present invention, the test of other types can adopt existing ESD test mode, also can test with reference to the test mode between the signal pin in the present invention and signal pin.
Fig. 4 is the general construction block diagram in one embodiment of the chip 400 with multiple territory in the present invention.Refer to shown in Fig. 4, described chip 400 includes three territories, first territory includes signal pin 1, signal pin 2, power pin 1 and ground pin one, second territory includes signal pin 3, signal pin 4, power pin 2 and ground pin two, and the 3rd territory includes signal pin 5, signal pin 6, signal pin 7, signal pin 8, power pin 3 and ground pin 4.Each territory all include one's own power pin, pin and signal pin.
Fig. 5 is the concrete structure block diagram in one embodiment of the chip 400 shown in Fig. 4.Refer to shown in Fig. 5, described chip 400 includes the first electrostatic discharge protective circuit 410 belonging to territory 1, the second electrostatic discharge protective circuit 420 belonging to territory 2, the 3rd electrostatic discharge protective circuit 430 belonging to territory 3 and internal logic circuit 440.Signal pin 1 and signal pin 2 are connected to internal logic circuit 440 via the first electrostatic discharge protective circuit 410.Signal pin 3 and signal pin 4 are connected to internal logic circuit 440 via the second electrostatic discharge protective circuit 420.Signal pin 5, signal pin 6, signal pin 7 and signal pin 8 are connected to internal logic circuit 440 via the 3rd electrostatic discharge protective circuit 420.Described internal logic circuit 440 is made up of the internal logic circuit belonging to three territories respectively, because this part content and the present invention there is no much relations, therefore in Figure 5 and not shown.In addition, also comprise promising respective internal logic circuit in each territory and the pin of VDD-to-VSS (not shown) is provided.
First electrostatic discharge protective circuit 410 includes the first Electro-static Driven Comb power lead ESDVDD1, the first Electro-static Driven Comb ground wire ESDVSS1 and multiple ESD device (being represented by the rectangular box in Fig. 5 in 410).Second electrostatic discharge protective circuit 420 includes the second Electro-static Driven Comb power lead ESDVDD2, the second Electro-static Driven Comb ground wire ESDVSS2 and multiple ESD device (being represented by the rectangular box in Fig. 5 in 420).3rd electrostatic discharge protective circuit 430 includes the 3rd Electro-static Driven Comb power lead ESDVDD3, the 3rd Electro-static Driven Comb ground wire ESDVSS3 and multiple ESD device (being represented by the rectangular box in Fig. 5 in 430).
Signal pin in each territory is connected with the Electro-static Driven Comb ground wire ESDVSS in this territory via an ESD device, is connected with the Electro-static Driven Comb power lead ESDVDD in this territory via an ESD device.Ground pin in each territory is connected with the Electro-static Driven Comb ground wire ESDVSS in this territory, and is connected with the Electro-static Driven Comb power lead ESDVDD in this territory via an ESD device.Power pin in each territory is connected with the Electro-static Driven Comb power lead ESDVDD in this territory, and is connected with the Electro-static Driven Comb ground wire ESDVSS in this territory via an ESD device.Described chip 400 also includes three power supplys and cuts off device, be respectively used to cut off the Electro-static Driven Comb power lead ESDVDD in adjacent two territories, connect the Electro-static Driven Comb ground wire ESDVSS in adjacent two territories, such three Electro-static Driven Comb ground wire ESDVSS just define a closed loop.
Electro-static Driven Comb path between two signal pins in not same area in Fig. 5 is similarly: electrostatic positive signal pin, Electro-static Driven Comb power lead, Electro-static Driven Comb ground wire, power supply cut off device, Electro-static Driven Comb ground wire, electrostatic negative signal pin, but because three Electro-static Driven Comb ground wire ESDVSS just define a closed loop, so Electro-static Driven Comb path is also incomplete same.
For example, Electro-static Driven Comb path between signal 1 (electrostatic high-pressure positive pole) with signal 3 (electrostatic high-pressure negative pole) comprises two branch roads in parallel, A branch road is: signal 1, ESDVDD1, ESDVSS1, power supply cut off device, ESDVSS2, signal 3, B branch road is: signal 1, ESDVDD1, ESDVSS1, power supply cut off device, ESDVSS3, power supply partition device, ESDVSS2, signal 3, and these two branch roads constitute a complete closed loop; Electro-static Driven Comb path between signal 1 (electrostatic high-pressure positive pole) with signal 4 (electrostatic high-pressure negative pole) is same also comprises two branch roads in parallel: A branch road is: signal 1, ESDVDD1, ESDVSS1, power supply cut off device, ESDVSS2, signal 4, B bar branch road is: signal 1, ESDVDD1, ESDVSS1, power supply cut off device, ESDVSS3, power supply partition device, ESDVSS2, signal 4, and these two branch roads equally also constitute a complete closed loop.A, B two Electro-static Driven Comb branch roads of parallel connection between careful contrast signal 1 and 3 can find with A, B Electro-static Driven Comb branch road in parallel between signal 1 and 4, A branch road between signal 1 and 3 is compared with the A branch road between signal 1 and 4, the road walked on ESDVSS2 except two branch roads is except length is different, both are substantially just the same, B branch road between signal 1 and 3 is compared with the B branch road between signal 1 and 4, the road walked on ESDVSS2 except two branch roads is except length is different, and both are substantially just the same.Due to the mode that A branch road and B branch road are in parallel, and the length of A branch road and B branch road and be definite value, therefore A branch road and B branch road length the most close to time, the resistance between signal pin is maximum, and static discharge ability is the poorest.Therefore, the static discharge ability of the Electro-static Driven Comb path between signal 1 and signal 4 is compared with the static discharge ability of the Electro-static Driven Comb path between signal 1 and signal 3.Like this, in the present invention, ESD electrostatic test is only needed to carry out between signal 1 and signal 4 just passable, if ESD test is between the two passed through, so in general, certainly also out of question between signal 1 and signal 3, also test with regard to not needing again to carry out ESD between signal 1 and signal 3.
Again for example, Electro-static Driven Comb path between signal 1 (electrostatic high-pressure positive pole) with signal 8 (electrostatic high-pressure negative pole) comprises two branch roads in parallel, A branch road is: signal 1, ESDVDD1, ESDVSS1, power supply cut off device, ESDVSS3, signal 8, B branch road is: signal 1, ESDVDD1, ESDVSS 1, power supply cut off device, ESDVSS2, power supply partition device, ESDVSS3, signal 8, and these two branch roads constitute a complete closed loop; Electro-static Driven Comb path between signal 1 (electrostatic high-pressure positive pole) with signal 5 (electrostatic high-pressure negative pole) includes two branch roads in parallel, A branch road is: signal 1, ESDVDD1, ESDVSS1, power supply cut off device, ESDVSS3, signal 5, B branch road is: signal 1, ESDVDD1, ESDVSS1, power supply cut off device, ESDVSS2, power supply partition device, ESDVSS3, signal 5, and these two branch roads also constitute a complete closed loop.A, B two Electro-static Driven Comb branch roads of parallel connection between careful contrast signal 1 and 8 can find with A, B Electro-static Driven Comb branch road in parallel between signal 1 and 5, A branch road between signal 1 and 8 is compared with the A branch road between signal 1 and 5, the road walked on ESDVSS2 except two branch roads is except length is different, both are substantially just the same, B branch road between signal 1 and 8 is compared with the B branch road between signal 1 and 8, the road walked on ESDVSS2 except two branch roads is except length is different, and both are substantially just the same.Due to the mode that A branch road and B branch road are in parallel, and the length of A branch road and B branch road and be definite value, therefore A branch road and B branch road length the most close to time, the resistance between signal pin is maximum, and static discharge ability is the poorest.Therefore, the static discharge ability of the Electro-static Driven Comb path between signal 1 and signal 5 is compared with the static discharge ability of the Electro-static Driven Comb path between signal 1 and signal 8.Like this, in the present invention, ESD electrostatic test is only needed to carry out between signal 1 and signal 5 just passable, if ESD test is between the two passed through, so in general, certainly also out of question between signal 1 and signal 8, therefore do not need between signal 1 and signal 8, again carry out ESD and test.
Therefore, for each signal pin in each territory, only need in other territories each, look for a signal pin that Electro-static Driven Comb via resistance is larger with it to carry out ESD test, greatly reduce ESD testing time like this, also ensure that the accuracy that ESD tests simultaneously.For the chip shown in Fig. 5,8 signal pins, adopt ESD method of testing of the present invention altogether, for each signal pin, only need to look for two signal pins in other two territories, carry out twice ESD test, therefore need altogether 2*8=16 ESD test.
Chip structure shown in Figure 4 and 5 and be all concept in order to territory is described to deserved explanation and how find find the signal pin that Electro-static Driven Comb via resistance is larger in other territories, this does not also mean that the ESD method of testing in the present invention only can be used in said chip.There is a variety of method can modify to the chip shown in Fig. 5, such as can increase one or more territory again, also can reduce by a territory, Electro-static Driven Comb bottom line ESDVSS for another example in three territories can not form a closed loop, and be only once connect, the Electro-static Driven Comb path between every like this two signal pins just only has a road warp.
Therefore, the ESD method of testing 600, Fig. 6 that the present invention proposes a kind of improvement is ESD method of testing 600 process flow diagram in one embodiment of the chip in the present invention.Please refer to shown in Fig. 6, described method of testing comprises the steps.
Step 610, for each signal pin in each territory, selects this signal pin as the first measured signal pin.With reference to shown in Fig. 5, the signal 1 in the first territory such as first can be selected to be the first measured signal pin, after terminating the ESD test to signal 1, the signal 2 in the first territory can be selected again to be the first measured signal pin, after terminating the ESD test to signal 2, the signal 3 in the second territory can be selected again to be the first measured signal pin, so constantly to carry out ESD test, until carried out ESD test to each signal pin in each territory.
Step 620, select in other territories each and only select a signal pin as the second measured signal pin, the Electro-static Driven Comb ability wherein between the second measured signal pin and the first measured signal pin is compared with the Electro-static Driven Comb ability between other signal pins in the territory at the second measured signal pin place and the first measured signal pin.With reference to shown in Fig. 5, signal 1 in such as the first territory is chosen as the first measured signal pin, so need to select in the second territory and only select a signal pin 4 as the second measured signal pin, Electro-static Driven Comb ability wherein between signal pin 1 and signal pin 4 is compared with the Electro-static Driven Comb ability between signal pin 1 and signal pin 3, need to select in the 3rd territory and only select a signal pin 5 as the second measured signal pin, Electro-static Driven Comb ability wherein between signal pin 1 and signal pin 5 is signal pin 1 and signal pin 6 comparatively, Electro-static Driven Comb ability between 7 or 8.
It is to be appreciated that, Electro-static Driven Comb ability between two signal pins is determined by the resistance on the Electro-static Driven Comb path between them, and the resistance on Electro-static Driven Comb path between two signal pins is corresponding with the distance between them on chip pin is arranged.Above, the analysis and comparison of the resistance on having carried out between two signal pins Electro-static Driven Comb path for Fig. 5, is just no longer repeated herein.
Step 630, carries out ESD test between the first measured signal pin and the second measured signal pin.In one embodiment, step 630 can comprise: the resistance measured between the first measured signal pin and the second measured signal pin obtains the first resistance value; Instantaneous high pressure is applied to simulate Electro-static Driven Comb between the first measured signal pin and the second measured signal pin; The resistance again measured between the first measured signal pin and the second measured signal pin obtains the second resistance value; Relatively whether the first resistance value and the second resistance value change, if not change, then illustrate that the ESD test between the first measured signal pin and the second measured signal pin is passed through, if changed, then illustrate that the ESD test between the first measured signal pin and the second measured signal pin is not passed through.
Obviously, in above-described embodiment of ESD method of testing, for each first pin to be measured in each territory, need in other territories each, select a signal pin as the second measured signal pin, like this for the chip with 8 signal pins shown in Fig. 5, then need 16 ESD tests.In order to reduce ESD testing time further, step 620 can be revised as: select in other territories and only select a signal pin as the second measured signal pin, the Electro-static Driven Comb ability between wherein said signal pin and the first measured signal pin is compared with the Electro-static Driven Comb ability between other signal pins and the first measured signal pin.Like this, for each first pin to be measured in each territory, only need to select a signal pin just passable as the second measured signal pin in other territories, specifically, for the chip with 8 signal pins shown in Fig. 5, then only need 8 ESD tests.
Advantage, feature or a benefit of the present invention are: tested for ESD by the path finding out relieving capacity between the signal pin of chip and signal pin poor, this addresses the problem the shortcoming of the test duration length of traditional traversal, also solve not comprehensive, the inaccurate shortcoming of Test coverage of conventional parallel method simultaneously.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. an ESD method of testing for chip, described chip comprises at least two territories, and each territory includes power pin, ground pin and signal pin, it is characterized in that, described method comprises:
For each signal pin in each territory, select each signal pin as the first measured signal pin;
Select in other territories each and only select a signal pin as the second measured signal pin, the Electro-static Driven Comb ability wherein between the second measured signal pin and the first measured signal pin is compared with the Electro-static Driven Comb ability between other signal pins in the territory at the second measured signal pin place and the first measured signal pin; With
ESD test is carried out between the first measured signal pin and the second measured signal pin,
Electro-static Driven Comb ability between two signal pins is determined by the resistance on the Electro-static Driven Comb path between them, and the resistance on the Electro-static Driven Comb path between two signal pins is corresponding with their distances on chip pin is arranged,
Described carry out between the first measured signal pin and the second measured signal pin ESD test comprise:
The resistance measured between the first measured signal pin and the second measured signal pin obtains the first resistance value;
Instantaneous high pressure is applied to simulate Electro-static Driven Comb between the first measured signal pin and the second measured signal pin;
The resistance again measured between the first measured signal pin and the second measured signal pin obtains the second resistance value; With
Relatively whether the first resistance value and the second resistance value change, if not change, then illustrate that the ESD test between the first measured signal pin and the second measured signal pin is passed through, if changed, then illustrate that the ESD test between the first measured signal pin and the second measured signal pin is not passed through.
2. an ESD method of testing for chip, described chip comprises at least two territories, and each territory includes power pin, ground pin and signal pin, it is characterized in that, described method comprises:
For each signal pin in each territory, select each signal pin as the first measured signal pin;
Select in other territories and only select a signal pin as the second measured signal pin, the Electro-static Driven Comb ability wherein between the second measured signal pin and the first measured signal pin is compared with the Electro-static Driven Comb ability between other signal pins and the first measured signal pin; With
ESD test is carried out between the first measured signal pin and the second measured signal pin,
Electro-static Driven Comb ability between two signal pins is determined by the resistance on the Electro-static Driven Comb path between them, and the resistance on the Electro-static Driven Comb path between two signal pins is corresponding with their distances on chip pin is arranged,
Described carry out between the first measured signal pin and the second measured signal pin ESD test comprise:
The resistance measured between the first measured signal pin and the second measured signal pin obtains the first resistance value;
Instantaneous high pressure is applied to simulate Electro-static Driven Comb between the first measured signal pin and the second measured signal pin;
The resistance again measured between the first measured signal pin and the second measured signal pin obtains the second resistance value; With
Relatively whether the first resistance value and the second resistance value change, if not change, then illustrate that the ESD test between the first measured signal pin and the second measured signal pin is passed through, if changed, then illustrate that the ESD test between the first measured signal pin and the second measured signal pin is not passed through.
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| CN104502646B (en) * | 2014-12-22 | 2019-07-05 | 上海斐讯数据通信技术有限公司 | A kind of mobile terminal test fixture protective device |
| CN107121605A (en) * | 2017-04-21 | 2017-09-01 | 浙江诺尔康神经电子科技股份有限公司 | A kind of cochlear implant stimulator chip antistatic method of testing |
| CN108680800B (en) * | 2018-03-16 | 2021-10-29 | 昆山国显光电有限公司 | ESD testing arrangement |
| CN109541432A (en) * | 2018-09-30 | 2019-03-29 | 天津大学 | Chip-scale ESD automatization test system based on Labview |
| CN109951700B (en) * | 2019-02-15 | 2020-09-04 | 信利光电股份有限公司 | ESD (electro-static discharge) testing tool and testing method for camera module |
| CN110361601B (en) * | 2019-08-02 | 2021-05-25 | 深圳市全洲自动化设备有限公司 | Method for rapidly testing electric indexes of pins of LCD (liquid crystal display) device |
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| CN1576868A (en) * | 2003-07-08 | 2005-02-09 | 松下电器产业株式会社 | Semiconductor integrated circuit, and electrostatic withstand voltage test method and apparatus therefor |
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| WO2008132561A1 (en) * | 2007-04-27 | 2008-11-06 | Freescale Semiconductor, Inc. | Integrated circuit, electronic device and esd protection therefor |
| CN101793923A (en) * | 2009-11-03 | 2010-08-04 | 福建星网锐捷网络有限公司 | Electrostatic discharge test device, system and method |
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| US5072175A (en) * | 1990-09-10 | 1991-12-10 | Compaq Computer Corporation | Integrated circuit having improved continuity testability and a system incorporating the same |
| CN1576868A (en) * | 2003-07-08 | 2005-02-09 | 松下电器产业株式会社 | Semiconductor integrated circuit, and electrostatic withstand voltage test method and apparatus therefor |
| CN101122621A (en) * | 2006-08-10 | 2008-02-13 | 华硕电脑股份有限公司 | Electrostatic discharge detection device and method |
| WO2008132561A1 (en) * | 2007-04-27 | 2008-11-06 | Freescale Semiconductor, Inc. | Integrated circuit, electronic device and esd protection therefor |
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