CN102111127B

CN102111127B - Signal count delay method and circuit in chip electrifying process

Info

Publication number: CN102111127B
Application number: CN 200910243494
Authority: CN
Inventors: 卢锋; 赵贵勇; 关红波; 刘华茂
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2009-12-23
Filing date: 2009-12-23
Publication date: 2013-05-15
Anticipated expiration: 2029-12-23
Also published as: CN102111127A

Abstract

The invention relates to the field of the reliability of chips, in particular to a signal count delay method in a chip electrifying process. The method increases the reliability of circuit count delay time by improving a conventional chip electrifying delay count circuit. The method is specifically implemented by the following steps of: delaying a plurality of signals by using a counter in the chip electrifying process; extracting marks of a plurality of count values from the count values of a delay counter; stopping counting by using the counter only when the extracted mark values are counted by using the counter; and generating a delayed signal after the counter stops. By adopting the method, the guarantee of the count values of the delay counter when the chip is electrified abnormally can be increased, and the reliability when the chip is electrified abnormally can be remarkably improved.

Description

A kind of Method and circuits of chip power process signal count delay

Technical field

The invention belongs to the reliability field of chip, be specifically related to the reliability of chip when improper mode power-on and power-off.

Background technology

Along with informationalized development, electronic product occupies more and more important role in daily life.The problem that the reliability of these electronic products has become people to be concerned about very much, Reliability Synthesis have reflected the characteristics such as permanance, non-fault, validity and its usage economy of a product, are important quality index of product.Vitals in the electronic product that chip is carried as the individual, unconsciously, more and more every aspects that are applied in people's life.The widespread use of chip makes its reliability be paid close attention to greatly by people.

In the application of chip, there are some abominable applied environments or nonstandard operation, some improper power-on and power-off situations appear.Good not as the reliability design of fruit chip, the impact of improper damaging property of power-on and power-off meeting.

During the improper power-on and power-off operation of chip reply in the past, the reliable design proposal that postpones of internal signal is: some key signal in power up is carried out digital delay with simple counter, when the signal after postponing is effective, internal power source voltage is stable, then whole chip brings into operation, and guarantees in this way the stability of moving after chip power.in such scheme, there is some problems in simple counter delay when improper power-on and power-off, following description: when the chip due to abnormal electrifying, powering on, when finishing, the voltage of internal standard unit does not also reach normal operational voltage value, but this hour counter is started working, it is abnormal that improper operating voltage can make counter works occur, cause counter not write all count values all over and arrive very soon the counting terminal point, thereby when causing chip to be started working, builtin voltage does not also arrive the normal working voltage value, too low voltage makes the execution of CPU cause confusion and chip is caused a devastating effect.

Along with the development of semiconductor technology to dark nanometer direction, how to guarantee that chip reliability of chip when improper power-on and power-off becomes to become increasingly conspicuous.The present invention has improved the counting reliability of chip power hour counter greatly by the decision procedure of improving counter and rolling counters forward, the safety of chip internal data when improper power-on and power-off is protected.

Summary of the invention

The improving one's methods of inner power up key signal delay digital counter used when the object of the present invention is to provide a kind of chip due to abnormal electrifying improved chip security of data in card when improper power-on and power-off.Simultaneously, the present invention can also reduce the power consumption of circuit by the clock signal of closing counter register after rolling counters forward is completed.

In order to realize the purpose of foregoing invention, technical scheme provided by the present invention is described in detail as follows:

A kind of circuit of chip power process signal count delay, its circuit comprise counter circuit, count tag circuit, mark treatment circuit, the clock gating circuit that improves counting mode.The principle of work of whole circuit be during by the chip due to abnormal electrifying delay counter through the counting intermediate value of all settings, thereby can guarantee count delay time long enough, avoided when due to abnormal electrifying is worked rolling counters forward result inaccurate and gate time that cause is significantly less than the situation of expection.

The above-mentioned said chip that comprises various applications.

The above-mentioned said key signal delay counter that powers on, its concrete circuit form can be any type of counter, the common counter that adds the improved procedure of mentioning in 1 device or the present invention.The counter of improved procedure is by simplifying the combinational logic complexity in counter circuit, guaranteed that under the low pressure condition, counter can normally be counted under the chip exterior clock, included two kinds of forms: linear feedback shift register (LFSR) and asynchronous counter.

Above-mentioned said count tag circuit is comprised of two parts, comparator circuit and flag register.Wherein comparator circuit is the condition that produces flag register set, produces the counting condition of this flag register if the counter meter has been a counting track numerical value that sets in advance.The effect of flag register circuit is to indicate that the counter meter crosses the counting intermediate value of all settings.

Above-mentioned said mark treatment circuit is logical circuit, and its input is the output of all flag registers, and output is the signal after postponing.

The effect of above-mentioned said clock gating circuit is that in shut-off circuit, the clock of all registers is to save power consumption after rolling counters forward postpones to complete, and the gate type can be two kinds.A kind of is and the gateable clock gating circuit that purpose is to allow the clock signal of counter register and flag register be parked in low level; Another kind is or the gateable clock gating circuit that purpose is to allow the clock signal of counter register and flag register be parked in high level.

A kind of method of chip power process signal count delay, utilize the circuit in this method can significantly improve chip security of data in card when improper power-on and power-off, strengthen greatly the reliability of chip, guaranteed the application safety of chip under various mal-conditions.

Description of drawings

Fig. 1 overall circuit structural drawing

Fig. 2 linear feedback shift register circuit principle sketch

Fig. 3 asynchronous counter principle sketch

Fig. 4 count tag circuit diagram

Embodiment

Below in conjunction with Figure of description, the specific embodiment of the present invention is further described.

Fig. 1 is overall construction drawing of the present invention.the specific works flow process of whole circuit is, counter begins counting after input signal is invalid, in the counter works process, the corresponding marker bit of count tag circuit Lookup protocol when if counter values is remembered of set count tag intermediate value, signal after the mark treatment circuit produces final delay automatically after all marker bits all are set to effectively, signal after delay is given subsequent control circuit in card, signal after this postpones is simultaneously also delivered to clock gating circuit and is used for turn-offing the clock of counter register and the clock of flag register.

The below is the problem of common count delay during the explanation chip power as an example of the count delay of chip power reset signal example.When the chip due to abnormal electrifying, its external terminal signal begins effectively.Because the electrification reset level in chip is general all well below the normal operation level of internal standard unit, the level of power-on reset signal generally also can only keep tens microseconds, when due to abnormal electrifying speed is slow, block but exist the invalid rear delayed management counter of electrification reset to start working the situation that builtin voltage does not reach the logical block normal working voltage, result can cause the rolling counters forward confusion and make counter count very early end.Voltage when above-mentioned situation can make the card system reset invalid in card does not reach normal working voltage and causes CPU to carry out confusion.

In said process, the logical circuit between common counter register is long, occurs abnormal situation probability under low pressure very high.When specifically implementing, the present invention can select the simple counter of some logical circuits, two kinds of counters as shown in Figures 2 and 3, respectively linear feedback shift register and asynchronous counter, combinational logic path between register is very little, and the reliability than common rolling counters forward under identical low voltage operating condition is higher.

Count tag is the pith of content of the present invention, and Fig. 3 has described the principle of a count tag generation circuit in a plurality of flag registers.Comparer produces the set condition of flag register, and when counter had been remembered the numerical value identical with the value that sets in advance, the corresponding flag register of meeting set can be remained valid after flag register set always.The mark treatment circuit has all been delivered in the output of all flag registers.

The principle of mark treatment circuit is, must wait until that in flag register, all marker bits all are set rear just release to give subsequent conditioning circuit, the minimum requirement of guarantee delay counter time like this.

The purpose of clock gating circuit is to save the circuit dynamic power consumption for clock signal that the counting that powers on is closed the clock signal of counter register and flag register after completing reaches.

The enforcement of above-mentioned detailed circuit scheme in the present invention can effectively strengthen the reliability of chip when improper power-on and power-off operation, and the dynamic power consumption of delay circuit when powering on can reduce chip operation the time.

Claims

1. the method that in a chip power process, signal-count postpones, it is characterized in that the method strengthens the reliability of power up signal delay rolling counters forward with a plurality of flag registers, when numerical value that counter counts identical with the value that sets in advance, the corresponding flag register of meeting set, only have all flag registers all to be set, counter just stops counting, produces the signal after postponing.

2. a circuit that is used for the signal-count delay of chip power process, is characterized in that this circuit is comprised of counter, a plurality of count tag circuit, mark treatment circuit and clock gating circuit, wherein:

When described counter is realized chip power to the delay counter function of source signal;

Described count tag circuit is by comparator circuit and flag register the electric circuit constitute, and comparator circuit produces the set condition of flag register circuit, when numerical value that counter counts identical with the value that sets in advance, and the corresponding flag register circuit of set;

Described mark treatment circuit is for generation of the signal after postponing, when numerical value that counter counts identical with the value that sets in advance, can the corresponding flag register of set, only have all flag registers all to be set, counter just stops counting, produces the signal after postponing;

Described clock gating circuit is closed the clock signal of register in whole circuit to save power consumption after counting is completed.

3. the circuit that postpones of a kind of signal-count for the chip power process as claimed in claim 2, is characterized in that the value that sets in advance can be the arbitrary value in rolling counters forward numerical value.

4. the circuit that postpones of a kind of signal-count for the chip power process as claimed in claim 2, is characterized in that when all flag registers of set after, postpones the clock that signal controlling is afterwards closed counter.