CN116961628B - Method and device for realizing fixed delay time - Google Patents
Method and device for realizing fixed delay time Download PDFInfo
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- CN116961628B CN116961628B CN202311221141.1A CN202311221141A CN116961628B CN 116961628 B CN116961628 B CN 116961628B CN 202311221141 A CN202311221141 A CN 202311221141A CN 116961628 B CN116961628 B CN 116961628B
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- 150000004706 metal oxides Chemical class 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 238000012795 verification Methods 0.000 description 21
- 238000010586 diagram Methods 0.000 description 15
- 230000005540 biological transmission Effects 0.000 description 5
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/38—Starting, stopping or resetting the counter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
Abstract
The invention discloses a method and a device for realizing fixed delay time, comprising the following steps: the pre-stage circuit sends a signal to the latch circuit, and the latch circuit latches effective information in the signal; the counter counts the external clock according to the effective information; acquiring the current working frequency of a system according to the public parameter values of at least two system modules in the chip, and configuring a frequency marking signal to send to a combinational logic circuit; the combination logic circuit judges the count of the counter according to the frequency marking signal, generates a stop signal when the preset requirement is met, and replaces the mode that the existing oscillator circuit generates delay after the latch circuit is invalid, so that the number of selected MOS (metal oxide semiconductor) tubes is obviously reduced, and the defect that the MOS tubes are influenced by the effects of temperature, voltage and process factors is overcome; the delay is generated in a digital mode, and the current working frequency of the system is judged through the common parameter values among the modules in the system, so that the systems running at different working frequencies can generate accurate fixed delay time.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a method and a device for realizing fixed delay time by adopting a digital mode in a scene with different operating frequencies.
Background
In order to improve applicability and stability, when the memory leaves the factory, the working frequency of the memory is generally set to be a default low frequency, for example, the default frequency of the DDR3 memory of the previous generation is generally 160 MHz, and the factory default frequency of the DDR4 memory is generally 2400MHz. In practice, however, the memory may operate at higher frequencies by over-clocking, e.g., DD4 memory at an off-clocking of 2400MHz may be over-clocking to operating at high frequencies of 2666MHz and 3200 MHz.
According to the constitution of the memory particles, the frequency, time sequence and voltage characteristics are different, so that the memory product can usually operate at different working frequencies, but in the design of dram (dynamic random access memory), some signals are required to be delayed for a fixed time at different working frequencies, so that a counting circuit is required to be introduced to count the fixed delay time.
Conventionally, it is a kind of oscillating circuit as shown in fig. 1. Referring to fig. 1, a signal carrying effective information latches the effective information through a latch circuit, the effective information controls an oscillator to start working, thereby generating a fixed periodic clock, the clock signal controls a counter to count the effective information, a combinational logic circuit judges the output of the counter, when the design requirement is met, a stop signal is generated and fed back to the latch circuit and the oscillator, the signal is set in an invalid state, the oscillator is stopped, and the counter is stopped working, so that the fixed periodic clock generated by the oscillator controls the counter to count, and the delay fixed time is realized. Fig. 2 is a timing diagram showing the timing of the oscillator circuit of fig. 1 to achieve a delay of a fixed time, as shown in fig. 2, after the lapse of the period of time counted by the counter, the output signal is also changed from low to high.
In the existing mode, although the realization of delay fixed time can be solved, in the mode of adopting analog delay, a large number of MOS (metal oxide semiconductor) tubes are needed for generating the required delay, which inevitably leads to the bulkiness of an oscillator circuit, the design of the circuit is complex, the layout area is difficult to reduce, and the accuracy and the stability of generating the fixed delay of the MOS tubes are insufficient due to the characteristics of the MOS tubes, which are easily influenced by temperature, voltage and preparation process.
It is therefore desirable to provide a method for reducing the number of MOS transistors and improving the accuracy and stability of the fixed delay generation, thereby solving the above-mentioned problems of the prior art.
Disclosure of Invention
The invention provides a method and a device for realizing fixed delay time to solve at least one of the technical problems.
To solve the above technical problem, a first aspect of the present invention is to adopt a method for implementing a fixed delay time, the implementing method comprising the following steps: the pre-stage circuit sends a signal to the latch circuit, and the latch circuit latches effective information in the signal; the counter counts an external clock according to the effective information; acquiring the current working frequency of a system according to the public parameter values of at least two system modules in the chip, and configuring a frequency marking signal to be sent to the combinational logic circuit; the combination logic circuit judges the count of the counter according to the frequency marking signal, generates a stop signal when the count of the counter meets the preset requirement, feeds back the stop signal to the latch circuit, and circulates the steps after the latch circuit is invalid.
As a preferred embodiment of the first aspect of the present invention, the step of obtaining the current operating frequency of the system according to the common parameter value of at least two system modules in the chip is specifically: in the chip initialization process, acquiring current clock periods corresponding to time settings of at least two system modules, determining working frequency intervals of the two systems according to the current clock periods, and defining the working frequency intervals as a first interval range and a second interval range respectively; acquiring an intersection of the first interval range and the second interval range to determine a current operating frequency of the system, and taking the current operating frequency of the system as the frequency marking signal.
In a second aspect of the present invention, there is provided a fixed delay time apparatus configured between functional modules under a chip system, wherein the apparatus comprises: a latch circuit that receives a data signal including effective information transmitted from the pre-stage circuit; a counter structure that counts an external clock by the effective information control; and the combination logic circuit is configured to judge the count of the counter structure according to the frequency marking signal so as to generate a stop signal to control the latch circuit to stop.
As a further preferred aspect of the present invention, the frequency signature signal is obtained from a common parameter value of at least one system module within the chip, in particular: in the chip initialization process, acquiring current clock periods corresponding to time settings of at least two system modules, determining working frequency intervals of the two systems according to the current clock periods, and defining the working frequency intervals as a first interval range and a second interval range respectively; acquiring an intersection of the first interval range and the second interval range to determine a current operating frequency of the system, and taking the current operating frequency of the system as the frequency marking signal.
As a further preferred feature of this aspect of the invention, the apparatus further comprises a controller circuit including a verification circuit therein, the control circuit verifying the effective information and transmitting both the effective information and the first verification result to a memory, the memory performing a second verification of the effective information and comparing the result of the second verification with the first verification result transmitted by the control circuit and outputting a warning signal, wherein the latch circuit latches the warning signal, the counter structure counts the external clock until the combination logic circuit determines the count of the counter structure and transmits a stop signal.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following beneficial technical effects:
1. under the scene that the chip system needs to generate fixed delay time under different working frequencies, the traditional mode is improved, the mode of generating delay by replacing the original oscillator circuit is replaced, the number of MOS (metal oxide semiconductor) tubes selected in the circuit is obviously reduced, and the defect that the MOS tubes are influenced by temperature, voltage and process factors to generate the fixed delay time is overcome;
2. meanwhile, delay is generated in a digital mode, the current working frequency of the system is judged through the common parameter values among the modules in the system, and the combination logic circuit is configured in a frequency identification signal mode, so that judgment is made on the count of the counter, and therefore, the system running at different working frequencies can generate accurate fixed delay time.
Drawings
Fig. 1 is a block diagram showing an equivalent circuit of an oscillator circuit that implements a delay fixed time in a conventional manner;
FIG. 2 is a timing diagram illustrating the timing of the oscillator circuit shown in FIG. 1 to achieve a fixed delay time;
FIG. 3 is a frame diagram showing the structure of a frame of the fixed delay time device according to the preferred embodiment of the present invention;
FIG. 4 is a block diagram illustrating the structure of command and address verification to which the first embodiment of the present invention pertains;
FIG. 5 is a block diagram illustrating a block structure of a command and address verification module according to a first embodiment of the present invention;
fig. 6 is a schematic diagram showing an equivalent circuit diagram of a verify reset circuit in the first embodiment of the present invention;
fig. 7 is a schematic diagram showing an equivalent circuit diagram of a self-refresh circuit in the second embodiment of the present invention.
Detailed Description
Referring back to fig. 1, the MOS transistors selected in the conventional structure are mainly a plurality of MOS transistors connected to each other in an oscillator circuit, so as to implement an oscillator circuit. For example, in an equivalent structure of a ring oscillator, an odd number of adjustable delay units serving as inverters are sequentially connected, and one oscillator clock is triggered and output by a clock signal. It will be seen that the use of a multi-stage MOS transistor is required for analog delay on the one hand, and that the oscillator circuit is operative to generate a clock for controlling the counter count, the clock generated by the oscillator circuit being a clock of a fixed clock period, i.e. a fixed delay time, on the other hand.
The preferred embodiment of the invention expects to reduce the number of MOS tubes selected in the circuit so as to obviously reduce the influence of the characteristics of the MOS tubes on the fixed delay generation process, so that the thought of solving the technical problem should relate to two aspects, namely, the fixed delay is realized in a mode of not selecting MOS tubes to form an oscillator; secondly, a new way of triggering the count needs to be provided for the counter, in other words, a new clock signal is provided for the counter. In this idea, it is an easy way to implement a delay fixed time with a digital delay. Referring to fig. 3, fig. 3 is a frame diagram showing a frame structure of the fixed delay time device according to the preferred embodiment of the present invention, in which an oscillator originally used for generating a fixed clock period is removed, and an external clock is used as a driving clock of a counter. When the system works at different frequencies, since the external clock period is not a fixed period, in the mode of delaying the fixed time by digital implementation, how to change the number and mode of the counter according to different external clock periods needs to be solved, in other words, how to set up the number of the counter to reach, a stop signal is generated and fed back to the latch circuit.
After the oscillator is removed and an external clock is introduced, the preferred embodiment of the present invention determines the current operating frequency of the system by other information within the system. Under the chip system, a part of common parameters are shared among all functional modules, and a part of the common parameters have different clock cycles because the system works at different working frequencies, if the common parameters are utilized, the working frequency of the system can be deduced through the change of the clock cycles. Although the system operating frequency pointed by the current clock cycle of the common parameter is not unique, the interval range of a plurality of operating frequencies can be determined through the system operating frequency corresponding to the current clock cycle of the common parameter, and the obtained operating frequency is obtained by solving the intersection of the interval ranges, namely the current operating frequency of the system. And then, the working frequency is used as a marking signal to configure a combinational logic circuit, the combinational logic circuit judges whether the count of the counter meets the preset requirement according to the marking signal of the working frequency, when the count meets the requirement, the combinational logic circuit can generate a stop signal to control the latch circuit to stop, and then, the counter stops working and does not count an external clock. This completes one counting cycle, although repeated as per the above steps.
Embodiments of a fixed delay time implementation method and apparatus according to the present invention will be described below with reference to the accompanying drawings. Those skilled in the art will recognize that the described embodiments may be modified in various different ways without departing from the spirit and scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive in scope. Furthermore, in the present specification, the drawings are not drawn to scale, and like reference numerals denote like parts.
It should be noted that, in the embodiments of the present invention, the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the expressions "first" and "second" are merely used for convenience of description, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
The application scenario of the preferred embodiment of the present invention may be a plurality of different functional modules within a system-on-a-chip. These modules have the following characteristics: there is a fixed delay time when operating at different clock cycles. When this fixed delay time is counted by a counter, the system needs to explicitly stop the counting of the counter for what duration and reset the counter. For example, when a fixed delay time of 10ns is required, if the clock frequency counted by the counter is 1ns, the combination logic of the system should control the counter to stop counting when the counter counts to 10, and if the clock frequency of the counter or the clock frequency counted by the counter is changed, for example, becomes 2ns, the stop signal should be sent out by the combination logic of the system when the counter counts to 5. The following describes the operation of the preferred embodiments of the present invention in two embodiments.
Example 1
In one embodiment, a command and address verification function module in a dynamic random access memory is taken as an example. In dram, in a chip design based on a conventional architecture, commands and addresses need to be repeatedly transferred between the memory side and the operation side of the system. In order to ensure the accuracy of the transmission of commands and addresses inside the chip, a verification mechanism is usually introduced in the transmission process of the commands and addresses.
Referring to fig. 4, fig. 4 is a block diagram illustrating a structure of command and address verification to which an embodiment of the present invention belongs. The command and address are checked twice in the dram system controller and in the dram. Specifically, the checking circuit at the controller end checks the command and the address to obtain a first checking result. Then, the controller sends the command and address together with the result of the first verification to the storage side of dram. And the verification circuit at the storage side performs secondary verification on the command and the address sent by the controller, and obtains a secondary verification result. And finally, comparing the two checking results to obtain a parity check bit, wherein the parity check bit signal is used for judging whether the command and the address data are changed in the transmission process.
Turning to fig. 5, fig. 5 is a block diagram illustrating a block structure of a command and address verification module according to a first embodiment of the present invention. In order to make the results of the two checks sent together to the comparator for comparison in the command and address function checking module as described above, a warning signal is generated and delayed if the parity bit marks that the command and address change during transmission in the command and address module as described above. When the method is implemented, a verification circuit of the command and address module comprises a verification delay module, and after the command and address data are sent to the verification delay module, two groups of commands and two groups of address data are generated. As shown in the figure, for convenience of explanation and illustration, two sets of command and address data are defined as command 1, address 1, command 2 and address 2, respectively, wherein, command 1 and address 1 are data which do not carry the verification delay information, and command 2 and address 2 are data which carry the verification delay information.
Under the delay module, the command 1 and the command 2 and the check bit of the address 1 and the address 2 are checked, and finally a signal is generated after passing through a check reset circuit to indicate whether the two groups of commands and the address are consistent, when the commands or the addresses are misplaced, the signal is sent to identify the current command and the address error, the transmission is stopped, the signal is delayed for a period of time, and otherwise, the address and the command carrying the correct information can be continuously transmitted. Here, the delay time is realized by a circuit as shown in fig. 6. In the check reset circuit as shown in the figure, a latch circuit, which way the counter is, and a combinational logic circuit are included. And a latch in the latch circuit receives the check bit information, and the latch command latches the data carried by the check bit information. When the input of the latch circuit is set to be low, the output O is also set to be low. After passing through a NAND gate, a high level is output to the counter. After the counter is input at a high level, the external clock is counted. The combination logic circuit judges whether the count of the counter meets the preset requirement, namely, the combination logic circuit judges whether the count of the current counter reaches the count required by generating the fixed delay time, and when the count is met, a stop signal is generated and sent to an enabling end of the latch circuit, and the counter stops counting while the latch circuit stops working.
In this process, the logic combination circuit determines the standard of counter count, i.e., by the frequency signature signal. In one embodiment of the present invention, the generation of the frequency signature signal is determined based on the clock cycle of the column write latency (CAS WRITE latency). When the dram is in operation, the initialization process of the chip sets some time of the system, wherein the column write latency refers to the clock period between the internal write command of the system and the first valid data input, and the time needs to set the corresponding clock period under different operating frequencies of the system. For example, when the column write latency is set to 12 clock cycles, it can be judged that the column write latency is operated at 2400MHz or 1866MHz, and correspondingly, if the check cycle of the command and the address is set to 5 clocks, it can be judged that the column write latency is operated at 2400MHz or 2666MHz, and by combining the two information, it can be judged that the dram is currently operated at 2400 HZ. After knowing the current operating frequency of the system, the frequency signature signal can be configured according to the frequency value, so that the combinational logic circuit can make a judgment on the count of the counter according to the current requirement of the system.
It should be noted that, since, for example, the column write latency and command and address check period values are common parameters for each module in the system, these parameters can be used to reverse the operating frequency of the system. It should be understood that the method for determining the operating frequency of the system is not limited to the command and address module, but is also not limited to selecting the latency of the row writing and the verification period as the common parameter values.
Example 2
In a second embodiment of the present invention, a self-refresh (self-refresh) module of dram is taken as an example. The dynamic random access memory is a volatile memory, and memory cells in the dynamic random access memory are often refreshed repeatedly in the read-write process. When the chip receives the self-refresh command, the chip delays the generation of the subsequent refresh command for a fixed time.
Referring to fig. 7, fig. 7 is a schematic diagram showing an equivalent circuit diagram of a self-refresh circuit in a second embodiment of the present invention. A self-refresh enable signal is transmitted to the module, and refresh information carried by the signal is latched. The input signal is set to low, the output of the latch at point a is also low, and the output at point B is high after passing through the nand gate. The high level enables the counter to start counting the external clock.
In the second embodiment of the present invention, the frequency marking signal may be configured in the manner described in the first embodiment. The combination logic circuit judges the output of the counter by combining the frequency marking signal, when the frequency marking signal meets the preset requirement of the current working frequency, a high-level stop signal is generated, at the moment, the position of the point A is set to be high level, a refresh command is generated, meanwhile, the point B is low level, the latch circuit stops working, and then the counter stops working.
The foregoing examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (3)
1. A method for implementing a fixed delay time, wherein the method comprises the steps of:
the pre-stage circuit sends a signal to the latch circuit, and the latch circuit latches effective information in the signal;
the counter counts an external clock according to the effective information;
in the chip initialization process, acquiring current clock periods corresponding to time settings of at least two system modules, determining working frequency intervals of the two systems according to the current clock periods, and defining the working frequency intervals as a first interval range and a second interval range respectively; acquiring an intersection of the first interval range and the second interval range to determine the current working frequency of the system, and sending the current working frequency of the system to a combinational logic circuit as a frequency marking signal;
the combination logic circuit judges the count of the counter according to the frequency marking signal, generates a stop signal when the count of the counter meets the preset requirement, feeds back the stop signal to the latch circuit, and circulates the steps after the latch circuit is invalid.
2. A fixed delay time device configured between functional modules under a chip system, wherein the device comprises:
a latch circuit that receives a data signal including effective information transmitted from the pre-stage circuit;
a counter structure that counts an external clock by the effective information control;
the combination logic circuit is configured to judge the count of the counter structure according to the frequency marking signal so as to generate a stop signal to control the latch circuit to stop, wherein in the chip initialization process, the current clock period corresponding to the time setting of at least two system modules is acquired, the working frequency intervals of the two systems are determined according to the current clock period, and the working frequency intervals are respectively defined as a first interval range and a second interval range; and acquiring an intersection of the first interval range and the second interval range to determine the current working frequency of the system, wherein the frequency marking signal is determined by the current working frequency of the system.
3. The fixed delay time device of claim 2, wherein the device further comprises a control circuit including a check circuit therein, the control circuit checks the effective information and transmits both the effective information and the first check result to a memory, the memory performs a second check on the effective information and compares the result of the second check with the first check result transmitted by the control circuit and outputs a warning signal, wherein,
the latch circuit latches the warning signal, and the counter structure counts the external clock until the combination logic circuit judges the count of the counter structure and then sends a stop signal.
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| CN202311221141.1A CN116961628B (en) | 2023-09-21 | 2023-09-21 | Method and device for realizing fixed delay time |
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| CN202311221141.1A CN116961628B (en) | 2023-09-21 | 2023-09-21 | Method and device for realizing fixed delay time |
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