KR20240007735A - Memory, control units, clock processing methods and electronics - Google Patents

Abstract

An embodiment of the present invention provides a memory, a control device, a clock processing method, and an electronic device, wherein a clock processing circuit in the memory performs duty cycle adjustment on a data clock signal and outputs an internal clock signal. module; a first clock generation module configured to receive an internal clock signal and, based on the internal clock signal, output a first read clock signal, wherein the first read clock signal is a pulse signal; a second clock generation module configured to generate and output a second read clock signal, wherein the second read clock signal has only one level state change edge; and a selection module configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as the target read clock signal.

Description

Memory, control units, clock processing methods and electronics

Cross-reference to related applications

The present invention is filed based on a Chinese patent application with application number 202210806176.0, application date July 8, 2022, and the title of the invention is “Memory, control device, clock processing method and electronic device,” and the above Chinese patent Claiming the priority of the application, the entire contents of the above Chinese patent application are hereby incorporated by reference.

The present invention relates to the field of semiconductor memory technology, and particularly to memories, control devices, clock processing methods and electronic devices.

In an electronic device, a central processing unit (CPU) sends a read command to a memory, then receives a read clock signal and a read data signal returned by the memory, and uses the read clock signal to signal a read data signal. By performing latch processing on , the required data is obtained. However, in the process where the memory performs duty cycle adjustment for the clock signal, the central processing unit must obtain the duty cycle parameter of the clock signal through reading the corresponding mode register in the memory, but in this process, the clock inside the memory Since the signal may be malformed, the read clock signal returned by the memory to the central processing unit may also be malformed, causing the central processing unit to obtain incorrect data, and ultimately resulting in failure of duty cycle adjustment of the clock signal. .

The present invention provides a memory, a control device, a clock processing method and an electronic device, and provides a second read clock signal having a single level change edge to avoid data latch failure when the duty cycle of the internal clock signal of the memory is abnormally changed. You can select to use it as the target read clock signal.

The technical solution of the present invention is implemented as follows.

In a first aspect, an embodiment of the present invention provides a memory, the memory comprising a clock processing circuit, the clock processing circuit comprising:

Receive an externally generated data clock signal; a duty cycle module configured to perform duty cycle adjustment on the data clock signal and output an internal clock signal;

a first clock generation module configured to receive the internal clock signal and, based on the internal clock signal, output a first read clock signal, wherein the first read clock signal is a pulse signal;

a second clock generation module configured to generate and output a second read clock signal while the first read clock signal is present, wherein the second read clock signal has only one level state change edge; and

and a selection module configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as a target read clock signal.

In some embodiments, the clock processing circuit further includes a detection module and a mode register; Here, the detection module is configured to receive the internal clock signal, perform duty cycle detection on the internal clock signal, and output a duty cycle parameter; The mode register is configured to receive and store the duty cycle parameter.

In some embodiments, the selection module further receives a selection instruction signal, and when the selection instruction signal is in a first state, outputs the first read clock signal as a target read clock signal; Alternatively, when the selection instruction signal is in the second state, it is configured to output the second read clock signal as a target read clock signal.

In some embodiments, the memory receives a data read command; configured to output a read data signal based on the data read command and output the target read clock signal through the clock processing circuit; Here, the target read clock signal is for latching the read data signal, and the level state change edge of the second read clock signal indicates the end time of valid data in the read data signal.

In some embodiments, the memory further sets the selection instruction signal to a first state when the data read command is a first read command; Alternatively, when the data read command is a second read command, it is configured to set the selection instruction signal to a second state; Here, the second read command instructs the clock processing circuit to obtain a duty cycle parameter of the mode register, and the first read command indicates a data read command excluding the second read command.

In some embodiments, the memory further sets the selection instruction signal to a first state when the data read command is a first read command; Alternatively, if the data read command is a second read command and the duty cycle of the internal clock signal is within a preset range, setting the selection instruction signal to the first state; Alternatively, when the data read command is a second read command and the duty cycle of the internal clock signal is not within the preset range, the selection instruction signal is set to the second state.

In some embodiments, the first read clock signal includes eight clock cycles, and the level state change edge of the second read clock signal is aligned with the rising edge of the fifth clock cycle of the first read clock signal. ; Here, the level state change edge of the second read clock signal indicates the change of the second read clock signal from a low level state to a high level state.

In some embodiments, the duty cycle module includes: a receiving module configured to receive and output the data clock signal from an external source; and an adjustment module configured to perform duty cycle adjustment on the data clock signal and output the internal clock signal.

In some embodiments, the data clock signal is a write clock signal.

In a second aspect, an embodiment of the present invention provides a control device, the control device being connected to a memory; here,

The control device transmits a data read command to the memory; configured to receive a read data signal returned by the memory and a target read clock signal, and perform latch processing on the read data signal using the target read clock signal;

Here, the target read clock signal is a first read clock signal or a second read clock signal, the first read clock signal is a pulse signal, and the second read clock signal has only one level state change edge.

In some embodiments, the control device also receives a first read clock signal returned by the memory when the data read command is a first read command, and uses the first read clock signal to read the read command. perform latch processing on the data signal; Alternatively, when the data read command is a second read command, receive a second read clock signal returned by the memory, and latch the read data signal using a level state change edge of the second read clock signal. configured to perform processing; wherein the memory includes a clock processing circuit, the second read instruction instructs to obtain a duty cycle parameter of a mode register in the clock processing circuit, and the first read instruction reads data excluding the second read instruction. Indicates a command.

In some embodiments, the control device also receives a first read clock signal returned by the memory when the data read command is a second read command, and detects a level state change edge of the first read clock signal. It is configured to perform latch processing on the read data signal using .

In a third aspect, an embodiment of the present invention provides a clock processing method and is applied to a memory, the method comprising:

Receiving an externally generated data clock signal; performing duty cycle adjustment on the data clock signal to determine an internal clock signal;

Based on the internal clock signal, determining a first read clock signal, wherein the first read clock signal is a pulse signal;

While the first read clock signal is present, generating a second read clock signal, wherein the second read clock signal has only one level state change edge; and

and outputting one of the first read clock signal and the second read clock signal as a target read clock signal.

In some embodiments, the memory includes a mode register, and the method includes:

performing duty cycle detection on the internal clock signal to obtain a duty cycle parameter; and storing the duty cycle parameter in the mode register.

In some embodiments, the memory is coupled to a control device, and outputting one of the first read clock signal and the second read clock signal as a target read clock signal includes:

When receiving a first read command transmitted by a device, determining a read data signal based on the first read command and determining the first read clock signal as a target read clock signal; and when receiving a second read command transmitted by the control device, determining the read data signal based on the second read command and determining the second read clock signal as a target read clock signal. ; Here, the target read clock signal is for latching the read data signal, the second read instruction instructs to obtain the duty cycle parameter of the mode register, and the first read instruction is for latching the read data signal, and the first read instruction is for latching the read data signal. Indicates a data read command.

In some embodiments, the memory is connected to a control device, and outputting one of the first read clock signal and the second read clock signal as a target read clock signal includes:

When receiving a first read command transmitted by the control device, determining a read data signal based on the first read command and determining the first read clock signal as a target read clock signal; When receiving a second read command sent by the control device and the duty cycle parameter is within a preset range, determine a read data signal based on the second read command, and target the first read clock signal. Determining with a read clock signal; and when receiving a second read command sent by a control device and the duty cycle parameter is not within a preset range, determine the read data signal based on the second read command, and determine the second read clock signal. It includes determining as a target read clock signal; Here, the target read clock signal is for latching the read data signal, the second read instruction instructs to obtain the duty cycle parameter of the mode register, and the first read instruction is for latching the read data signal, and the first read instruction is for latching the read data signal. Indicates a data read command.

In a fourth aspect, an embodiment of the present invention provides an electronic device, the electronic device including at least a memory according to the first aspect and a control device according to the second aspect.

Embodiments of the present invention provide a memory, a control device, a clock processing method, and an electronic device, wherein the memory includes a clock processing circuit, and the clock processing circuit receives an externally generated data clock signal; a duty cycle module configured to perform duty cycle adjustment on a data clock signal and output an internal clock signal; a first clock generation module configured to receive an internal clock signal and, based on the internal clock signal, output a first read clock signal, wherein the first read clock signal is a pulse signal; a second clock generation module configured to generate and output a second read clock signal while the first read clock signal is present, wherein the second read clock signal has only one level state change edge; and a selection module configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as the target read clock signal. Accordingly, when a duty cycle abnormality change occurs in the internal clock signal of the memory, the second read clock signal having a single level change edge can be selected and used as the target read clock signal to avoid data latch failure.

Figure 1 is an example operation sequence diagram of the MRR instruction.
Figure 2 is an example structure of a clock processing circuit.
Figure 3 is an example waveform of a read clock signal.
Figure 4 is an exemplary structure diagram of a memory provided in an embodiment of the present invention.
Figure 5 is Figure 1 showing an example of the local structure of a clock processing circuit provided in an embodiment of the present invention.
Figure 6 is Figure 2, an example of the local structure of a clock processing circuit provided in an embodiment of the present invention.
Figure 7 is an example signal waveform of data latch processing provided in an embodiment of the present invention.
Figure 8 is an exemplary work process diagram of a clock processing circuit provided in an embodiment of the present invention.
Figure 9 is an exemplary structural diagram of a control device provided in an embodiment of the present invention.
Figure 10 is an exemplary flow diagram of a clock processing method provided in an embodiment of the present invention.
Figure 11 is an exemplary structural diagram of an electronic device provided in an embodiment of the present invention.

Below, the technical solutions of the embodiments of the present invention will be clearly and completely explained by combining the drawings of the embodiments of the present invention. It should be understood that the specific embodiments described herein are merely for interpreting the related application and are not limiting to the application. It should also be noted that, for convenience of explanation, the drawings only show portions related to the related application.

Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as commonly understood by a person skilled in the art. The terms used in the present invention are merely for explaining the purpose of the embodiments of the present application and are not intended to limit the embodiments of the present invention.

In the description below, references are made to “some embodiments”, which describe a subset of all possible embodiments, but “some embodiments” may be the same subset or a different subset of all possible embodiments, provided there is no conflict. It is understandable that they can be combined with each other.

The terms “first/second/third” mentioned in the embodiments of the present invention are only for distinguishing similar objects and do not indicate a specific order of objects, and can be understood as “first/second/third.” “The specified order or sequence may be interchanged where permitted, so that the embodiments of the invention described herein may be practiced in sequences other than those shown or described herein.

DRAM (Dynamic Random Access Memory): Dynamic random access memory

Synchronous Dynamic Random Access Memory (SDRAM): Synchronous dynamic random access memory

MRR (Mode Register Read): Mode register read command

Mbps (Million bits per second): Megabits per second

N-Metal-Oxide-Semiconductor (NMOS): N-type channel field-effect transistor

PMOS (P-Metal-Oxide-Semiconductor): N-type channel field-effect transistor

In memory (e.g. DRAM), the MRR instruction and the normal read instruction adopt exactly the same sequence of operations. Referring to Figure 1, an example operation sequence of the MRR instruction is shown. In Figure 1, T0, T1... are intended to represent different clock periods, Ck_c and Ck_t are a pair of differential clock signals, CS is a chip select signal, CA is a command address signal, COMMAND indicates the operation command, DQ[7:0] is the data signal of 8 bits of memory, DQ[15:0] is the data signal of 16 bits of memory, and the data clock signal WCK is the host of the electronic device ( It is an external write clock signal sent by the host to the memory, and can be expressed as a single signal or a pair of differential clock signals WCK_c and WCK_t at different circuit locations; The read clock signal RDQS is a clock signal output from the memory to an electronic device, and can be expressed as a single signal or a pair of differential clock signals RDQS_c and RDQS_t at different circuit locations. Specifically, after the memory receives the MRR instruction sent by the CPU, it generates a data signal DQ (can be referred to as a read data signal) and generates a read clock signal RDQS using the data clock signal WCK received from the outside. can be created. In the process of executing the data read instruction, the memory jointly returns the read data signal DQ and the read clock signal RDQS to the CPU, and then the CPU uses the read clock signal RDQS to latch the read data signal DQ to obtain the required data. Acquire. In addition, Figure 1 is a standard sequence prescribed according to the Electronic Device Engineering Design Council (JEDEC) standard, of which the meaning of each signal, the principles of related changes, and some of the unmentioned noun abbreviations are understood by referring to the industry standard document JEDEC. Since it is unrelated to the technical solution of the embodiments of the present invention and does not affect the technician's understanding of the embodiments of the present invention, it will not be described.

A clock processing circuit is installed in the memory, and adjustments are made to the duty cycle of the data clock signal WCK0 (including a pair of complementary signals WCK_c/WCK_t), so that the duty cycle of the data clock signal WCK0 meets the requirements. . Referring to Figure 2, an example structure of a clock processing circuit is shown. As shown in Figure 2, in the clock processing circuit, the receiving module is configured to receive the data clock signal WCK0 from the outside, and the adjusting module performs duty cycle adjustment on the data clock signal WCK to obtain the internal clock signal WCK1; , the detection module is configured to detect the duty cycle parameter of the internal clock signal WCK1 and store it in the mode register. At the same time, while the memory is performing duty cycle adjustment, the CPU sends an MRR instruction to read the duty cycle parameter in the mode register to determine the next step of operation. As another example, as shown in Figure 2, assuming that the duty cycle of the externally input data clock signal WCK0 is 57%, which is the upper limit specified by JEDEC, in the initial stage of duty cycle adjustment, the duty cycle adjustment module We increased the duty cycle of the data clock signal WCK0 by 7 units (the upper limit specified by JEDEC, each unit being 5 picoseconds), i.e. added 35 picoseconds, which reduces the duty cycle by 15% at a rate of 8533 Mbps. It is the same as increasing, and at this time, the duty cycle of the internal clock signal WCK1 in the memory reaches 72%, and the duty cycle of the read clock signal RDQS generated using this also reaches 72%. At this time, referring to FIG. 3, an exemplary waveform of a read clock signal is shown. As shown in Figure 3, the read clock signal RDQS, whose duty cycle reaches 72%, is attenuated through the channel during transmission and is severely deformed when it reaches the CPU receiving end, making it difficult to accurately identify it by the CPU. That is, the MRR instruction obtains incorrect data, ultimately resulting in duty cycle regulation failure. As memory speeds become higher, this problem becomes more severe.

Based on this, an embodiment of the present invention provides a memory, the memory including a clock processing circuit, the clock processing circuit receiving an externally generated data clock signal; a duty cycle module configured to perform duty cycle adjustment on a data clock signal and output an internal clock signal; a first clock generation module configured to receive an internal clock signal and, based on the internal clock signal, output a first read clock signal, wherein the first read clock signal is a pulse signal; a second clock generation module configured to generate and output a second read clock signal while the first read clock signal is present, wherein the second read clock signal has only one level state change edge; and a selection module configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as the target read clock signal. Accordingly, when a duty cycle abnormality change occurs in the internal clock signal of the memory, the second read clock signal having a single level change edge can be selected and used as the target read clock signal to avoid data latch failure.

Each embodiment of the present invention will be described below by combining the drawings.

In one embodiment of the present invention, referring to FIG. 4, an exemplary structure diagram of the memory 10 provided in the embodiment of the present invention is shown. As shown in FIG. 4, the memory 10 includes a clock processing circuit 20, and the clock processing circuit 20 includes,

Receive an externally generated data clock signal; a duty cycle module 21 configured to perform duty cycle adjustment on the data clock signal and output an internal clock signal;

A first clock generation module 22 configured to receive an internal clock signal and, based on the internal clock signal, output a first read clock signal, where the first read clock signal is a pulse signal;

A second clock generation module 23 configured to generate and output a second read clock signal while the first read clock signal is present, the second read clock signal having only one level state change edge; and

and a selection module 24 configured to receive a first read clock signal and a second read clock signal, and output one of the first read clock signal and the second read clock signal as a target read clock signal.

It should be noted that, in an embodiment of the present invention, the memory 10 may be various types of semiconductor memory, for example, DRAM, SDRAM, double rate DRAM, low power double rate DRAM, etc.

A first clock generation module 22 and a second clock generation module 23 are installed simultaneously in the memory 10, and the first clock generation module 22 has a plurality of pulses according to a data clock signal received from the outside. A first read clock signal may be generated, and the second clock generation module 23 may generate a second read clock signal having only one level state change edge. Accordingly, in different working scenarios, the first read clock signal or the second read clock signal can be selected as the target read clock signal and sent to the CPU to implement data latch processing. In particular, since the second read clock signal is not affected by the occurrence of abnormal changes in the duty cycle of the internal clock signal, accurate latch of data can still be ensured even in a scenario where the abnormal changes in the duty cycle of the internal clock signal are relatively large.

Here, there are various possibilities for the specific waveform and generation process of the second read clock signal, and the embodiments of the present invention are only used as examples in the future and do not constitute specific limitations. In particular, the level change edge of the second read clock signal and the end time of valid data in the read data signal are synchronized, or the level change edge of the second read clock signal is advanced before the end time of valid data in the read data signal, Ensures accurate latch of data. Additionally, the level change edge may be a rising edge (i.e., the second read clock signal changes from a low level to a high level) or a falling edge (i.e., the second read clock signal changes from a high level to a low level).

It should be noted that, as shown in Figure 5, the duty cycle module 21 includes two parts: a reception module 211 and an adjustment module 212, the specific implementation can refer to the future description; The first clock generation module 22 may be composed of a logic element and a delay unit to implement delay matching and the standard sequence specified in the JEDEC standard; The second clock generation module 23 may be configured as a frequency divider consisting of a D-type trigger and an inverter, and the selection module 24 may be implemented through an alternative data selector.

In some embodiments, the data clock signal is a write clock signal received from an external source, hereinafter indicated as WCK0; The internal clock signal is a write clock signal through duty cycle adjustment inside the memory, and will be referred to as WCK1 in the future; The target read clock signal is the read operation data strobe signal, hereinafter referred to as RDQS; The read data signal can be represented as DQ.

In some embodiments, as shown in Figure 5, clock processing circuit 20 further includes a detection module 25 and a mode register 26; Here, the detection module 25 is configured to receive the internal clock signal WCK1, perform duty cycle detection on the internal clock signal WCK1, and output a duty cycle parameter; Mode register 26 is configured to receive and store duty cycle parameters.

It should be noted that the detection module 25 may be composed of a logic gate, a transmission gate, a capacitance and a signal comparator.

In some embodiments, as shown in Figure 6, the selection module 24 also receives a selection instruction signal, and when the selection instruction signal is in the first state, it converts the first read clock signal to the target read clock signal RDQS. output as; Alternatively, when the selection instruction signal is in the second state, it is configured to output the second read clock signal as the target read clock signal RDQS.

Here, the selection module 24 may be an alternative data selector and therefore outputs a first read clock signal or a second read clock signal depending on the state of the selection instruction signal.

In some embodiments, memory 10 receives a data read command; Based on the data read command, it is configured to output a read data signal DQ and output a target read clock signal RDQS through the clock processing circuit 20; Here, the target read clock signal RDQS is for latching the read data signal DQ, and the level state change edge of the second read clock signal indicates the end time of valid data in the read data signal DQ.

In other words, in an electronic device including a memory 10, the CPU of the electronic device commands an operation instruction to the memory 10 to implement data writing or data reading. In the process of reading data, the CPU sends a data read command to the memory 10, and the memory 10 generates a read data signal DQ (carrying the read parameters required by the CPU) according to the data read command, and clocks A target read clock signal RDQS is generated through the processing circuit 20. Accordingly, both the read data signal DQ and the target read clock signal RDQS are transmitted to the CPU, and the CPU performs latch on the read data signal using the target read clock signal RDQS, making it convenient to obtain required parameters through decoding in the future. .

In an embodiment of the present invention, data read instructions are divided into two types: first read instructions and second read instructions. The second read command instructs the clock processing circuit 20 to obtain the duty cycle parameter of the mode register 26, and the first read command indicates a data read command excluding the second read command.

In a specific embodiment, the memory 10 also sets the selection instruction signal to the first state when the data read command is the first read command; Alternatively, when the data read command is a second read command, the selection instruction signal is configured to be set to the second state.

As described above, when the data read command is to read the duty cycle parameter in mode register 26, memory 10 may be in the process of adjusting the duty cycle, and in certain cases, may cause abnormal changes to the internal clock signal WCK1. If this occurs, for example, when the duty cycle of the internal clock signal WCK1 reaches 72%, an abnormal change also occurs in the first read clock signal, and the CPU uses the first read clock signal to Performing a latch may produce erroneous results. In an embodiment of the present invention, when the data read command is to read the duty cycle parameter in the mode register 26, the second read clock signal is output as the target read clock signal RDQS, and the second read clock signal has one Since there is only a level change edge of Cycle parameters can be obtained.

Additionally, in order to reduce power consumption, when the data read command is the first read command, the second clock generation module 23 may not be enabled, that is, the second clock generation module 23 does not work. , the goal of reducing current and power consumption can be reached.

In another specific embodiment, the memory 10 also sets the selection instruction signal to the first state when the data read command is the first read command; Alternatively, when the data read command is a second read command and the duty cycle of the internal clock signal WCK1 is within the preset range, the selection instruction signal is set to the first state; Alternatively, when the data read command is a second read command and the duty cycle of the internal clock signal WCK1 is not within a preset range, the selection instruction signal is configured to be set to the second state.

In other words, if the data read command is to read the duty cycle parameter in the mode register 26, and the duty cycle of the internal clock signal WCK1 meets the requirement, then the first read clock signal is not abnormally changed; The CPU still uses the first read clock signal to latch on the read data signal.

Below, the specific waveform of the second read clock signal and the latch process of the read data signal will be explained using an example where the DRAM has a burst length of 16 and has 16 DQ terminals.

For the second read command, the previous 8 bits of the read data signal DQ carry valid data, and are indicated as DQ <7:0>. According to the provisions of the JEDEC standard, the previous 8 bits (previous 4 clock cycles) of the target read clock signal RDQS carry the parameter values of the mode register (MR Content), and the subsequent 8 bits (subsequent 4 clock cycles) carry indifferent data. Send (Valid). At this time, the first read clock signal includes eight clock cycles, and the level state change edge of the second read clock signal is aligned with the rising edge of the fifth clock cycle in the first read clock signal; Here, the level state change edge of the second read clock signal indicates the change of the second read clock signal from a low level state to a high level state.

In other words, as shown in (1) of FIG. 7, when the first read clock signal is used as the target read clock signal RDQS, the CPU uses the signal edge of the target read clock signal RDQS to generate the read data signal DQ < 7:0>, the data latched by the previous 4 clock cycles is MR Content, and the data latched by the subsequent 4 clock cycles Valid is not used; As shown in (2) of FIG. 7, when the second read clock signal is used as the target read clock signal RDQS, the CPU uses the rising edge of the second read clock signal to generate the read data signal DQ <7: Perform latch on 0> to obtain MR Content.

In some embodiments, as shown in Figure 5 or Figure 6, the duty cycle module 21 includes a reception module 211 configured to receive and output a data clock signal WCK0 from the outside; and an adjustment module 212 configured to perform duty cycle adjustment on the data clock signal WCK0 to output an internal clock signal WCK1.

It should be noted that adjustment module 212 is configured to perform duty cycle adjustment. When duty cycle adjustment is started, the default setting of the adjustment module 212 is to cause the duty cycle of the data clock signal WCK0 to be increased uniformly, and according to the provisions of JEDEC, the upper limit of the increase in duty cycle is 7 units (step), That is, 35 picoseconds.

The receiving module 211 may be implemented through a signal receiver composed of elements such as NMOS and PMOS, and the adjustment module 212 may be implemented through cascaded delay units, and each delay unit is composed of NMOS and PMOS, Forward/backward adjustment of the rising edge of the data clock signal WCK0 is implemented, and/or forward/backward adjustment of the falling edge of the data clock signal WCK0 is implemented, and finally the duty cycle of the data clock signal WCK0 is adjusted.

The possible operation scenarios provided below illustrate the technical effects of the embodiments of the present invention. As shown in (a) of Figure 8, the duty cycle of the externally generated data clock signal WCK0 is 57%, and when the duty cycle adjustment process begins, the duty cycle of the data clock signal WCK0 is defaulted to 7 units ( 35 picoseconds), if the speed of the memory is 8633Mbps, then the duty cycle of the internal clock signal WCK1 continues to increase by 15% on the basis of the data clock signal WCK0, that is, the duty cycle of the internal clock signal WCK1 is 72% reaches. As shown in (b) of FIG. 8, at this time, the CPU transmits a second read command to the memory, the selection instruction signal is set to the second state, and the memory 10 performs a second read command with a single signal edge. By using the clock signal as the target read clock signal RDQS, the CPU uses the second read clock signal to latch on the read data signal DQ <7:0> to obtain the correct duty cycle parameter, thereby performing a duty cycle adjustment operation. success can be guaranteed.

In summary, an embodiment of the present invention provides a memory, the memory including a clock processing circuit, the clock processing circuit receiving an externally generated data clock signal; a duty cycle module configured to perform duty cycle adjustment on a data clock signal and output an internal clock signal; a first clock generation module configured to receive an internal clock signal and, based on the internal clock signal, output a first read clock signal, wherein the first read clock signal is a pulse signal; a second clock generation module configured to generate and output a second read clock signal while the first read clock signal is present, wherein the second read clock signal has only one level state change edge; and a selection module configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as the target read clock signal. Accordingly, when a duty cycle abnormality change occurs in the internal clock signal, the second read clock signal having a single level change edge can be selected and used as the target read clock signal to avoid data latch failure.

In another embodiment of the present invention, referring to FIG. 9, an exemplary structural diagram of a control device 30 provided in an embodiment of the present invention is shown. As shown in Figure 9, the control device 30 is connected to the memory 10; here,

The control device 30 transmits a data read command to the memory 10; configured to receive the read data signal DQ and the target read clock signal RDQS returned by the memory 10, and perform latch processing on the read data signal DQ using the target read clock signal RDQS; Here, the target read clock signal RDQS is a first read clock signal or a second read clock signal, the first read clock signal is a pulse signal, and the second read clock signal has only one level state change edge.

It should be noted that the control device 30 may be a CPU. Specifically, the control device 30 transmits a command through the memory controller of the memory 10 to read data from the mode register/memory array in the memory 10. Specifically, when reading data in the memory 10, the CPU sends a data read command to the memory through the command bus and the data bus, and the memory 10 interprets the data read command and executes the corresponding read operation. , obtain the read data signal. In addition, the memory also generates a target read clock signal, allowing the control device 30 to perform latch processing on the read data signal DQ using the target read clock signal RDQS to obtain the required data.

4 to 6, in the embodiment of the present invention, the target read clock signal RDQS received by the control device 30 from the memory 10 may have a plurality of pulses or only one level state change edge. . In other words, when the duty cycle of the first read clock signal changes abnormally, the memory 10 adopts the second read clock signal with only one level state change edge and uses it as the target read clock signal RDQS to control the control device ( 30), the read data signal DQ is accurately latched.

In a specific embodiment, the control device 30 also receives the first read clock signal returned by the memory 10 when the data read command is the first read command, and uses the first read clock signal to perform latch processing on the read data signal DQ; Alternatively, when the data read command is a second read command, receive the second read clock signal returned by the memory 10 and latch the read data signal DQ using the level state change edge of the second read clock signal. It is configured to perform processing.

It should be noted that the memory 10 includes a clock processing circuit 20, wherein a second read instruction directs the clock processing circuit 20 to obtain a duty cycle parameter of the mode register, and the first read instruction directs the clock processing circuit 20 to obtain the duty cycle parameter of the mode register. 2 Indicates a data read command excluding the read command.

Accordingly, when the data read command is a second read command, the memory 10 may be in the process of duty cycle adjustment, and the internal clock signal WCK1 in the memory 10 may be abnormally changed, that is, the first read clock The signal is deformed, and the second read clock signal is adopted and used as the target read clock signal RDQS, making it convenient for the control device 30 to obtain accurate duty cycle parameters. Conversely, when the data read command is the first read command, both the internal clock signal WCK1 and the first read clock signal in the memory are normal. Therefore, if the first read clock signal is adopted and used as the target read clock signal RDQS, The control device 30 can obtain accurate results.

In another specific embodiment, the control device 30 also receives the first read clock signal returned by the memory 10 when the data read command is a second read command and determines the level of the first read clock signal. It is configured to perform latch processing on the read data signal DQ using a state change edge.

Accordingly, when the data read command is the second read command, the internal clock signal WCK1 and the first read clock signal in the memory 10 may still be normal, so the memory 10 also still adopts the first read clock signal to target It can be used as a read clock signal RDQS.

An embodiment of the present invention provides a control device, the control device coupled to a memory; The control device sends a data read command to the memory; configured to receive a read data signal returned by the memory and a target read clock signal, and perform latch processing on the read data signal using the target read clock signal; Here, the target read clock signal is a first read clock signal or a second read clock signal, the first read clock signal is a pulse signal, and the second read clock signal has only one level state change edge. Accordingly, when a duty cycle abnormality change occurs in the internal clock signal, the read data signal is latched using the second read clock signal having a single level change edge, thereby avoiding data latch failure.

In another embodiment of the present invention, referring to FIG. 10, an exemplary flow diagram of a clock processing method provided by the embodiment of the present invention is shown. As shown in Figure 10, the method includes the following steps.

In S401, an externally generated data clock signal is received; Duty cycle adjustment is performed on the data clock signal to determine the internal clock signal.

In S402, determine a first read clock signal based on the internal clock signal; Here, the first read clock signal is a pulse signal.

In S403, while the first read clock signal exists, generate a second read clock signal; Here, the second read clock signal has only one level state change edge.

In S404, one of the first read clock signal and the second read clock signal is output as the target read clock signal.

It should be noted that the above method is applied to the memory 10 described above. Thereby, the memory 10 can simultaneously generate the first read clock signal and the second read clock signal, and in different working scenarios, select the first read clock signal or the second read clock signal as the target read clock signal RDQS. It is sent to the CPU to implement latch processing of the data signal. In particular, the second read clock signal is not affected by the irregularity change in the duty cycle of the internal clock signal WCK1, so even in the scenario where the irregularity change in the duty cycle of the internal clock signal WCK1 is relatively large, accurate latch of the data signal can still be guaranteed. .

In some embodiments, as described above, memory 10 includes a mode register 26, and the method includes:

Perform duty cycle detection on the internal clock signal to obtain a duty cycle parameter; It further includes storing the duty cycle parameter in a mode register.

In a specific embodiment, as described above, the memory 10 is connected to the control device 30, and outputting one of the first read clock signal and the second read clock signal as a target read clock signal includes:

When receiving a first read command sent by the control device, determining a read data signal based on the first read command and determining the first read clock signal as a target read clock signal; and when a second read command transmitted from the control device is received, determining a read data signal based on the second read command and determining the second read clock signal as the target read clock signal.

Here, the target read clock signal is for latching the read data signal, the second read instruction directs obtaining the duty cycle parameter of the mode register, and the first read instruction directs the data read instruction excluding the second read instruction. .

In another specific embodiment, the step of outputting one of the first read clock signal and the second read clock signal as a target read clock signal includes:

When receiving a first read command sent by the control device, determining a read data signal based on the first read command and determining the first read clock signal as a target read clock signal; When receiving the second read command sent by the control device and the duty cycle parameter is located in the preset range, determine the read data signal based on the second read command, and convert the first read clock signal to the target read clock signal. deciding step; And when a 2 read command transmitted from the control device is received and the duty cycle parameter is not located in the preset range, a read data signal is determined based on the second read command, and the second read clock signal is converted to a target read clock signal. Includes decision-making steps.

An embodiment of the present invention provides a clock processing method, the method comprising: receiving an externally generated data clock signal; performing duty cycle adjustment on the data clock signal to determine an internal clock signal; Based on the internal clock signal, determining a first read clock signal, the first read clock signal being a pulse signal; generating a second read clock signal while the first read clock signal is present, the second read clock signal having only one level state change edge; and outputting one of the first read clock signal and the second read clock signal as a target read clock signal. Accordingly, when a duty cycle abnormality change occurs in the internal clock signal, the second read clock signal having a single level change edge can be selected and used as the target read clock signal to avoid data latch failure.

In another embodiment of the present invention, referring to FIG. 11, it is an exemplary structural diagram of an electronic device 50 provided in an embodiment of the present invention. As shown in FIG. 11, the electronic device 50 includes at least the memory 10 described above and the control device 30 described above.

Since memory 10 can output a first read clock signal having a plurality of pulses, or can output a second read clock signal having a single level change edge, the internal clock signal in memory 10 When a duty cycle abnormality change occurs, a second read clock signal having a single level change edge can be selected and used as the target read clock signal, and the control device 30 selects the level change edge in the second read clock signal. By performing a data latch, you can avoid obtaining incorrect data.

The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. It should be noted that, in the present invention, the term “comprising” or any other variation thereof is intended to include non-exclusive inclusion, thereby allowing a process, method, article or device comprising a set of elements to include such elements. In addition, it may be permitted to include other elements not explicitly listed, or to cause such process, method, article, or apparatus to contain unique elements. In the absence of further qualification, the phrase “one…” … An element defined by “including” does not exclude the presence of other identical elements in a process, method, article or device that includes the element. The numbers of the embodiments of the present invention are only for explanation and do not indicate superiority or inferiority of the embodiments. The methods mentioned in several method embodiments provided by the present invention can be arbitrarily combined if they do not conflict to obtain new method embodiments. The features mentioned in several product embodiments provided by the present invention can be arbitrarily combined as long as they do not conflict to obtain new product embodiments. The features mentioned in several method or device embodiments provided by the present invention can be arbitrarily combined as long as they do not conflict, to obtain new method embodiments or device embodiments. The above description is only a specific embodiment of the present invention, and the scope of protection of the present invention is not limited thereto, and those skilled in the art will understand that all changes or replacements within the technical scope disclosed in the present invention are not limited to the present invention. It will be easy to see that it must fall within the scope of protection. Therefore, the scope of protection of the present invention should be based on the scope of protection of the patent claims.

Embodiments of the present invention provide a memory, a control device, a clock processing method, and an electronic device, wherein the memory includes a clock processing circuit, and the clock processing circuit receives an externally generated data clock signal; a duty cycle module configured to perform duty cycle adjustment on a data clock signal and output an internal clock signal; a first clock generation module configured to receive an internal clock signal and, based on the internal clock signal, output a first read clock signal, wherein the first read clock signal is a pulse signal; a second clock generation module configured to generate and output a second read clock signal while the first read clock signal is present, wherein the second read clock signal has only one level state change edge; and a selection module configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as the target read clock signal. Accordingly, when a duty cycle abnormality change occurs in the internal clock signal of the memory, the second read clock signal having a single level change edge can be selected and used as the target read clock signal to avoid data latch failure.

Claims (17)

As a memory,
A clock processing circuit comprising:
Receive an externally generated data clock signal; a duty cycle module configured to perform duty cycle adjustment on the data clock signal and output an internal clock signal;
a first clock generation module configured to receive the internal clock signal and, based on the internal clock signal, output a first read clock signal, wherein the first read clock signal is a pulse signal;
a second clock generation module configured to generate and output a second read clock signal while the first read clock signal is present, wherein the second read clock signal has only one level state change edge; and
and a selection module configured to receive the first read clock signal and the second read clock signal and output one of the first read clock signal and the second read clock signal as a target read clock signal. Memory. According to paragraph 1,
The clock processing circuit further includes a detection module and a mode register,
The detection module is configured to receive the internal clock signal, perform duty cycle detection on the internal clock signal, and output a duty cycle parameter;
The mode register is configured to receive and store the duty cycle parameter. According to paragraph 2,
The selection module also receives a selection instruction signal, and when the selection instruction signal is in a first state, outputs the first read clock signal as a target read clock signal; Alternatively, when the selection instruction signal is in a second state, the memory is configured to output the second read clock signal as a target read clock signal. According to paragraph 3,
The memory receives a data read command; configured to output a read data signal based on the data read command and output the target read clock signal through the clock processing circuit;
The target read clock signal is for latching the read data signal, and a level state change edge of the second read clock signal indicates an end time of valid data in the read data signal. According to paragraph 4,
The memory also sets the selection instruction signal to a first state when the data read command is a first read command; or, when the data read command is a second read command, configured to set the selection instruction signal to a second state;
wherein the second read command instructs the clock processing circuit to obtain a duty cycle parameter of a mode register, and the first read command indicates a data read command excluding the second read command. According to clause 5,
The memory also sets the selection instruction signal to a first state when the data read command is a first read command; or,
If the data read command is a second read command and the duty cycle of the internal clock signal is within a preset range, set the selection instruction signal to the first state; or,
When the data read command is a second read command and the duty cycle of the internal clock signal is not within a preset range, the memory is configured to set the selection instruction signal to a second state. According to any one of claims 1 to 6,
The first read clock signal includes eight clock cycles, and the level state change edge of the second read clock signal is aligned with the rising edge of the fifth clock cycle of the first read clock signal;
A memory wherein a level state change edge of the second read clock signal indicates a change of the second read clock signal from a low level state to a high level state. In clause 7,
The duty cycle module is,
a receiving module configured to receive and output the data clock signal from the outside; and
A memory comprising an adjustment module configured to perform duty cycle adjustment on the data clock signal and output the internal clock signal. According to clause 8,
A memory, wherein the data clock signal is a write clock signal. As a control device,
connected to memory,
The control device transmits a data read command to the memory; configured to receive a read data signal returned by the memory and a target read clock signal, and perform latch processing on the read data signal using the target read clock signal;
The target read clock signal is a first read clock signal or a second read clock signal, the first read clock signal is a pulse signal, and the second read clock signal has only one level state change edge. controller. According to clause 10,
The control device also receives a first read clock signal returned by the memory when the data read command is a first read command, and performs latch processing on the read data signal using the first read clock signal. Do; or,
When the data read command is a second read command, receive a second read clock signal returned by the memory, and perform latch processing on the read data signal using a level state change edge of the second read clock signal. configured to perform;
The memory includes a clock processing circuit, the second read instruction directs the clock processing circuit to obtain a duty cycle parameter of a mode register, and the first read instruction includes a data read instruction other than the second read instruction. A control device characterized by giving instructions. According to clause 10,
The control device also receives the first read clock signal returned by the memory when the data read command is a second read command, and uses a level state change edge of the first read clock signal to read the read data. A control device configured to perform latch processing on a signal. As a clock processing method,
Applied to memory, the clock processing method is,
Receiving an externally generated data clock signal; performing duty cycle adjustment on the data clock signal to determine an internal clock signal;
Based on the internal clock signal, determining a first read clock signal, wherein the first read clock signal is a pulse signal;
While the first read clock signal is present, generating a second read clock signal, wherein the second read clock signal has only one level state change edge; and
A clock processing method comprising outputting one of the first read clock signal and the second read clock signal as a target read clock signal. According to clause 13,
The memory includes a mode register, and the clock processing method is:
performing duty cycle detection on the internal clock signal to obtain a duty cycle parameter; and
A clock processing method further comprising storing the duty cycle parameter in the mode register. According to clause 14,
The memory is connected to a control device, and outputting one of the first read clock signal and the second read clock signal as a target read clock signal includes:
When receiving a first read command transmitted by the control device, determining a read data signal based on the first read command and determining the first read clock signal as a target read clock signal; and
When receiving a second read command transmitted by the control device, determining the read data signal based on the second read command and determining the second read clock signal as a target read clock signal; ;
The target read clock signal is to latch the read data signal, the second read instruction is to obtain a duty cycle parameter of the mode register, and the first read instruction is to read data except the second read instruction. A clock processing method characterized by instructing instructions. According to clause 14,
The memory is connected to a control device, and outputting one of the first read clock signal and the second read clock signal as a target read clock signal includes:
When receiving a first read command transmitted by the control device, determining a read data signal based on the first read command and determining the first read clock signal as a target read clock signal;
When receiving a second read command sent by the control device and the duty cycle parameter is within a preset range, determine a read data signal based on the second read command, and target the first read clock signal. determining with a read clock signal; and
When receiving a second read command sent by a control device and the duty cycle parameter is not within a preset range, determine the read data signal based on the second read command, and determine the second read clock signal. determining a target read clock signal;
The target read clock signal is to latch the read data signal, the second read instruction is to obtain a duty cycle parameter of the mode register, and the first read instruction is to read data except the second read instruction. A clock processing method characterized by instructing instructions. As an electronic device,
The electronic device is characterized in that it includes a memory according to any one of claims 1 to 9 and a control device according to any one of claims 10 to 12.