KR100935598B1 - Circuit for Controlling Column Address and Semiconductor Memory Apparatus Using the Same - Google Patents

Abstract

The present invention outputs an address as a column address in response to a write signal and a read signal, and in response to a control signal, a column address output unit for inverting and outputting the level of the column address, and in response to a test signal and a counting enable signal. And a control unit for generating the control signal.

Column address, least significant bit address, test, data output

Description

Circuit for Controlling Column Address and Semiconductor Memory Apparatus Using the Same}

The present invention relates to semiconductor memory technology, and more particularly, to a column address control circuit and a semiconductor memory device using the same.

As semiconductor memory devices become ever faster, test equipment for testing them must also be faster. For example, it is assumed that a test is performed to determine whether data is normally stored in the semiconductor memory device and whether the stored data is normally output. In this case, the test equipment for testing the semiconductor memory device should be able to detect data at a high speed as much as the data output speed of the semiconductor memory device. That is, when the semiconductor memory device operates at a high speed, the test equipment should also operate at a high speed.

As shown in FIG. 1, a conventional semiconductor memory device outputs data A, B, C, D, E, F, G, and H in synchronization with a clock CLK. At this time, the semiconductor memory device outputs 8 bits of data A, B, C, D, E, F, G, and H at a read command. Therefore, as the frequency of the clock CLK increases, the data A, B, C, D, E, F, G, H are also output at an early timing. If the test equipment detects such 8-bit data (A, B, C, D, E, F, G, H), the test equipment should operate at high speed as indicated by the arrow indicated by A. When the test equipment operates at the low speed as indicated by the arrow indicated by B, only the 4-bit data (A, C, E, G) of the 8 bit data (A, B, C, D, E, F, G, H) can be detected. .

As a result, high speed test equipment is required to test semiconductor memory devices that output high speed data.

However, high-speed test equipment is more expensive than low-speed test equipment, which increases the cost of semiconductor memory devices.

Disclosure of Invention The present invention has been made to solve the above-described problem, and an object thereof is to provide a column address control circuit capable of performing data input / output tests using test equipment operating at a lower speed than a semiconductor memory device, and a semiconductor memory device using the same. There is this.

A column address control circuit according to an embodiment of the present invention outputs an address as a column address in response to a write signal and a read signal, and a column address output unit for inverting and outputting the level of the column address in response to a control signal, and a test. And a controller configured to generate the control signal in response to a signal and a counting enable signal.

The semiconductor memory device using the column address control circuit according to the present invention includes a data input / output circuit which inputs and outputs data corresponding to a counted address by internally counting an address when a read command or a write command is input, and a least significant bit among the counted addresses. And a column address control circuit for fixing an address to a constant level in response to a test signal, wherein when the least significant bit address is fixed to a constant level, the data input / output circuit includes the same pattern according to the address including the fixed least significant bit address. It is characterized by repeatedly outputting the data.

The column address control circuit and the semiconductor memory device using the same according to the present invention can reduce the cost of the semiconductor memory device by enabling data input / output testing even in test equipment operating at a lower speed than the semiconductor memory device.

As shown in FIG. 2, the column address control circuit according to the present invention includes a column address output unit 100 and a controller 200.

The column address output unit 100 receives the least significant bit address (hereinafter referred to as Add <2>) among the write signal WT, the read signal RD, and an internal address and receives the least significant bit address among the column addresses (hereinafter, referred to as a column). Address Yadd <2>). In addition, the column address output unit 100 receives the column address Yadd <2> and outputs the inverted column address Yadd <2> in response to a control signal ctrl.

The controller 200 receives a test signal Test and a counting enable signal icasp and outputs the control signal ctrl.

The control unit 200 disables the control signal ctrl when the test signal Test is enabled, and responds to the counting enable signal icasp when the test signal Test is disabled. Enable or disable (ctrl).

As shown in FIG. 3, the column address output unit 100 includes an output unit 110, an inversion unit 120, and a latch unit 130.

The output unit 110 outputs the address Add <2> when any one of the write signal WT and the read signal RD is enabled.

The output unit 110 includes a first switching unit 111 and a second switching unit 112.

The first switching unit 111 outputs the address Add <2> to the latch unit 130 when the write signal WT is enabled.

The first switching unit 111 includes a first inverter IV11 and a first pass gate PG11. The first inverter IV11 receives the write signal WT. The first pass gate PG11 receives the output signal of the first inverter IV11 to the first control terminal, receives the write signal WT to the second control terminal, and the address Add <2 to the input terminal. And the input terminal of the latch unit 130 is connected to the output terminal.

The second switching unit 112 outputs the address Add <2> to the latch unit 130 when the read signal RD is enabled.

The second switching unit 112 includes a second inverter IV12 and a second pass gate PG12. The second inverter IV12 receives the read signal RD. The second pass gate PG12 receives the output signal of the second inverter IV12 at the first control terminal, the read signal RD at the second control terminal, and the address Add <2> at the input terminal. ) And the input terminal of the latch unit 130 is connected to the output terminal.

When the control signal ctrl is enabled, the inverting unit 120 inverts the column address Yadd <2> and outputs the inverted portion to the latch unit 130.

The inverting unit 120 includes third and fourth inverters IV13 and IV14 and a third pass gate PG13. The third inverter IV13 receives the control signal ctrl. The fourth inverter IV14 receives the column address Yad <2>. The third pass gate PG13 receives the output signal of the third inverter IV13 at the first control terminal, receives the control signal ctrl at the second control terminal, and receives the fourth inverter IV14 at the input terminal. The input signal of the latch unit 130 is connected to the output terminal of the output signal of the input.

The latch unit 130 includes fifth to seventh inverters IV15 to IV17. The fifth inverter IV15 has a node connected to an output terminal of the first switching unit 111, the second switching unit 112, and the inverting unit 120 connected to an input terminal of the fifth inverter IV15. In the sixth inverter IV16, an output terminal of the fifth inverter IV15 is connected to an input terminal, and an input terminal of the fifth inverter IV15 is connected to an output terminal. The seventh inverter IV17 receives the output signal of the fifth inverter IV15 and outputs it as the column address Yadd <2>.

As shown in FIG. 4, the controller 200 includes eighth and ninth inverters IV21 and IV22 and a NAND gate ND21. The eighth inverter IV21 receives the test signal Test. The NAND gate ND21 receives an output signal of the eighth inverter IV21 and the counting enable signal icasp. The ninth inverter IV22 receives the output signal of the NAND gate ND21 and outputs it as the control signal ctrl.

The column address control circuit according to the embodiment of the present invention configured as described above operates as follows.

Referring to FIG. 4, in the case of a test operation, that is, when the test signal Test is enabled, the control signal ctrl is disabled. That is, when the test signal Test is enabled at the high level, the control signal ctrl is disabled at the low level.

Referring to FIG. 3, in the case of a read operation, that is, when the read signal RD is enabled at a high level, the level of the address Add <2> is stored in the latch unit 130 and stored in the latch unit 130. The level is output to the column address (Yadd <2>). For example, assume that the level of the address Add <2> is a high level. When the read signal RD is enabled, the latch unit 130 stores a high level and outputs the column address Yadd <2> at a high level. In this case, since the control signal ctrl is disabled at the low level, the inversion unit 120 does not affect the latch unit 130 in the off state.

As a result, in the column address control circuit according to the present invention, the read signal RD is enabled during the test, and the level stored in the latch unit 130 is fixed to the level of the column address Yadd <2>.

The operation of the semiconductor memory device to which the column address control circuit according to the present invention is described will now be described with reference to FIG. 5. In this case, the semiconductor memory device described above operates in burst length 8 and outputs 8-bit data in one read command.

Before describing the operation of the semiconductor memory device to which the column address control circuit according to the present invention is applied, the operation of the conventional semiconductor memory device will be described with reference to FIG. 1.

As shown in FIG. 1, when the read command Read is input, 8-bit data A, B, C, D, E, F, G, and H synchronized with the clock CLK are output. At this time, the semiconductor memory device counts internal addresses and outputs data corresponding to the counted internal addresses. At least three counted internal addresses are required to output 8-bit data, and the counted internal addresses are limited to three column addresses (Yadd <2: 4>), as shown in Table 1 below. Yadd <4> is the most significant bit address of the column address and Yadd <2> is the least significant bit address of the column address.

Table 1. 0: low, 1: high

Yadd <4> Yadd <3> Yadd <2> Data output 0 0 0 A One 0 0 B 0 One 0 C One One 0 D 0 0 One E One 0 One F 0 One One G One One One H

As described above, the conventional semiconductor memory device counts an internal address during a test or a non-test, and outputs the counted internal address as a column address (Yadd <2: 4>) and corresponds to the column address (Yadd <2: 4>). The data was output.

The semiconductor memory device including the column address control circuit according to the present invention outputs data through the operations shown in Table 1 when the test is not a test. At this time, the counting signal icasp is enabled when the level of Yadd <4> transitions fourth or when the level of Yadd <3> transitions second. As a result, the enabled counting signal icasp turns on the inverting unit 120 (see FIG. 3) as the enabled control signal ctrl. Accordingly, the low level (indicated by 0) of the fed back Yadd <2> is inverted and thus the level of Yadd <2> output from the latch unit 130 becomes a high level (indicated by 1). On the other hand, during the test, data is output through the operation shown in Table 2.

Table 2. 0: low, 1: high

Yadd <4> Yadd <3> Yadd <2> Data output 0 0 0 (1) A (E) One 0 0 (1) B (F) 0 One 0 (1) C (G) One One 0 (1) D (H) 0 0 0 (1) A (E) One 0 0 (1) B (F) 0 One 0 (1) C (G) One One 0 (1) D (H)

The column address control circuit according to the present invention fixes the level of the internal address Add <2> at the time of enabling the read signal RD and outputs it as the column address Yadd <2>. That is, even if the test signal Test is enabled and the counting enable signal icasp is enabled, the control signal ctrl is not enabled. Therefore, the inverting unit 120 that receives the disabled control signal ctrl does not output the inverted level of Yadd <2> fed back to the latch unit 130. As a result, the latch unit 130 maintains a predetermined level when the read signal RD is enabled. When the semiconductor memory device outputs data through such an operation, the 8-bit data repeatedly outputs 4-bit data.

Accordingly, as illustrated in FIG. 5, when sensing data in an arrow indicated by a dotted line, the semiconductor memory device may be tested.

In the semiconductor memory device having the column address control circuit according to the present invention, the 8-bit data A, B, C, D, If the operation to output E, F, G, H is fixed to 4-bit data (Yadd <2> = 0) at the same address, the data pattern is A, B, C, D, A, B, C, D or Yadd. When < 2 > = 1 is fixed, the data pattern switches to the operation of repeatedly outputting E, F, G, H, E, F, G, H).

As a result, a semiconductor memory device that outputs data in a data pattern as in the present invention may be tested using test equipment that detects data at a lower speed than that of outputting data.

When not in the test, when the write signal WT is enabled, the level of the internal address Add <2> is stored and output as the level of the column address Yadd <2>. When the counting enable signal icasp is enabled, the column address Yadd <2> is inverted and output. In addition, the internal address Add <2> is fixed when the write signal WT is enabled in the test, and the level of the column address Yadd <2> does not change even when the counting enable signal icasp is enabled. .

Although the foregoing has been described using an example of a burst length 8 (8-bit data output per lead instruction) as an embodiment of the present invention, the present invention is not limited thereto, and the data pattern is determined by fixing the least significant bit address among the column addresses during the test. Since it is the principle of the present invention, it is obvious that it can be easily applied to an operation such as burst length 4 or burst length 16 using the same.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a timing diagram of a semiconductor memory device according to the prior art;

2 is a configuration diagram of a column address control circuit of a semiconductor memory device according to the present invention;

3 is a detailed configuration diagram of the column address output unit of FIG. 2;

4 is a detailed configuration diagram of the control unit of FIG. 2;

5 is a timing diagram of a semiconductor memory device to which the column address control circuit of the present invention is applied.

<Description of the symbols for the main parts of the drawings>

100: column address output unit 200: control unit

Claims (14)

A column address output unit for outputting an address as a column address in response to a write signal and a read signal, and inverting and outputting the level of the column address in response to a control signal; And And a controller configured to generate the control signal in response to a test signal and a counting enable signal. The method of claim 1, The column address output unit And inverting the level of the column address when the control signal is enabled, and outputting the level of the column address as it is when the control signal is disabled. The method of claim 2, The column address output unit An output unit configured to output the received address when any one of the write signal and the read signal is enabled; An inversion unit inverting and outputting the column address in response to the control signal, and And a latch unit which stores the output of the output unit and the inverter and outputs the outputs as the column addresses. The method of claim 3, wherein The output unit A first switching unit outputting the address in response to the write signal, and And a second switching unit configured to output the address in response to the read signal. The method of claim 3, wherein The inversion unit And a switching unit for inverting and outputting the column address in response to the control signal. The method of claim 1, The control unit And disabling the control signal when the test signal is enabled, and enabling or disabling the control signal in response to the counting enable signal when the test signal is disabled. Circuit. A data input / output circuit for inputting / outputting data corresponding to the counted address by internally counting an address when a read command or a write command is input; And A column address control circuit configured to fix the least significant bit address among the counted addresses to a predetermined level in response to a test signal, And when the least significant bit address is fixed at a predetermined level, the data input / output circuit repeatedly outputs data having the same pattern according to an address including the fixed least significant bit address. The method of claim 7, wherein The column address control circuit And output the counted least significant bit address when the test signal is disabled, and output the least significant bit address fixed to a constant level when the test signal is enabled. The method of claim 8, The column address control circuit A controller configured to generate a control signal in response to the test signal and the counting enable signal, and And an address output unit for inverting and outputting the least significant bit address in response to the control signal. The method of claim 9, The control unit And disabling the control signal when the test signal is enabled and enabling or disabling the control signal in response to the counting enable signal when the test signal is disabled. The method of claim 9, The address output unit And inverting the least significant bit address when the control signal is enabled, and outputting the least significant bit address when the control signal is disabled. The method of claim 11, The address output unit An output unit configured to receive and output the least significant bit address in response to a read or write signal, An inverter which receives the least significant bit address in response to the control signal and inverts the least significant bit address to be output; And a latch unit configured to receive and store outputs of the output unit and the inverter, and output the output as the least significant bit address. The method of claim 12, The output unit A first switching unit outputting the least significant bit address in response to the write signal; And a second switching unit configured to output the least significant bit address in response to the read signal. The method of claim 12, The inversion unit And a switching unit inverting and outputting the least significant bit address in response to the control signal.

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