KR20070041956A - Semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, comprising: an internal control signal generator that decodes externally applied command signals and outputs an internal control signal, and performs a refresh operation internally in a DRAM and counts each row address sequentially, During the test, an internal address generator that generates a refresh address and then latches and outputs an internal address while limiting the increase of the refresh address count by a predetermined number of times, and a memory cell including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines. In the array and normal mode, a plurality of word lines are sequentially accessed, and in a test mode, a row address decoder for decoding one word line repeatedly for a predetermined number of times is provided.

Accordingly, the present invention can implement a semiconductor memory test operation in a short cycle even in low frequency devices by implementing a DRAM operation in a low frequency device in a test mode capable of repeatedly accessing the same word line internally.

Description

Semiconductor memory device

1 is a block diagram showing the configuration of a semiconductor memory device for performing a conventional refresh operation.

2 is a block diagram showing the structure of a conventional refresh address counter.

FIG. 3 is an operation timing diagram for explaining the count operation for the conventional refresh address counter shown in FIG.

4 is an operation timing diagram for explaining a row address disturb test apparatus of a conventional semiconductor memory.

Fig. 5 is a block diagram showing the configuration of a semiconductor memory device performing a refresh address count operation for a short period row address disturb test of the present invention.

Fig. 6 is a block diagram showing the configuration of the refresh address counter section of the present invention.

FIG. 7 is an operation timing diagram for explaining the count operation for the refresh address counter of the present invention shown in FIG.

Fig. 8 is an operation timing diagram for explaining the internal operation of the semiconductor by the short address row address test apparatus of the semiconductor memory device of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that develops a test mode to enable row address disturbance in a short period.

The information in the DRAM is stored as charge accumulated in the capacitors in the cell, and only temporary storage is possible. Therefore, these DRAMs need to be periodically refreshed by special external circuits to prevent data stored in the memory cells from being changed by leakage current, and the external refresh circuit drives each row of the DRAM once within the refresh time interval. This is done by continuously changing the internal address by a command signal applied from the outside.

The typical refresh frequency is once every few ms, and the CPU cannot use the memory during the refresh cycle, and the memory interface adjustment circuit must adjust the memory requests of the CPU and the requests from the refresh circuit.

Thus, refresh cycles can be programmed or software controlled to completely disable refresh, and during precharge time the CPU can't access the memory, resulting in 6-12% bandwidth loss for overall system operation.

Modern synchronous DRAM devices (SDRAMs) generally use an " auto-refresh " mode to refresh one row of a DRAM memory cell array each time an auto refresh operation is initiated by an external memory controller. The internal refresh low counter increments low for continuous auto refresh operation and returns to the top when the end of the array is reached.

1 is a block diagram showing a configuration of a semiconductor memory device performing a conventional refresh operation. The internal control signal generator 10, the internal refresh operation unit 20, the refresh address counter unit 30, the address latch 40, The row address decoder 50 and the memory cell array 50 are configured.

The internal refresh unit 20 includes a self refresh generator 21, an auto refresh generator 25, a self refresh pulse generator 22, an active generator 23, and a precharge generator 24, and a refresh address counter unit. 30 includes a counter pulse generator CNTP and a refresh address counter 31.

Fig. 2 is a block diagram showing the structure of a conventional refresh address counter, which is composed of a counter pulse generator CNTP and n + 1 counter generators CNT0 to CNTn.

FIG. 3 is an operation timing diagram for explaining the count operation for the conventional refresh address counter shown in FIG. 2, where CNTP is a waveform of a counter pulse generator, and CNT0 to CNTn are respective counters within the refresh address counter 31. FIG. The waveform of the generator.

In FIG. 1, when the internal control signal generator 10 decodes command signals applied from the outside and outputs an internal control signal, the refresh internal operation unit 20 performs a refresh operation internally in the DRAM, and the refresh address counter unit ( 30) sequentially counts each row address and outputs a row address.

After that, when one row address finishes refreshing, the refresh address counter 31 counts up one bit to prepare the next refresh cycle as shown in FIG. 3, where CNTn is the nth square of 2 of CNT0. The address information applied to the address latch 40 is output while having a double cycle.

The address latch 40 latches the refresh address to output an internal address, the row address decoder 50 decodes the internal address to sequentially access a plurality of word lines, and the memory cell array 60 stores the plurality of words. Write or read data to a plurality of memory cells connected between a line and a plurality of bit lines.

Next, FIG. 4 is an operation timing diagram for explaining a row address disturb test apparatus of a conventional semiconductor memory. Referring to FIG. 4, a conventional row address disturb test apparatus will be described below.

The disturb test uses a test pattern that detects a soft error in a semiconductor memory test, and checks whether peripheral cell information changes as the same address is repeatedly read for cells that normally operate.

In Fig. 4, tRC is given as 720ns as the time required for the auto refresh operation to be completed, and tCC is 240ns as the semiconductor internal system clock. In the rising transition of the system clock, the word line active, write, and precharge operations are completed once during the auto refresh cycle, and the operation is repeated.

However, in low frequency equipment such as burn-in equipment, which stresses the voltage and ambient temperature more severely than actual conditions in order to detect early defects in DRAM, the rise transition time and fall transition time to ensure stable semiconductor operation. Consider that these are 50ns each.

Therefore, since the system clock must be 240 ns or more, there is a problem that it is impossible to perform word line disturb with 100 ns or less in which the auto refresh cycle is short.

Disclosure of Invention An object of the present invention is to provide a semiconductor memory device capable of dynamic row address disturb using a short auto refresh cycle when testing a semiconductor memory in a low frequency device of 5 MHz or less.

In other words, by developing a test mode to enable word line active and precharge operation in a short period of 100ns or less, the auto refresh cycle enables screening (removal) of dynamic refresh failures caused by short auto refresh cycles in low frequency equipment. have.

In order to achieve the above object, the present invention includes an internal control signal generator, an internal address generator, a row address decoder, and a memory cell array, and the internal address generator includes a refresh internal operation part, a refresh address counter part, a count blocking part, and an address. It consists of a latch.

In the present invention, the refresh address count blocking unit prevents the pulse of the counter pulse generator from entering the row address decoder by a combination of the semi-logical sum of the output of the refresh address counter unit and the output of the mode register set, and the oscillator counter in the conventional refresh address counter configuration. And adding two NOR gates to semi-logically combine the outputs of the second counter generator and the oscillator counter so that the pulses of the counter generator are reset in the test mode, thereby limiting the number of count occurrences.

Hereinafter, a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

Fig. 5 is a block diagram showing the configuration of a semiconductor memory device performing a refresh address count operation for a short period row address disturb test of the present invention. The internal control signal generator 100, the internal address generator 500, and the row address are shown. The decoder 600 includes a memory cell array 700, and the internal address generator 500 includes a refresh internal operation unit 200, a refresh address counter unit, a count blocking unit 300, and an address latch 400. do.

The internal refresh unit 200 includes a self refresh generator 210, an auto refresh generator 250, a self refresh pulse generator 220, an active generator 230, and a precharge generator 240, and a refresh address counter unit. The count blocking unit 300 includes a refresh address counter 310 and two NOR gates NOR1 and NOR2. The refresh address counter 310 includes a counter pulse generator CNTP, a mode register 311, It consists of a refresh address counter 312.

The function of each of the blocks shown in FIG. 5 will be described below.

The internal control signal generator 100 decodes the signals applied from the outside to generate the mode register set MRS, the first refresh pulse PRFH1, and the active pulse PRB, and the refresh internal operation unit 200 controls the internal control. Upon receiving the decoded signal from the signal generator 100, the DRAM enters the self refresh mode to generate a self refresh pulse, and internally performs active and precharge operations without an external command.

The counter pulse generator CNTP receives the first refresh pulse PRFH1 from the refresh address counter unit and the count block unit 300 to generate a counter pulse. The refresh address counter 312 receives a counter pulse to each row. The refresh address is generated while increasing the row address count by 1 bit for the address.

The address latch 400 receives a refresh address, a refresh operation signal PRD, and an auto precharge pulse PAPB to output an internal address, and the row address decoder 600 receives an internal address to receive a plurality of words in a normal mode. The lines are sequentially accessed, and in the test mode, the word lines WL of each of the memory cell arrays 700 are decoded so as to repeatedly access one word line four or eight times.

The memory cell array 700 stores the data DIN in the memory cell MC connected between the selected word line WL and the bit line BL in the write operation, and selects the selected word line WL in the read operation. The data DOUT is output from the memory cell MC connected between the bit line BL and the bit line BL.

On the other hand, the mode register 311 in the refresh address counter and the count block 300 is a device for programming and storing data for controlling various operation modes of the semiconductor memory, and setting the test mode by setting the semiconductor memory test mode. The first NOR gate NOR1 receives the output of the refresh address counter 312 and the mode register 311, and the second NOR gate NOR2 receives the output of the first NOR gate NOR1 and the mode register 311. ) Is outputted to the address latch 400.

Therefore, in the semiconductor memory test mode, the pulse generated at the refresh address counter 312 by the set of mode registers 311 is not directly applied to the address latch 400 as conventionally, so that the refresh address counter 312 does not increase. The activation operation is repeatedly performed on the word line.

Next, Fig. 6 is a block diagram showing the configuration of the refresh address counter 310 of the present invention, which is comprised of a counter pulse generator CNTP, a refresh address counter 312, and a mode register 311, and a refresh address counter. 312 consists of n + 1 counter generators, oscillator counters, and two NOR gates.

Fig. 7 is an operation timing diagram for explaining the count operation for the refresh address counter of the present invention shown in Fig. 6, where CNTP is the waveform of the counter pulse generator CNTP, and CNT0 to CNTn are inside the refresh address counter 312. It is the waveform of each counter generator, RA is the waveform of the address latch 400, and X4CNT is the waveform of the oscillator counter (XCNT).

In FIG. 7, when one row address finishes refreshing, the refresh address counter 312 counts up one bit to prepare the next refresh cycle as shown in FIG. 7, and specifies the next address. The generator CNTn receives the refresh address information applied to the address latch 400 while having a period n times a power of 2 of the first counter generator CNT0 to which the output of the counter pulse generator CNTP is applied.

Here, the first NOR gate NOR1 receives the output of the second counter generator CNT1 and the output of the oscillator counter XCNT, and the second NOR gate NOR2 is connected to the output of the first NOR gate NOR1. By receiving the output of the mode register 311 and outputting an address to the third counter generator CNT2, as shown in FIG. 7, the count operation cannot be performed after the third counter generator CNT2.

The oscillator counter (XCNT) is fed back to the internal operation part of the refresh when the counter pulse becomes four times or eight times the counter pulse generator (CNTP) cycle, so that four active and precharge operations can be automatically performed. As shown, when the output becomes a high level by the test mode register 311 set, the counter generators are reset to limit the number of counter occurrences.

Therefore, since the row address count does not increase during the semiconductor memory test, the same word line is repeatedly activated, thereby enabling short period test disturb in the high frequency test equipment intended in the present invention.

Next, FIG. 8 is a timing diagram illustrating the internal operation of the semiconductor by the test apparatus of the semiconductor memory of the present invention, in which a desired number of word line active operations are performed internally by entering the test mode.

Self-refresh mode is a mode used for low power operation or data storage for a long time, and not only the refresh address but also the refresh entry command is generated internally, thereby reducing the power consumption by increasing the generation period.

When all banks of memory cells are idle, CSB, RASB, CASB, and CKE go low, WEB goes high, and enters self-refresh mode. Afterwards, the SDRAM goes into an idle state, at which point you can enter another command.

FIG. 8 is an operation timing diagram for explaining the internal operation of a semiconductor device by a short-period row address disturb test apparatus of the semiconductor memory of the present invention, and illustrates the same word line repetition activation operation using a count pulse in a self-refresh logic design. .

The internal clock of a typical DRAM is operated in synchronization with an external clock. However, in a tester that cannot operate at a high speed, the test can be performed by enabling a word line at a period shorter than a frequency that the tester can generate. It is operated by the system clock only when entering the mode, and then by the counter inside the DRAM.

Therefore, if the system clock, which is not a word line active operation in synchronization with the system clock, is set in the test mode in the mode register 311 for an asynchronous clock of 400 ns, the word line active and precharge operation of a cycle having an auto refresh period of 100 ns is performed. It occurs four times, and when the precharge cycle is complete, the corresponding row of memory cells can begin a new activation cycle.

The meanings and functions of the signals according to the timing diagram shown in FIG. 8 will be described below.

In Fig. 8, CSB is a memory semiconductor chip select signal, RASB is a row address strobe signal, which acts like a chip enable to start the operation of DRAM, and CASB is a column address strobe signal to give the column address to DRAM. Informs you that you are authorized.

WEB determines whether to write or read data to DRAM as a write enable signal, CKE is an external clock enable signal to maintain a low level in self-refresh mode, RA is an address latch signal, and word line internal operation The signal is a signal in which the active and precharge operations in the semiconductor are performed. The reason why the write and read operations are omitted is as follows.

In the operation of DRAM, when data is written to a cell, the magnetic data of a defective cell is changed by a potential difference between other word lines or cells adjacent to each other when there is a leakage source. This is because the effect occurs only by enabling or disabling the word line.

First, when the test mode MRS (Mode Register Set) is set, the test mode is set by using the self-refresh logic design with CKE being high, and CSB, RASB, CASB, and WEB are set low to enter the self-refresh mode. And deactivates CKE from high to low level.

On the other hand, the PRB is an active pulse, which is shifted low during the active operation, and the PRD is a refresh operation signal, which generates an active at high level and a precharge at low level.

PSELF is a self refresh enable signal, and SRFHP is a self refresh pulse, which is the basic self refresh period generation pulse signal.

PRFH is a high level enable refresh pulse in the refresh mode to block external addresses, and SRSP is a self refresh signal that internally generates refresh operation information when entering the self refresh operation mode.

PSCNT is a refresh address counter signal generated by receiving the oscillator pulse generated during the self-refresh operation. The PSCNT is generated by the counter pulse generated by the PRFH. The PSCNT is applied to the address latch RA when it is input to the CNTP position. Instead of increasing the internal address, it functions as an oscillator only four or eight times to form an active or precharge feedback circuit, where PAPB is an auto precharge pulse.

5 and 8, operations according to the signals of the semiconductor memory device of the present invention will be described below.

In FIG. 5, the internal control signal generator 100 receives and decodes the signals CSB, RASB, CASB, WEB, and CKE from the outside, and outputs the signals MRS, PRFH1, PSELF, and PRB. As a memory register set signal, sets the test mode.

The self refresh generator 210 receives the self refresh enable signal PSELF and the output signal X4CNT of the oscillator counter in the refresh address counter to output the self refresh pulse SRFHP, and the auto refresh generator 250 outputs the refresh pulse. SRFHP is applied to output the second refresh pulse PRFH2, and the self refresh pulse generator 210 receives the second refresh pulse PRFH2 to output the self refresh signal SRSP.

In addition, the active generator 210 receives the active pulse PRB and receives the self refresh signal SRSP to output the refresh operation signal PRD, and the precharge generator 210 outputs the second refresh pulse PRFH2. When applied, it outputs an auto precharge pulse (PAPB).

The counter pulse generator CNTP generates a pulse for driving the refresh address counter 312 by receiving the first or second refresh pulses PRFH1 and PRFH2, and the mode register 311 generates a mode register setting signal ( The test mode is set by receiving the MRS, and the refresh address counter 312 receives the output of the counter pulse generator and the mode register, and outputs the oscillator counter signal X4CNT to be fed back to the self refresh generator 210.

The address latch 400 receives an output signal from the refresh address counter and the count cutoff unit 300, the refresh operation signal PRD, and the auto precharge pulse PAPB to output the internal address radd.

The row address decoder 400 receives an internal address radd to decode the address and outputs a row address, and the memory cell array 500 includes a memory cell connected between the selected word line WL and the bit line BL. The data DIN is stored in the MC or the data DOUT is output from the memory cell MC.

In FIG. 8, when the signal RASB goes down, the signal PRB goes down and the first active operation is enabled, and the signal PRD goes up and performs the active operation internally in the DRAM word line. )

When the signal CKE goes down, the signal PRFH rises and prevents the application of an external address with an auto pulse in the refresh mode, and a refresh address counter PSCNT is generated. When the signal PRFH falls again, the signal goes down. (PAPB) descends to provide auto precharge information, signal PRB rises to disable RAS master clock, and signal PRD goes down to perform precharge operation (S②).

When the signal PSELF goes up, the self refresh operation starts. When the signal SRFHP goes up and then goes down, the signal PRFH goes up and prevents the application of an external address with an auto pulse in the refresh mode. PSCNT) is generated. On the other hand, as the signal SRSP rises and transitions to generate the precharge signal information internally in the self-refresh operation mode, an active operation is performed by rising and shifting the signal PRD. (S③)

When the signal PRFH falls down again, the signal SRSP falls down, exits the self-refresh mode, and performs a precharge operation by falling down the signal PRD.

When the signal SRFHP falls down again, the signal PRFH rises and prevents the application of an external address with an auto pulse in the refresh mode, and the refresh address counter PSCNT is generated and at the same time, the signal SRSP rises and shifts the signal ( The active operation is performed by increasing the PRD). (S⑤)

If the signal PRFH falls down again, the precharge operation is performed in the same manner as in step S④ (S⑥), and if the signal SRFHP transitions down again, the active operation is performed in the same manner as in step S⑤ (S⑦).

Lastly, when the signal PRFH falls down again, the signal SRSP falls down, exits the self-refresh mode, and falls down the signal PRD to perform the precharge operation and simultaneously the signal PAPB falls down. (S⑧)

After completing the active and precharge operations four times in the semiconductor, the self-refresh mode is terminated by activating the signal CKE to a high level.

Accordingly, the refresh address counter PSCNT is generated by the counter pulse generator CNTP generated by the signal PRFH, and is applied to the address latch 400 when it is inputted to the position of the counter pulse generator CNTP. The row address is not increased and the refresh address counter (PSCNT) is not increased by performing active and precharge operations internally in the DRAM as only four or eight oscillators, thereby enabling the activation operation repeatedly for the same word line. Done.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art will be variously modified and modified within the scope of the present invention without departing from the spirit and scope of the present invention described in the claims below. It will be appreciated that it can be changed.

In the memory device of the present invention, the semiconductor memory test operation can be performed in a short period even in low frequency devices by implementing the DRAM operation in a test mode that can repeatedly access the same word line internally in low frequency devices that cannot operate in a cycle of 100 ns or less. have.

Claims (7)

An internal control signal generator configured to decode command signals applied from the outside and output a first refresh pulse, a self refresh enable, and an active pulse; In response to the first refresh pulse, the self refresh enable, and the active pulse, a refresh operation is performed internally in the DRAM and counts for each row address sequentially. An internal address generator for latching after generating an address and outputting an internal address; A memory cell array comprising a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines; And a row address decoder configured to sequentially access a plurality of word lines in the normal mode by receiving the internal address, and to decode one word line to be repeatedly accessed a predetermined number of times in the test mode. . The method of claim 1, The internal address generator is The first refresh pulse, the self refresh enable, and the active pulse are applied in the normal mode to perform one refresh operation in the DRAM, and in the test mode, the refresh address count limit signal is applied to perform the refresh operation a predetermined number of times. A refresh internal operation unit configured to output a second refresh pulse, a refresh operation signal, and an auto precharge pulse; A refresh address counter unit configured to receive the first refresh pulse and the second refresh pulse to count refresh addresses for each row address, and output a refresh address count limit signal and a refresh address to block an address count increase in a test mode; A count blocker; And an address latch configured to receive the refresh address, the refresh operation signal, and an auto precharge pulse to output an internal address. The method of claim 2, The refresh internal operation unit A self refresh generator configured to enter the self refresh mode in the DRAM by receiving the self refresh pulse and the refresh address count limit signal; An auto refresh generator configured to receive the self refresh pulse and output a second refresh pulse to refresh the DRAM internally without an external command; A self refresh pulse generator configured to receive the second refresh pulse to generate a self refresh signal; An active generator which receives the active pulse and the self refresh signal and outputs a refresh operation signal to perform an active operation internally in the semiconductor; And a precharge generator configured to receive the first refresh pulse and output an auto precharge pulse to perform a precharge operation in the semiconductor. The method of claim 2, The refresh address counter unit and the count blocking unit A counter pulse generator receiving the first refresh pulse to generate a counter pulse; A mode register configured to set and set a test mode in a semiconductor memory test; A refresh address counter receiving the counter pulse and the test mode setting signal and increasing a row address count by one bit for each row address to output an n-th counter generator value and an oscillator counter value; A first NOR gate receiving the test mode setting signal and the n-th counter generator value and outputting a refresh address; And a second NOR gate configured to receive an output of the first NOR gate and an output of the n-th counter generator value and output an address. The method of claim 4, wherein The refresh address counter is N-th counter generators receiving the counter pulse and generating counter pulses at a period of n-th power of two; An oscillator counter for generating a refresh address count limit signal at a period four times or eight times the counter pulse generator period and for resetting the counter pulse generator at a high level output; A first NOR gate receiving an output of the second counter generator and an output of the oscillator counter to output a semi-logical sum result; And a second NOR gate configured to receive an output of the first NOR gate and an output of the oscillator counter and output a semi-logical sum result. The method according to claim 2 or 4, The refresh address counter unit and the count blocking unit In the semiconductor memory test mode, the pulse generated at the refresh address counter is not directly applied to the address latch due to the setting of the mode register, so that the refresh address counter does not increase, thereby repeatedly performing the activation operation on the same word line. A semiconductor memory device, characterized in that. The method according to claim 4 or 5, The refresh address counter is When the output becomes high by the mode register setting, the counter generator is reset so that the number of counter occurrences is limited and the row address count does not increase in the test mode, thereby repeatedly activating the same word line. A semiconductor memory device.

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