WO2014132836A1

WO2014132836A1 - Semiconductor device

Info

Publication number: WO2014132836A1
Application number: PCT/JP2014/053715
Authority: WO
Inventors: 持田　宜晃
Original assignee: ピーエスフォールクスコエスエイアールエル
Priority date: 2013-02-28
Filing date: 2014-02-18
Publication date: 2014-09-04
Also published as: TW201510998A

Abstract

[Problem] To reduce current consumption caused by refresh operations by fine-tuning an adjustment pitch of a refresh rate. [Solution] In response to the first activation of a refresh signal (RF), N units of word lines are selected twice, and thereby, refresh operations are performed, and then, in response to the second activation of the refresh signal (RF), N units of word lines are selected three times, and thereby, refresh operations are performed. As a result, in response to an activation of the refresh signal (RF), it is possible to perform, on average, 2.5 refresh operations, and therefore, it is possible to more finely tune the adjustment pitch of the refresh rate. As a result, in accordance with data retention time of a memory cell, it is possible to reduce current consumption more.

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device that performs a refresh operation for holding data stored in a memory cell array.

DRAM (Dynamic Random Access Memory), a typical semiconductor device, is a volatile semiconductor memory device that stores information based on the amount of charge stored in the cell capacitor. Information is lost due to current. For this reason, it is necessary to refresh all memory cells before information is lost due to leakage current. The period (= tREF) at which all the memory cells are refreshed is set to 64 msec, for example, according to the standard. For this reason, the controller that controls the DRAM issues refresh commands, for example, 8k (= 2 ¹³ ) times so that all word lines are selected within a period of 64 msec.

However, in reality, the data retention time of the memory cell is not necessarily 64 msec, and changes depending on the process conditions. Considering this point, the number of word lines activated in response to one refresh command is reduced in a DRAM having a long data holding time, and conversely, a single refresh command in a DRAM having a short data holding time. In some cases, control is performed such that the number of word lines to be activated is increased in response to (see Patent Document 1).

For example, if the number of word lines that are simultaneously activated in one refresh operation is N, and the data retention time is as designed (64 msec or more), N in response to one refresh command. When two word lines are activated twice and the data retention time is more than twice the design value (128 msec or more), N word lines are activated only once in response to one refresh command. What is necessary is just to make it. Conversely, if the data holding time is shorter than the design value (64 × 2/3 msec or more and less than 64 msec), N word lines may be activated three times in response to one refresh command. . Further, when the data holding time is 32 msec or more and less than 64 × 2/3 msec, N word lines may be activated four times in response to one refresh command. As a result, the refresh frequency for each memory cell is optimized, so that the current consumption due to the refresh operation can be reduced.

JP 2010-170608 A

However, in the above-described method, since the adjustment pitch of the refresh frequency is defined as an integer multiple of N, the adjustment pitch is coarse and the effect of reducing current consumption is not sufficient. For example, when the data retention time is 64 × 4/5 msec or more and less than 64 msec, N word lines may be activated 2.5 times in response to one refresh command. Of course, such a refresh operation is impossible. Similarly, if the data holding time is 64 × 4/3 msec or more and less than 128 msec, N word lines may be activated 1.5 times in response to one refresh command. However, such a refresh operation is also impossible.

A semiconductor device according to an aspect of the present invention includes a plurality of memory cells that need to retain data by a refresh operation, a memory cell array including a plurality of word lines that select the plurality of memory cells, and a first activation of a refresh signal The refresh operation is performed by selecting a first number of word lines from among the plurality of word lines in response to activation, and among the plurality of word lines in response to second activation of the refresh signal. And a refresh control circuit that performs the refresh operation by selecting a second number of word lines different from the first number.

A semiconductor device according to another aspect of the present invention includes a plurality of memory cells that need to hold data by a refresh operation, and first and second memory banks each including a plurality of word lines that select the plurality of memory cells. In response to the first activation of the refresh signal, a first number of word lines are selected from the plurality of word lines included in the first memory bank, and are included in the second memory bank. A refresh control circuit that performs the refresh operation by selecting a second number of word lines different from the first number among the plurality of word lines.

According to the present invention, since the adjustment pitch of the refresh frequency can be set more finely, the current consumption can be further reduced according to the data retention time of the memory cell.

1 is a block diagram showing an overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention. FIG. 2 is a block diagram showing a characteristic part extracted from the semiconductor device 10 and corresponds to the first embodiment of the present invention. 3 is a circuit diagram of a refresh counter 200. FIG. FIG. 3 is a circuit diagram of a starting circuit 100. 3 is a circuit diagram showing a configuration of a main part of a mode register 14. FIG. FIG. 10 is a timing chart for explaining a refresh operation when a setting signal M8K is activated. FIG. 10 is a timing chart for explaining a refresh operation when a setting signal M53K is activated. FIG. 10 is a timing chart for explaining a refresh operation when a setting signal M64K is activated. FIG. 10 is a timing chart for explaining a refresh operation when a setting signal M107K is activated. It is a block diagram which extracts and shows the characteristic part among the semiconductor devices 10, and is equivalent to the 2nd Embodiment of this invention. It is a circuit diagram of the refresh counter 200a. It is a circuit diagram of the starting circuit 100a. 3 is a circuit diagram showing a configuration of a main part of a mode register 14. FIG. FIG. 10 is a timing chart for explaining a refresh operation when a setting signal M64K is activated. FIG. 10 is a timing chart for explaining a refresh operation when a setting signal M107K is activated.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

The semiconductor device 10 according to the present embodiment is a DRAM integrated on a single semiconductor chip and has a memory cell array 11. The memory cell array 11 includes a plurality of word lines WL and a plurality of bit lines BL, and has a configuration in which memory cells MC are arranged at intersections thereof. The memory cell MC is a DRAM cell that needs to hold data by a refresh operation. Selection of the word line WL is performed by the row decoder 12, and selection of the bit line BL is performed by the column decoder 13. As will be described later, the memory cell array 11 is divided into a plurality of memory banks (BANK0 to BANK7), and non-exclusive access to different memory banks is possible.

As shown in FIG. 1, the semiconductor device 10 is provided with an address terminal 21, a command terminal 22, a clock terminal 23, a data terminal 24, and a power supply terminal 25 as external terminals.

The address terminal 21 is a terminal to which an address signal ADD is input from the outside. The address signal ADD input to the address terminal 21 is supplied to the address latch circuit 32 via the address input circuit 31 and is latched by the address latch circuit 32. The address signal PADD latched by the address latch circuit 32 is supplied to the row decoder 12, the column decoder 13, or the mode register 14. The mode register 14 is a circuit in which a parameter indicating the operation mode of the semiconductor device 10 is set.

The command terminal 22 is a terminal to which a command signal CMD is input from the outside. The command signal CMD includes a plurality of signals such as a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE. Here, a slash (/) at the head of the signal name means that the corresponding signal is an inverted signal or that the signal is a low active signal. The command signal CMD input to the command terminal 22 is supplied to the command decoding circuit 34 via the command input circuit 33. The command decode circuit 34 is a circuit that generates various internal commands by decoding the command signal CMD. As internal commands, there are an active signal AC, a column signal ICOL, a refresh signal RF, a mode register set signal MRS, and the like.

The active signal AC is a signal that is activated when the command signal CMD indicates row access (active command). When the active signal AC is activated, the address signal ADD latched by the address latch circuit 32 is supplied to the row decoder 12. Thereby, the word line WL designated by the address signal ADD is selected.

The column signal ICOL is a signal that is activated when the command signal CMD indicates column access (read command or write command). When the internal column signal ICOL is activated, the address signal ADD latched by the address latch circuit 32 is supplied to the column decoder 13. As a result, the bit line BL specified by the address signal ADD is selected.

Therefore, when an active command and a read command are input in this order, and a row address and a column address are input in synchronization therewith, read data is read from the memory cell MC specified by the row address and the column address. The read data DQ is output to the outside from the data terminal 24 via the FIFO circuit 15 and the input / output circuit 16. On the other hand, when an active command and a write command are input in this order, and a row address and a column address are input in synchronization therewith, and then write data DQ is input to the data terminal 24, the write data DQ is input to the input / output circuit 16 The data is supplied to the memory cell array 11 via the FIFO circuit 15 and written to the memory cell MC specified by the row address and the column address. The operations of the FIFO circuit 15 and the input / output circuit 16 are performed in synchronization with the internal clock signal LCLK. The internal clock signal LCLK is generated by the DLL circuit 39.

The refresh signal RF is a signal that is activated when the command signal CMD indicates a refresh command. When the refresh signal RF is activated, row access is performed by the refresh control circuit 35, and a predetermined word line WL is selected. As a result, the plurality of memory cells MC connected to the selected word line WL are refreshed. Details of the refresh control circuit 35 will be described later.

The mode register set signal MRS is a signal that is activated when the command signal CMD indicates a mode register set command. Therefore, if a mode register set command is input and a mode signal is input from the address terminal 21 in synchronization therewith, the set value of the mode register 14 can be rewritten.

The clock terminal 23 is a terminal to which external clock signals CK and / CK are input. The external clock signal CK and the external clock signal / CK are complementary signals, and both are supplied to the clock input circuit 36. The clock input circuit 36 generates an internal clock signal ICLK based on the external clock signals CK and / CK. The internal clock signal ICLK is supplied to the timing generator 37, whereby various internal clock signals are generated. Various internal clock signals generated by the timing generator 37 are supplied to circuit blocks such as the address latch circuit 32 and the command decode circuit 34, and define the operation timing of these circuit blocks.

The internal clock signal ICLK is also supplied to the DLL circuit 39. The DLL circuit 39 is a clock generation circuit that generates an internal clock signal LCLK whose phase is controlled based on the internal clock signal ICLK. As described above, the internal clock signal LCLK is supplied to the FIFO circuit 15 and the input / output circuit 16. As a result, the read data DQ is output in synchronization with the internal clock signal LCLK.

The power supply terminal 25 is a terminal to which power supply potentials VDD and VSS are supplied. The power supply potentials VDD and VSS supplied to the power supply terminal 25 are supplied to the internal power supply generation circuit 38. The internal power supply generation circuit 38 generates various internal potentials VPP, VARY, VBLP, VPERI and the like based on the power supply potentials VDD and VSS. The internal potential VPP is a potential mainly used in the row decoder 12, the internal potentials VARY and VBLP are mainly potentials used in the memory cell array 11, and the internal potential VPERI is used in many other circuit blocks. It is a potential.

FIG. 2 is a block diagram showing a characteristic part extracted from the semiconductor device 10 according to the present embodiment, and corresponds to the first embodiment of the present invention.

As shown in FIG. 2, the refresh control circuit 35 includes a startup circuit 100, a refresh counter 200, and a bank selection circuit 300. The activation circuit 100 is a circuit that generates the timing signal RREFT once or a plurality of times in response to the activation of the refresh signal RF, and how many times the timing signal RREFT is activated is designated by the setting signal M. In the present embodiment, the setting signal M includes setting signals M53, M8, and M107. The timing signal RREFT is supplied to the refresh counter 200, the bank selection circuit 300, and the address selector 18.

As shown in FIG. 3, the refresh counter 200 is a counter that is incremented (or decremented) by the timing signal RREFT, and the count value is supplied to the address selector 18 as the refresh address XADD. Although not particularly limited, in this embodiment, the refresh address XADD has a 14-bit configuration including bits X0 to X13.

As shown in FIG. 3, the refresh counter 200 includes two

latch circuits

201 and 202 that are circularly connected, and performs a latch operation in synchronization with the rising edge and the falling edge of the timing signal RREFT, respectively. The output of the latch circuit 202 is used as the bit X13 and also as a clock signal for the

latch circuits

203 and 204 at the next stage. The output of the latch circuit 204 is used as a bit X12 and also as a clock signal for the next stage latch circuit. Such a connection is repeated up to the

latch circuits

205 and 206 at the final stage, and the output of the latch circuit 206 is used as the bit X0. With this configuration, when the timing signal RREFT is activated 16k times (= 2 ¹⁴ ), the refresh counter 200 makes one cycle of the refresh address XADD that is the count value.

The bank selection circuit 300 is a circuit that activates the bank selection signals MCBAT0 to MCBAT7 in response to the timing signal RREFT. Bank selection signals MCBAT0 to MCBAT7 are signals for selecting the memory banks BANK0 to BANK7, respectively. In this embodiment, when the timing signal RREFT is activated, all the bank selection signals MCBAT0 to MCBAT7 are activated simultaneously. However, the activation timing of the bank selection signals MCBAT0 to MCBAT7 may be shifted in order to suppress the peak current.

As shown in FIG. 2, each of the memory banks BANK0 to BANK7 includes a memory cell array 11, a row decoder 12, and an address latch circuit 17 independently. The address latch circuit 17 serves to latch the row address RADD supplied from the address selector 18 and supply it to the corresponding row decoder 12. The address selector 18 selects either the address signal PADD supplied from the address latch circuit 32 shown in FIG. 1 or the refresh address XADD supplied from the refresh counter 200, and outputs the selected address as the row address RADD. . The selection is controlled by the active signal AC and the timing signal RREFT.

Specifically, the address signal PADD is selected when the active signal AC is activated, and the refresh address XADD is selected when the timing signal RREFT is activated. As a result, when an active command is issued from the outside, the address signal ADD supplied from the outside is supplied to each of the memory banks BANK0 to BANK7, thereby executing row access. On the other hand, when a refresh command is issued from the outside, the refresh address XADD is supplied to each of the memory banks BANK0 to BANK7, thereby executing a refresh operation.

FIG. 4 is a circuit diagram of the activation circuit 100.

As shown in FIG. 4, in the activation circuit 100, the pulse generation circuit 110 that generates a one-shot pulse in response to the rising edge of the refresh signal RF and the bank selection signals MCBAT0 and MCBAT7 both change to a low level. A pulse generation circuit 120 that generates a one-shot pulse in response and a counter circuit 130 that counts the timing signal RREFT are provided.

The counter circuit 130 is a 3-bit binary counter, and latch

circuits

131 and 132 that count the least significant bit,

latch circuits

133 and 134 that count the second least significant bit, and latch

circuits

135 and 136 that count the most significant bit. Including. The

latch circuits

131 and 132 are circularly connected and perform a latch operation in synchronization with the rising edge and falling edge of the timing signal RREFT, respectively. The output of the latch circuit 132 is used as a clock signal for the

latch circuits

133 and 134 at the next stage, and the output of the latch circuit 134 is used as a clock signal for the

latch circuits

135 and 136 at the final stage. With this configuration, the counter circuit 130 can count the number of activations of the timing signal RREFT.

The output of the counter circuit 130 is supplied to the gate circuit 140. The gate circuit 140 includes NAND gate circuits 141 to 143 to which setting signals M107, M8, and M53 are supplied, respectively, and one of the NAND gate circuits 141 to 143 is selected based on the setting signals M53, M8, and M107. Is done. As shown in FIG. 4, the outputs of the counter circuit 130 are input to the NAND gate circuits 141 to 143 with different logics. Then, according to the connection shown in FIG. 4, the NAND gate circuit 141 selected by the setting signal M107 makes the output low when the count value of the counter circuit 130 is 0, and the NAND gate circuit selected by the setting signal M8. The circuit 142 sets the output to a low level when the count value of the counter circuit 130 is 1, and the NAND gate circuit 143 selected by the setting signal M53 outputs the output when the count value of the counter circuit 130 is 2. Is low level.

The outputs of the NAND gate circuits 141 to 143 are input to the gate circuit 150 via the NAND gate circuit 144 and the inverter 145. The gate circuit 150 outputs the one-shot pulse generated by the pulse generation circuit 110 as the timing signal RREFT, and the one-shot pulse generated by the pulse generation circuit 120 on condition that the output of the inverter 145 is at a high level. Is output as a timing signal RREFT. Since the pulse generation circuit 120 generates a one-shot pulse when both the bank selection signals MCBAT0 and MCBAT7 change to a low level, the one-shot pulse is generated every time the refresh operation is completed. Here, the reason why the bank selection signals MCBAT0 and MCBAT7 are used is to correctly detect the completion of the refresh operation even when the refresh operation is performed by shifting the activation timing of the bank selection signals MCBAT0 to MCBAT7. .

With the above circuit configuration, when the setting signal M53 is activated, the timing signal RREFT is generated three times in response to the activation of the refresh signal RF, and when the setting signal M8 is activated, the refresh is performed. In response to the activation of the signal RF, the timing signal RREFT is generated twice, and when the setting signal M107 is activated, the timing signal RREFT is generated only once in response to the activation of the refresh signal RF. .

FIG. 5 is a circuit diagram showing a configuration of a main part of the mode register 14.

As shown in FIG. 5, the mode register 14 includes a register circuit unit 401 and a decoder 402 that decodes mode signals M64KT and M8KT among various parameters set in the register circuit unit 401. Various parameters set in the register circuit unit 401 are rewritten by an address signal PADD input in synchronization with the mode register set signal MRS, and a part thereof is set by a fuse signal FUSE output from a fuse circuit (not shown). Is done.

The mode signals M64KT and M8KT are binary signals, and the decoder 402 activates any one of the setting signals M53K, M64K, M8K, and M107K based on the value. Here, the setting signals M53K, M64K, M8K, and M107K are signals indicating the refresh frequency. The refresh frequency corresponds to the number of word lines WL activated in response to one refresh command, and the refresh frequency increases as the number increases. That is, a controller (not shown) that controls the semiconductor device 10 issues a refresh command, for example, 8k (= 2 ¹³ ) times so that all word lines WL are selected within a period of 64 msec determined by the standard. . That is, the number of refresh commands issued per unit time is determined in advance. On the other hand, the number of word lines WL that are simultaneously activated in one refresh operation can be arbitrarily set on the semiconductor device 10 side.

For example, when the number of word lines WL that are simultaneously activated in one refresh operation is N, and the data retention time is as designed (64 msec or more), in response to one refresh command. If N different word lines WL are activated twice, the refresh address XADD, which is the count value of the refresh counter 200, can be made to circulate once within a period of 64 msec. When performing such an operation, the parameters of the register circuit unit 401 may be set so that the setting signal M8K is activated.

On the other hand, if the data holding time is 64 × 2/3 msec or more and less than 64 × 4/5 msec, different N word lines WL may be activated three times in response to one refresh command. . As a result, the refresh address XADD, which is the count value of the refresh counter 200, can be made to circulate once within a period of 64 × 2/3 msec. In other words, since a normal word line of 1.5 times is selected within a period of 64 msec determined by the standard, the current consumption required for the refresh operation increases to 1.5 times the normal value. When performing such an operation, the parameters of the register circuit portion 401 may be set so that the setting signal M53K is activated.

On the other hand, when the data holding time is 64 × 4/5 msec or more and less than 64 msec, if N different word lines WL are activated 2.5 times in response to one refresh command, The refresh address XADD, which is the count value of the refresh counter 200, can be made to circulate within a period of 64 × 4/5 msec, but it is needless to say that the number of activations of the word line WL needs to be an integer value. For this reason, in the present embodiment, in response to one refresh command, the operation of activating two different N word lines WL twice and the operation of activating three times are executed alternately. Achieve 2.5 activations. In this case, since the normal 1.25 times the word line is selected within the period of 64 msec determined by the standard, the current consumption required for the refresh operation increases to 1.25 times the normal. When performing such an operation, the parameters of the register circuit unit 401 may be set so that the setting signal M64K is activated.

Similarly, when the data holding time is 64 × 4/3 msec or more, if N different word lines WL are activated 1.5 times in response to one refresh command, 64 × 4 / The refresh address XADD, which is the count value of the refresh counter 200, can be made to make a round within a period of 3 msec. In the present embodiment, in response to one refresh command, the operation of activating different N word lines WL once and the operation of activating twice are equivalently performed, thereby equivalently 1 . Realize 5 activations. In this case, since the normal 0.75 times the word line is selected within the period of 64 msec determined by the standard, the current consumption required for the refresh operation is reduced to 0.75 times the normal. When performing such an operation, the parameters of the register circuit portion 401 may be set so that the setting signal M107K is activated.

As shown in FIG. 5, the setting signals M53K, M64K, M8K, and M107K are supplied to the gate circuits 411 to 413. The gate circuit 411 activates the setting signal M53 when the setting signal M53K is activated or when the switching signal RMOD is activated on condition that the setting signal M64K is activated. The gate circuit 412 activates the setting signal M8 when the setting signal M8K is activated or when the switching signal RMOD is deactivated on the condition that the setting signal M64K or M107K is activated. Make it. Further, the gate circuit 413 activates the setting signal M107 when the switching signal RMOD is activated on condition that the setting signal M107K is activated.

The switching signal RMOD is generated by the circularly connected

latch circuits

421 and 422. The

latch circuits

421 and 422 perform a latch operation in synchronization with the rising edge and the falling edge of the refresh signal RF on condition that the setting signal M64K or M107K is activated. For this reason, when the setting signal M64K or M107K is activated, the logic level of the switching signal RMOD is inverted every time a refresh command is issued. The switching signal RMOD is reset by a power-on reset signal PON that is activated when the power is turned on.

The above is the configuration of the semiconductor device 10 according to the present embodiment. Next, the refresh operation of the semiconductor device 10 according to the present embodiment will be explained.

FIG. 6 is a timing chart for explaining the refresh operation when the setting signal M8K is activated.

As shown in FIG. 6, when the setting signal M8K is activated, when the refresh signal RF is activated by issuing the refresh command REF, the timing signal RREFT is activated twice each time in response thereto. This is because the setting signal M8 is activated when the setting signal M8K is activated, and the activation circuit 100 counts the timing signal RREFT only once by the activation of the setting signal M8, and then stops the operation. Because it does.

When the timing signal RREFT is activated, a refresh operation is performed on the refresh address XADD, and the value is updated by the refresh counter 200. The number of word lines selected in response to one timing signal RREFT is constant (for example, N). In the example shown in FIG. 6, the refresh operation is performed for the refresh addresses XADD = n and n + 1 by issuing the first refresh command REF, and the refresh addresses XADD = n + 2 and n + 3 are issued by issuing the second refresh command REF. The refresh operation is performed. As a result, when the refresh command REF is issued 8k times, the refresh address XADD makes a round, and as described above, the refresh address XADD can make a round within the period of 64 msec.

FIG. 7 is a timing chart for explaining the refresh operation when the setting signal M53K is activated.

As shown in FIG. 7, when the setting signal M53K is activated, when the refresh signal RF is activated by issuing the refresh command REF, the timing signal RREFT is activated three times every time in response thereto. This is because the setting signal M53 is activated when the setting signal M53K is activated, and the activation circuit 100 counts the timing signal RREFT twice by the activation of the setting signal M53, and then stops the operation. Because.

In the example shown in FIG. 7, the refresh operation is performed on the refresh addresses XADD = n, n + 1, and n + 2 by issuing the first refresh command REF, and the refresh address XADD = n + 3, n + 4 is issued by issuing the second refresh command REF. And n + 5 are refreshed. As a result, when the refresh command REF is issued 8k × 2/3 times, the refresh address XADD makes a round, and as described above, the refresh address XADD can make a round within the period of 64 × 2/3 msec.

FIG. 8 is a timing chart for explaining the refresh operation when the setting signal M64K is activated.

As shown in FIG. 8, when the setting signal M64K is activated, when the refresh signal RF is activated by issuing the refresh command REF, the timing signal RREFT is activated alternately twice and three times in response thereto. . This is because when the setting signal M64K is activated, the setting signal M53 and the setting signal M8 are alternately activated every time the refresh command REF is issued.

In the example shown in FIG. 8, the refresh operation is performed on the refresh addresses XADD = n and n + 1 by issuing the first refresh command REF, and the refresh addresses XADD = n + 2, n + 3, and n + 4 are issued by issuing the second refresh command REF. A refresh operation is performed on the image. As a result, when the refresh command REF is issued 8k × 4/5 times, the refresh address XADD makes one round. As described above, the refresh address XADD can make one round within the period of 64 × 4/5 msec. Although not shown, the operation in response to the odd-numbered (third, fifth,...) Refresh command REF is the same as the operation in response to the first refresh command REF, and the even-numbered (fourth, sixth,... The operation in response to the refresh command REF of (-) is the same as the operation in response to the second refresh command REF.

FIG. 9 is a timing chart for explaining the refresh operation when the setting signal M107K is activated.

As shown in FIG. 9, when the setting signal M107K is activated, when the refresh signal RF is activated by issuing the refresh command REF, the timing signal RREFT is activated alternately once and twice in response thereto. . This is because when the setting signal M107K is activated, the setting signal M8 and the setting signal M107 are alternately activated every time the refresh command REF is issued. When the setting signal M107K is activated, the activation circuit 100 stops the operation without counting the timing signal RREFT.

In the example shown in FIG. 9, a refresh operation is performed on the refresh address XADD = n by issuing the first refresh command REF, and a refresh operation is performed on the refresh addresses XADD = n + 1 and n + 2 by issuing the second refresh command REF. Operation is taking place. As a result, when the refresh command REF is issued 8k × 4/3 times, the refresh address XADD makes one round, and as described above, the refresh address XADD can make one round within the period of 64 × 4/3 msec. Although not shown, the operation in response to the odd-numbered (third, fifth,...) Refresh command REF is the same as the operation in response to the first refresh command REF, and the even-numbered (fourth, sixth,... The operation in response to the refresh command REF of (-) is the same as the operation in response to the second refresh command REF.

As described above, the semiconductor device 10 according to the present embodiment has an operation mode for selecting a different number of word lines each time the refresh command REF is issued. Therefore, the timing signal RREFT can be activated on average 1.5 times or 2.5 times in response to one refresh command REF, and the refresh frequency adjustment pitch can be set more finely. Therefore, current consumption can be further reduced according to the data retention time of the memory cell.

Next, a second embodiment of the present invention will be described.

FIG. 10 is a block diagram showing a characteristic part extracted from the semiconductor device 10 according to the present embodiment, and corresponds to the second embodiment of the present invention.

As shown in FIG. 10, in this embodiment, the activation circuit 100, the refresh counter 200, and the bank selection circuit 300 included in the refresh control circuit 35 of the first embodiment are respectively the activation circuit 100a, the refresh counter 200a, and the bank selection. The difference from the first embodiment is that the circuit 300a is replaced. The refresh counter 200a includes a bank selector 210 that generates a selection signal RBA2 and a row address counter 220 that generates a refresh address XADD.

FIG. 11 is a circuit diagram of the refresh counter 200a.

As shown in FIG. 11, the refresh counter 200a has a circuit configuration in which a bank selector 210 is added to the least significant bit of the refresh counter 200 shown in FIG. The bank selector 210 includes two circularly connected

latch circuits

211 and 212, and inverts the logic level of the selection signal RBA2 every time the timing signal RREFT is activated. The selection signal RBA2 is used as a clock signal for the first

stage latch circuits

221 and 222 constituting the row address counter 220, and the output of the latch circuit 222 is used as the bit X13. The bit X13 is used as a clock signal for the next

stage latch circuits

223 and 224, and the output of the latch circuit 224 is used as a bit X12 and also as a clock signal for the next stage latch circuit. Such connection is repeated up to the

latch circuits

225 and 226 in the final stage, and the output of the latch circuit 226 is used as the bit X0. With this configuration, when the timing signal RREFT is activated 32k times (= 2 ¹⁵ ), the refresh counter 200 makes one cycle of the refresh address XADD that is the count value.

The selection signal RBA2 generated by the bank selector 210 is supplied to the bank selection circuit 300a. The bank selection circuit 300a is a circuit that activates the bank selection signals MCBAT0 to MCBAT7 in response to the timing signal RREFT. When the selection signal RBA2 is at a low level, the bank selection signals MCBAT0, 3, 4, and 7 are simultaneously transmitted. When the selection signal RBA2 is at a high level, the bank selection signals MCBAT1, 2, 5, 6 are simultaneously activated. However, in order to suppress the peak current, the activation timing of the bank selection signals MCBAT0, 3, 4, and 7 and the activation timing of the bank selection signals MCBAT1, 2, 5, and 6 may be shifted.

FIG. 12 is a circuit diagram of the activation circuit 100a.

As shown in FIG. 12, in the activation circuit 100a, the pulse generation circuit 161 that generates a one-shot pulse twice in response to the rising edge of the refresh signal RF and the bank selection signals MCBAT0, 1, 6, and 7 are all low. A pulse generation circuit 162 that generates a one-shot pulse twice in response to the change to the level and a counter circuit 170 that counts the timing signal RREFT are provided.

The counter circuit 170 is a 3-bit binary counter, and latch

circuits

171 and 172 that count the least significant bit,

latch circuits

173 and 174 that count the second least significant bit, and latch

circuits

175 and 176 that count the most significant bit. Including. The

latch circuits

171 and 172 are circularly connected and perform a latch operation in synchronization with the rising edge and falling edge of the timing signal RREFT, respectively. The output of the latch circuit 172 is used as a clock signal for the

latch circuits

173 and 174 at the next stage. The output of the latch circuit 174 is used as a clock signal for the

latch circuits

175 and 176 at the final stage. With this configuration, the counter circuit 170 can count the number of activations of the timing signal RREFT.

The output of the counter circuit 170 is supplied to the gate circuit 180. The gate circuit 180 includes NAND gate circuits 181 to 184 to which setting signals M107K, M8K, M64K, and M53K are respectively supplied. Any of the NAND gate circuits 181 to 184 is based on the setting signals M107K, M8K, M64K, and M53K. Or one is selected. As shown in FIG. 12, the outputs of the counter circuit 170 are inputted to the NAND gate circuits 181 to 184 with different logics. 12, the NAND gate circuit 181 selected by the setting signal M107K makes the output low when the count value of the counter circuit 170 is 2, and the NAND gate circuit selected by the setting signal M8K. When the count value of the counter circuit 170 is 3, the circuit 182 sets its output to a low level. The NAND gate circuit 183 selected by the setting signal M64K makes its output low when the count value of the counter circuit 170 is 4, and the NAND gate circuit 184 selected by the setting signal M53K When the count value is 5, the output is set to low level.

The outputs of the NAND gate circuits 181 to 184 are input to the gate circuit 190 via the NAND gate circuit 185 and the inverter 186. The gate circuit 190 outputs the one-shot pulse generated by the pulse generation circuit 161 as the timing signal RREFT, and the one-shot pulse generated by the pulse generation circuit 162 on condition that the output of the inverter 186 is at a high level. Is output as a timing signal RREFT. Since the pulse generation circuit 162 generates a one-shot pulse when any of the bank selection signals MCBAT0, 1, 6, and 7 changes to a low level, the one-shot pulse is generated every time the refresh operation is completed. Become. Here, the two bank selection signals MCBAT0 and MCBAT1 are used for the refresh operation of the group (G1) composed of the bank selection signals MCBAT0, 3, 4 and 7 and the bank selection signals MCBAT1, 2, 5, 6 This is because the refresh operation of the group (G2) consisting of is independently controlled. Further, the bank selection signal MCBAT7 is used in addition to the bank selection signal MCBAT0 even when the refresh operation is performed by shifting the activation timing of the bank selection signals MCBAT0, 1, 6, and 7. This is to correctly detect completion. The bank selection signal MCBAT6 is used in addition to the bank selection signal MCBAT1 for the same reason.

FIG. 12 also shows a part of the bank selection circuit 300a. The bank selection circuit 300a includes a gate circuit that activates one of the timing signals RREF0T and RREF1T according to the logic level of the selection signal RBA2 when the timing signal RREFT is activated. Here, the timing signal RREF0T is a signal for activating the bank selection signals MCBAT1, 2, 5, and 6, and the timing signal RREF1T is a signal for activating the bank selection signals MCBAT0, 3, 4, and 7. .

With the above circuit configuration, when the setting signal M53K is activated, the timing signal RREFT is generated six times in response to the activation of the refresh signal RF, and when the setting signal M64K is activated, the refresh is performed. In response to the activation of the signal RF, the timing signal RREFT is generated five times. Further, when the setting signal M8K is activated, the timing signal RREFT is generated four times in response to the activation of the refresh signal RF, and when the setting signal M107K is activated, the activation of the refresh signal RF In response to the timing, the timing signal RREFT is generated three times.

FIG. 13 is a circuit diagram showing a configuration of a main part of the mode register 14.

As shown in FIG. 13, in this embodiment, setting signals M53K, M64K, M8K, and M107K, which are output signals of the decoder 402, are output as they are and are input to the activation circuit 100a shown in FIG.

FIG. 14 is a timing chart for explaining the refresh operation when the setting signal M64K is activated.

As shown in FIG. 14, when the setting signal M64K is activated, when the refresh signal RF is activated by issuing the refresh command REF, the timing signal RREFT is activated five times in response thereto. At this time, since the selection signal RBA2 inverts its logic level in response to the timing signal RREFT, the bank selection signals MCBAT0, 3, 4, 7 constituting the group G1 and the bank selection signals MCBAT1, 2, 4 constituting the group G2 One of 5 and 6 is activated three times, and the other is activated twice.

In the example shown in FIG. 14, the bank selection signals MCBAT0, 3, 4, and 7 constituting the group G1 are activated three times in response to the first issue of the refresh command REF, and the bank selection signals MCBAT1 and MCBAT1 constituting the group G2 are activated. 2, 5 and 6 are activated twice. In response to the second issuance of the refresh command REF, the bank selection signals MCBAT0, 3, 4, and 7 constituting the group G1 are activated twice, and the bank selection signals MCBAT1, 2, 5, and 6 constituting the group G2 are activated. Is activated three times. Although not shown, the operation in response to the odd-numbered (third, fifth,...) Refresh command REF is the same as the operation in response to the first refresh command REF, and the even-numbered (fourth, sixth,... The operation in response to the refresh command REF of (-) is the same as the operation in response to the second refresh command REF. Thus, an average of 2.5 refresh operations are performed in response to one refresh command REF, and the same effect as described with reference to FIG. 8 can be obtained.

FIG. 15 is a timing chart for explaining the refresh operation when the setting signal M107K is activated.

As shown in FIG. 15, when the setting signal M107K is activated, when the refresh signal RF is activated by issuing the refresh command REF, the timing signal RREFT is activated three times in response thereto. Since the logic level of the selection signal RBA2 is inverted in response to the timing signal RREFT, the bank selection signals MCBAT0, 3, 4, and 7 constituting the group G1 and the bank selection signals MCBAT1, 2, 5, and 5 constituting the group G2 are used. One of 6 is activated twice, and the other is activated once.

In the example shown in FIG. 15, the bank selection signals MCBAT0, 3, 4, and 7 constituting the group G1 are activated twice in response to the first issue of the refresh command REF, and the bank selection signals MCBAT1 and MCBAT1 constituting the group G2 are activated. 2, 5, and 6 are activated once. Also, in response to the second issuance of the refresh command REF, the bank selection signals MCBAT0, 3, 4, 7 constituting the group G1 are activated once, and the bank selection signals MCBAT1, 2, 5, 6 constituting the group G2 are activated. Is activated twice. Although not shown, the operation in response to the odd-numbered (third, fifth,...) Refresh command REF is the same as the operation in response to the first refresh command REF, and the even-numbered (fourth, sixth,... The operation in response to the refresh command REF of (-) is the same as the operation in response to the second refresh command REF. Thus, an average of 1.5 refresh operations are performed in response to one refresh command REF, and the same effect as described with reference to FIG. 9 can be obtained.

Although not shown, when the setting signal M53K is activated, the timing signal RREFT is activated six times in response to the refresh command REF. As a result, every time the refresh command REF is issued, the bank selection signals MCBAT0 to MCBAT7 are all activated three times, so that the same effect as described with reference to FIG. 7 can be obtained. When the setting signal M8K is activated, the timing signal RREFT is activated four times in response to the refresh command REF. Accordingly, every time the refresh command REF is issued, the bank selection signals MCBAT0 to MCBAT7 are all activated twice, so that the same effect as described with reference to FIG. 6 can be obtained.

As described above, in the present embodiment, the bank selection signals MCBAT0 to MCBAT7 are divided into two groups G1 and G2, and when the refresh command REF is issued, the refresh operation is controlled for each group. The same effect as that of the first embodiment can be obtained.

The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

For example, in each of the embodiments described above, the operation when the refresh command REF is issued from the outside has been described. However, the present invention is also applicable to the operation in the self-refresh mode in which the refresh command is automatically generated inside the semiconductor device. Can be applied.

Further, in each of the above embodiments, the operation in response to the odd-numbered refresh command REF and the operation in response to the even-numbered refresh command REF are executed alternately, but the present invention is not limited to this. is not. For example, N word lines are activated three times in response to the first and second refresh commands REF, and N word lines are activated twice in response to the third refresh command REF. Such control can be repeated. By performing such control, the refresh frequency adjustment pitch can be set more finely.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Mode register 15 FIFO circuit 16 Input / output circuit 17 Address latch circuit 18 Address selector 21 Address terminal 22 Command terminal 23 Clock terminal 24 Data terminal 25 Power supply terminal 31 Address input circuit 32 Address Latch circuit 33 Command input circuit 34 Command decode circuit 35 Refresh control circuit 36 Clock input circuit 37 Timing generator 38 Internal power generation circuit 39

DLL circuit

100,

100a Start circuit

110, 120 Pulse generation circuit 130 Counter circuit 131-136 Latch circuit 140- 143 and 150

Gate circuits

161 and 162 Pulse generation circuit 170 Counter circuits 171 to 176 190 to 184, 190

gate circuit

200, 200a refresh counter 201 to 206 latch circuit 210 bank selector 211 to 226

latch circuit

300, 300a bank selection circuit 401 register circuit unit 402 decoder 411 to 413

gate circuit

421, 422 latch circuit BANK0 to BANK7 Memory banks G1, G2 Groups M53, M8, M107, M53K, M64K, M8K, M107K Setting signal M64KT, M8KT Mode signal MCBAT0 to MCBAT7 Bank selection signal RF Refresh signal RMOD Switching signal RREFT Timing signal

Claims

A plurality of memory cells that need to retain data by a refresh operation, and a memory cell array including a plurality of word lines that select the plurality of memory cells;
The refresh operation is performed by selecting a first number of word lines among the plurality of word lines in response to the first activation of the refresh signal, and in response to the second activation of the refresh signal. A semiconductor device comprising: a refresh control circuit that performs the refresh operation by selecting a second number of word lines different from the first number among the plurality of word lines.
2. The semiconductor device according to claim 1, wherein the refresh signal is activated in the order of the first activation and the second activation.
The refresh control circuit selects the first number of word lines from among the plurality of word lines in response to a third activation following the second activation of the refresh signal. The semiconductor device according to claim 2, wherein:
The refresh control circuit selects the second number of word lines among the plurality of word lines in response to a fourth activation following the third activation of the refresh signal, thereby performing the refresh operation. The semiconductor device according to claim 3, wherein:
The refresh control circuit selects the third number of word lines from the plurality of word lines a first number of times in response to the first activation of the refresh signal, thereby causing the first number of words. Selecting a line and selecting the third number of word lines out of the plurality of word lines for a second number of times different from the first number in response to the second activation of the refresh signal. The semiconductor device according to claim 1, wherein the second number of word lines is selected.
6. The semiconductor device according to claim 5, wherein the sum of the first number and the second number is not divisible by two.
A plurality of memory cells that need to hold data by a refresh operation, and first and second memory banks each including a plurality of word lines that select the plurality of memory cells;
In response to the first activation of the refresh signal, a first number of word lines are selected from among the plurality of word lines included in the first memory bank and included in the second memory bank. A semiconductor device comprising: a refresh control circuit that performs the refresh operation by selecting a second number of word lines different from the first number among the plurality of word lines.
The refresh control circuit selects the second number of word lines from the plurality of word lines included in the first memory bank in response to the second activation of the refresh signal, and 8. The semiconductor device according to claim 7, wherein the refresh operation is performed by selecting the first number of word lines among the plurality of word lines included in a second memory bank.
9. The semiconductor device according to claim 8, wherein the refresh signal is activated in the order of the first activation and the second activation.
The refresh control circuit is responsive to a third activation following the second activation of the refresh signal, and the first number of the plurality of word lines included in the first memory bank. 10. The refresh operation is performed by selecting a word line and selecting the second number of word lines from the plurality of word lines included in the second memory bank. The semiconductor device described.
The refresh control circuit is responsive to a fourth activation following the third activation of the refresh signal, and the second number of the plurality of word lines included in the first memory bank. 11. The refresh operation is performed by selecting a word line and selecting the first number of word lines among the plurality of word lines included in the second memory bank. The semiconductor device described.
The refresh control circuit selects the first number of word lines by selecting a third number of word lines among the plurality of word lines included in the first memory bank a first number of times; The second number of word lines are selected by selecting the third number of word lines out of the plurality of word lines included in the second memory bank a second number of times different from the first number of times. The semiconductor device according to claim 7, wherein the semiconductor device is selected.
13. The semiconductor device according to claim 12, wherein the sum of the first number and the second number is not divisible by two.