CN102110678B - 半导体封装件及其制造方法 - Google Patents

半导体封装件及其制造方法 Download PDF

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CN102110678B
CN102110678B CN2010106210310A CN201010621031A CN102110678B CN 102110678 B CN102110678 B CN 102110678B CN 2010106210310 A CN2010106210310 A CN 2010106210310A CN 201010621031 A CN201010621031 A CN 201010621031A CN 102110678 B CN102110678 B CN 102110678B
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chip
organic substrate
semiconductor package
chipset
package part
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CN102110678A (zh
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张效铨
蔡宗岳
赖逸少
叶昶麟
郑明祥
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体封装件及其制造方法。半导体封装件包括有机基板、刚性层及芯片组。芯片组设于有机基板上，芯片组包括第一芯片、第二芯片及第三芯片，第二芯片沿一堆栈方位及一翻转方位设于第一芯片与第三芯片之间，第二芯片支持第一芯片与第三芯片之间的相邻通信。刚性层形成于芯片组。

Description

半导体封装件及其制造方法
技术领域
本发明是有关于一种封装件及其制造方法，且特别是有关于一种半导体封装件及其制造方法。
背景技术
随着科技发展，on-chip基板的尺寸缩小及on-chip电路的工作频率增加，导致on-chip频宽快速增加。相似的进步未见于off-chip基板，因此导致on-chip与off-chip频宽之间的间隙及执行上的瓶颈。
相邻通信(Proximity communication)致力于解决off-chip频宽瓶颈。相邻通信在短距离下具有快速、低成本的优势。放置传送器(transmitter)及接收器(receiver)在极接近的相邻位置，该相邻位置仅分隔数微米，可降低整个通信成本。例如以对齐其中一芯片的传送器电路与另一芯片的接收器电路的方式面对面地放置二芯片。该二芯片经由电容耦合方式进行通信，其中传送器驱动其中一芯片的金属板耦接至另一芯片的对应的金属板。
共面性关系(coplanarity concern)的对于具有相邻通信功能的芯片的半导体封装件是重要。传统上，陶瓷基板被用于半导体封装件。为了降低成本，在一些半导体封装件上，使用有机基板(organic substrate)代替陶瓷基板是趋势。然而，具有有机基板的半导体封装件其翘曲量增加。因此，如何在共面性关系下降低有机基板的翘曲量是待解决的重要课题。
发明内容
本发明有关于一种半导体封装件及其制造方法，半导体封装件可降低在共面性关系下有机基板的翘曲量。
根据本发明的第一方面，提出一种半导体封装件。半导体封装件包括一有机基板(organic substrate)、一芯片组及一刚性层(stiffness layer)。芯片组设于有机基板上，芯片组包括一第一芯片、一第二芯片及一第三芯片。第二芯片沿一堆栈方位及一翻转(flipping)方位设于第一芯片与第三芯片之间，第二芯片支持第一芯片与第三芯片之间的相邻通信(proximity communication)。
根据本发明的第二方面，提出一种半导体封装件的制造方法。制造方法包括以下步骤。提供一刚性层；设置一黏着组件于刚性层上；设置一第一芯片及一第三芯片于黏着组件上；设置一第二芯片至第一芯片及第三芯片上，以形成一芯片组；结合芯片组至一有机基板；以及，电性连接第二芯片与有机基板。
为了对本发明的上述及其它方面有更佳的了解，下文特举较佳实施例，并配合附图，作详细说明如下：
附图说明
图1绘示依照本发明第一实施例的半导体封装件的侧视图。
图2A绘示图1中半导体封装件的芯片组具有以2×2矩阵形式配置的八个芯片的示意图。
图2B绘示图1中半导体封装件的芯片组具有以3×3矩阵形式配置的二十一个芯片的示意图。
图3绘示依照本发明第二实施例的半导体封装件的侧视图。
图4A绘示依照本发明第三实施例的半导体封装件的侧视图。
图4B绘示图4A的半导体封装件的上视图。
图4C绘示一实施例中省略焊线的半导体封装件的示意图。
图5A至5I绘示图4A及4B的半导体封装件的制造方法示意图。
图6绘示依照本发明第四实施例的半导体封装件的侧视图。
主要组件符号说明：
100、300、600：半导体封装件
102、302、402、602：有机基板
104、304、404′：刚性层
106、406：芯片组
108、308、408：第一芯片
108a、110a、112a、408a、410a、412a：主要表面
110、410：第二芯片
112、312、412：第三芯片
114、116、118、120：黏贴层
122、124、418：焊线
132、432：第一信号接垫
134、434：第二信号接垫
136、436：第三信号接垫
202：芯片
326、328、414、416：凸块
330、332：导通孔
420：密封件
422：开孔
424：凹部
502：胶带
504：黏胶
620、622：金属柱
具体实施方式
半导体封装件包括一有机基板(organic substrate)、一刚性层(stiffness layer)及一芯片组。刚性层形成于有机基板上。芯片组设于刚性层上，芯片组包括至少一第一芯片、至少一第二芯片及至少一第三芯片。第二芯片沿一堆栈方位设于第一芯片与第三芯片之间。第一芯片、第二芯片及第三芯片具有相邻通信的功能。
由于有机基板的硬度低于陶瓷基板的硬度，有机基板在封装过程中可能翘曲。经由刚性层形成于有机基板上，可增加有机基板的硬度。因此，可达成翘曲量的降低及优良共面性关系，其对具有相邻通信功能的芯片的半导体封装件而言必需的。
第一实施例
请参照图1，其绘示依照本发明第一实施例的半导体封装件100的侧视图。半导体封装件100包括有机基板102、刚性层104及芯片组106。刚性层104形成于有机基版102上。芯片组106设于刚性层104上。芯片组106包括至少一第一芯片108、至少一第二芯片110及至少一第三芯片112。第二芯片110沿一堆栈方位设于第一芯片108与第三芯片112之间。第一芯片108、第二芯片110及第三芯片112具有相邻通信的功能。
例如，刚性层104经由黏贴层114贴附于有机基板104。芯片组106经由黏贴层116贴附于刚性层104。经由黏贴层118及120分别连接第一芯片108与第三芯片112，第二芯片110连接第一芯片108与第三芯片112。第一芯片108及第三芯片112分别经由焊线(bonding wire)122及124电性连接于有机基板102。
为了实现芯片组106的第一芯片108、第二芯片110及第三芯片112的相邻通信功能，以对齐其中一芯片的传送器电路与另外一芯片的接收器电路的方式，面对面地放置第一芯片108与第二芯片110的一部分及第二芯片110与第三芯片112的一部分在极相邻的位置，例如仅有数微米的分隔距离。传送器电路与接收器电路之间的信号透过电容耦合或电感偶合(inductively coupling)的方式传送，如此降低通信成本。
例如，第一芯片108具有数个第一信号接垫132，其形成于第一芯片108的一主要表面108a，第二芯片110具有数个第二信号接垫134，其形成于第二芯片110的一主要表面110a，第三芯片112具有数个第三信号接垫136，其形成于第三芯片112的一主要表面112a。第二芯片110以与第一芯片108与第三芯片112面对面的方式配置，使至少一些第二信号接垫134电容耦合于至少一些第一信号接垫132及至少一些第三信号接垫136。第二芯片110的主要表面110a隔离于第一芯片108的主要表面108a及第三芯片112的主要表面112a。
以电容耦合的传送为例，第二芯片110的第二信号接垫134的一部分与第一芯片108的第一信号接垫132的一部分互相对齐，第二芯片110的第二信号接垫134的一部分与第三芯片112的第三信号接垫136的一部分互相对齐。由于该些接垫之间非物理接触，第一信号接垫132及第二信号接垫134之间具有电容(capacitance)，而第二信号接垫134及第三信号接垫136之间具有电容。此电容耦合提供第一芯片108与第二芯片110之间的信号路径以及第二芯片110与第三芯片112之间的信号路径。一信号接垫的表面金属的电位改变，导致对应的接垫的金属的电位对应地改变。各别芯片上的传送器电路的适合驱动器(suitable driver)及接收器电路的感测电路(sensing circuit)经由此小电容进行通信。
半导体封装件亦可具有一芯片组，芯片组具有数个芯片，其以矩阵形式配置。例如，芯片配置如图2A或图2B所示。如图2A所示，芯片组具有八个芯片202，其以2×2矩阵形式配置。如图2B所示，芯片组具有二十一个芯片204，其以3×3矩阵形式配置。二相邻芯片以堆栈关系彼此部分地重迭，以实现相邻通信功能。
刚性层104可以是硅载体(Silicon carrier)或以其它高硬度材料制成，例如是以金属制成。经由形成刚性层104于有机基板102上，有机基板102在制造过程或半导体封装件100在操作过程中不致翘曲。因此，有机基板102具有优良共面性，其使第一芯片108、第二芯片110及第三芯片112在相邻通信中适当地运作。
第二实施例
请参照图3，其绘示依照本发明第二实施例的半导体封装件100的侧视图。第二实施例的半导体封装件300与第一实施例的半导体封装件100的不同处如下所述。第一芯片308及第三芯片312中每一者具有数个电性触点(electric contact)，例如是凸块326及328。刚性层304具有数个导通孔(via)330及332。第一芯片308的凸块326及第三芯片312的凸块328分别透过导通孔330及332电性连接于有机基板302，使第一芯片308及第三芯片312电性连接于有机基板302。
第三实施例
请参照图4A及4B，其绘示依照本发明第三实施例的半导体封装件400的侧视图，其中图4B绘示半导体封装件400的上视图。半导体封装件400包括有机基板402、芯片组406及刚性层404。芯片组406设于有机基版406上。芯片组406包括至少一第1芯片408、至少一第二芯片410及至少一第三芯片412。第二芯片410沿堆栈方位及翻转(flipping)方位设于第一芯片408与第三芯片412之间。第一芯片408、第二芯片410及第三芯片412具有相邻通信功能。刚性层404设于芯片组406上。
例如，第一芯片408具有第一信号接垫432，其形成于第一芯片408的一主要表面408a，第二芯片410具有数个第二信号接垫434，其形成于第二芯片410的一主要表面410a，第三芯片412具有数个第三信号接垫436，其形成于第三芯片412的一主要表面412a。第二芯片410以与第一芯片408与第三芯片412面对面的方式配置，使至少一些第二信号接垫434电容耦合于至少一些第一信号接垫432及至少一些第三信号接垫436。第二芯片410的主要表面410a隔离于第一芯片408的主要表面408a及第三芯片112的主要表面112a。
第一芯片408具有数个凸块414，第一芯片408以凸块414电性连接于有机基板402。第三芯片412具有数个凸块416，第三芯片412以凸块416电性连接于有机基板402。第二芯片410具有数条焊线418，第二芯片410以焊线418电性连接于有机基板402。一密封件(sealant)420形成第二芯片410且覆盖焊线418。刚性层404具有至少一开孔422，其位置对应于焊线418的位置。
此外，有机基板402具有一凹部(cavity)424，其用以容置第二芯片410，以降低半导体封装件400的厚度。刚性层404经由以一盖子(lid)实现，例如以金属盖实现。该盖子较佳地由铝(aluminum)或不锈钢(stainless steel)制成。
请参照图5A至5I，其绘示半导体封装件400的制造方法。首先，提供刚性层404，如图5A所示。然后，设置一黏着组件于刚性层上，例如，贴附胶带(tape)502于刚性层404上，如图5B所示；或者，设置黏胶(glue)于刚性层404。然后，设置第一芯片及第三芯片于胶带上，例如，拿取(pick)并放置第一芯片408及第三芯片412于胶带502上，如图5C所示。然后，设置黏胶504于第一芯片408及第三芯片412上，如图5D所示。
接着，如图5E所示，设置第二芯片至第一芯片及第三芯片上，例如，拿取并放置第二芯片410至第一芯片408及第三芯片412上，以形成芯片组406(芯片组406绘示于图5F)。其中，第二芯片410透过黏胶504设于第一芯片408及第三芯片412上。然后，翻转芯片组406，如图5F所示。然后，结合(bond)芯片组406至有机基板402，如图5G所示。然后，进行打线作业，以至少一焊线418连接第二芯片410与有机基板402。如图5H所示，以及形成密封件420覆盖焊线418而形成半导体封装件400，如图5I所示。
第二芯片410可以其它组件代替焊线418而电性连接于有机基板402。若省略焊线418，则对于半导体封装件400来讲，密封件420及开孔422非必要。图4C绘示一实施例中省略焊线的半导体封装件的示意图。图4C的刚性层404’实质上呈矩形。
第一实施例的半导体封装件400可降低有机基板402的翘曲量。此外，刚性层404可避免第二芯片410断裂、破损。在失去刚性层404的情况下，由于不均等的应力作用在第二芯片410或作用在第一芯片408及第三芯片412，第二芯片412可能断裂。由于在放置第二芯片410至有机基板402的过程中芯片组406的倾斜(tilt)，第二芯片412可能断裂；或者，在传递芯片组406的过程中，第二芯片410可能发生断裂。刚性层404可保护芯片组406，降低第二芯片410断裂的可能性。
第四实施例
请参照图6，其绘示依照本发明第四实施例的半导体封装件600的侧视图。第三实施例的半导体封装件400与第四实施例的半导体封装件600的不同处如下所述。半导体封装件600的有机基板602不具有凹口，第二芯片410接触于有机基板602。此外，第一芯片608具有数个金属柱(metal pillar)620，第一芯片608以金属柱620电性连接于有机基板602。第三芯片612具有数个金属柱622，第三芯片612以金属柱622电性连接于有机基板602。金属柱620及622的高度实质上等于第二芯片610的高度。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视权利要求书所界定者为准。

Claims (10)

1.一种半导体封装件，包括：
一有机基板；以及
一芯片组，设于该有机基板上，该芯片组包括一第一芯片、一第二芯片及一第三芯片，该第二芯片沿一堆栈方位及一翻转方位设于该第一芯片与该第三芯片之间，该第二芯片支持该第一芯片与该第三芯片之间的相邻通信；以及
一刚性层，设于该芯片组。
2.如权利要求1所述的半导体封装件，其中该第一芯片与该第三芯片的每一者具有数个凸块，该第一芯片及该第三芯片以该些凸块电性连接于该有机基板；该第二芯片具有数个条焊线，该第二芯片以该些焊线电性连接于该有机基板；该刚性层具有至少一开孔，该开孔的位置对应于该些焊线的位置。
3.如权利要求1所述的半导体封装件，其中该有机基板具有一凹口，用以容置该第二芯片。
4.如权利要求1所述的半导体封装件，其中该第一芯片与该第三芯片的每一者具有数个金属柱，该第一芯片及该第三芯片以该些金属柱电性连接于有机基板，该些金属柱的高度等于该第二芯片的高度。
5.如权利要求1所述的半导体封装件，其中该第一芯片、该第二芯片及该第三芯片分别具有数个第一、第二、第三信号接垫且各具有一主要表面，该些第一信号接垫形成于该第一芯片的该主要表面上，该些第二信号接垫形成于该第二芯片的该主要表面上，而该些第三信号接垫形成于该第三芯片的该主要表面上；
其中，该第二芯片以与该第一芯片及该第三芯片面对面的方式配置，使该些第二信号接垫中至少一些电容耦合于该些第一信号接垫中至少一些及该些第三信号接垫中至少一些；
其中，该第二芯片的该主要表面与该第一芯片的该主要表面及该第三芯片的该主要表面隔离。
6.一种半导体封装件的制造方法，包括：
提供一刚性层；
设置一黏着组件于该刚性层上；
设置一第一芯片及一第三芯片于该黏着组件上；
设置一第二芯片至该第一芯片及该第三芯片上，以形成一芯片组；
结合该芯片组至一有机基板；以及
电性连接该第二芯片与该有机基板。
7.如权利要求6所述的制造方法，更包括：
设置一黏胶于该第一芯片及该第三芯片上；
于设置该第二芯片至该第一芯片及该第三芯片上的该步骤中，该第二芯片透过该黏胶设于该第一芯片及该第三芯片上。
8.如权利要求6所述的制造方法，于结合该芯片组至该有机基板的该步骤之前，该制造方法更包括：
翻转该芯片组。
9.如权利要求6所述的制造方法，其中于电性连接该第二芯片与该有机基板的该步骤包括：
以至少一焊线连接该第二芯片与有机基板。
10.如权利要求9所述的制造方法，更包括：
形成一密封件覆盖该至少一焊线。
CN2010106210310A 2009-12-31 2010-12-23 半导体封装件及其制造方法 Active CN102110678B (zh)

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