CN102098102B - Burst mode code error tester for optical circuit terminal optical module of gigabit passive optical network - Google Patents

Burst mode code error tester for optical circuit terminal optical module of gigabit passive optical network Download PDF

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CN102098102B
CN102098102B CN201110038261.9A CN201110038261A CN102098102B CN 102098102 B CN102098102 B CN 102098102B CN 201110038261 A CN201110038261 A CN 201110038261A CN 102098102 B CN102098102 B CN 102098102B
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circuit
signal
burst
sequential control
control circuit
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CN102098102A (en
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陈志强
袁涛
谭祖炜
陈旭光
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Wuhan Telecommunication Devices Co Ltd
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Wuhan Telecommunication Devices Co Ltd
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Abstract

The invention discloses a kind of burst mode code error tester for optical circuit terminal optical module of gigabit passive optical network, comprise burst hybrid circuit, burst extracts circuit, time-base signal testing circuit, sequential control circuit, burst light generation unit, communication interface circuit and power circuit; By the technical program, achieve requirement Gigabit Passive Optical Network optical line terminal optical module being carried out to performance test; Test platform is built simply, realizes cost low, easy to use; Can by the adjustment of Interface of Computer realization to various parameter, the sequential relationship of various parameter can show intuitively on Interface of Computer, product of the present invention can test the sensitivity of Gigabit Passive Optical Network optical line terminal optical module under different guard time, preamble length, consecutive identical code length, reset pulse position, saturation value and dynamic range easily in a word, thus meets the needs of Gigabit Passive Optical Network optical line terminal optical module performance test.

Description

Burst mode code error tester for optical circuit terminal optical module of gigabit passive optical network
Technical field
The present invention relates to the burst mode code error tester in a kind of communication test set, particularly relate to a kind of Gigabit Passive Optical Network optical line terminal (GPON OLT) optical module burst mode code error tester for the test of Gigabit Passive Optical Network optical line terminal (GPON OLT) optical module burst reception.
Background technology
Recent years, FTTH development is swift and violent, PON is as the preferred option of FTTH, one of core component is wherein exactly OLT optical module, GPON due to high efficiency and full-service ability obtain industry generally acknowledge, adopt P2MP mode, OLT operation of receiver is in burst mode, the code error detecting instrument of burst mode must be adopted to the test of its burst sensitivity, and common Error Detector can only the receiver sensitivity of test job under continuous mode, OLT burst sensitivity test is made to become an industry difficult problem, in the testing scheme that the well-known testing equipment provider in the world (as Agilent company of the U.S. etc.) provides, system building and use complexity, and price is high, limit and promote the use of.
Summary of the invention
In view of this, the technical problem to be solved in the present invention is to provide a kind of for Gigabit Passive Optical Network optical line terminal (GPON OLT) optical module burst mode code error tester, pass through the technical program, Gigabit Passive Optical Network optical line terminal (GPON OLT) optical module can be tested simply and easily at different guard time (GUARD TIME), lead code (PREAMBLE BIT) length, consecutive identical code (CID) length, sensitivity under (RESET) pulse position that resets, saturation value and dynamic range, the needs meeting the research and development of GPON OLT optical module and produce.
For solving the problems of the technologies described above, technical scheme of the present invention is achieved in that Gigabit Passive Optical Network optical line terminal (GPON OLT) optical module burst mode code error tester, comprises burst hybrid circuit, burst extracts circuit, time-base signal testing circuit, sequential control circuit, burst light generation unit, communication interface circuit and power circuit;
Described burst hybrid circuit is connected to burst light generation unit, time-base signal testing circuit, sequential control circuit and pulse pattern generator respectively;
Described burst extracts circuit and is connected to optical module to be measured, sequential control circuit and code error detecting instrument respectively;
Described time-base signal testing circuit is connected with sequential control circuit;
Described sequential control circuit is connected to burst light generation unit, communication interface circuit and optical module to be measured respectively;
Described communication interface circuit is connected to microcomputer respectively;
Described power circuit provides galvanic current pressure for the every circuit described in whole tester and unit.
Detected envelope and the signal starting point of pseudo noise code by time-base signal testing circuit, pseudo noise code is mixed into the uplink burst digital electric signal of designated frame form under the control action of this signal starting point; Burst extraction circuit is treated the sidelight module recovery signal of telecommunication out according to mask signal and is intercepted.
Described burst hybrid circuit is made up of with door fan-out device, high speed or door, level translator, frequency divider, high speed; Described fan-out device is connected with high speed or door, time-base signal testing circuit and pulse pattern generator respectively, high speed or door are connected with door with level translator and high speed respectively, level translator is connected with burst light generation unit respectively, frequency divider is connected with door with high speed with pulse pattern generator respectively, is connected at a high speed with door with sequential control circuit.
Described burst extracts circuit by forming with door and level translator at a high speed, and described high speed and door are connected with optical module to be measured with sequential control circuit, level translator respectively, and level translator is connected with code error detecting instrument respectively.
Described time-base signal testing circuit is made up of envelope detector, signal saltus step latch, level translator; Described envelope detector is connected with burst hybrid circuit, sequential control circuit respectively, and skip signal latch is connected with burst hybrid circuit, sequential control circuit, level translator respectively, and level translator is connected with sequential control circuit respectively.
When carrying out testing, pulse pattern generator (PPG) is to burst hybrid circuit input two paths of signals, and a road signal is insert the long 0 signal pseudo noise code connected of fixed qty each cycle, and another road signal is clock signal, time-base signal testing circuit detects the long 0 signal pseudo noise code of insertion, exports that this pseudo noise code is non-longly connects 0, represents envelope and the starting point detection signal (SD) of (ENVELOP), represent to sequential control circuit with rising edge with logic level, this sequential control circuit is using the starting point of the rising edge of detection signal (SD) as pseudo noise code non-length 0 part, and other timing control signal is using the benchmark of this starting point as time signal, sequential control circuit will represent the end point of the trailing edge of (ENVELOP) as pseudo noise code non-length 0 part using logic level, for giving the use of detection signal (SD) detector reset, clock signal is after frequency division, under the control of lead code enable (PREAMBLE EN) signal, the signal that 0 of designated length and 1 replace is substituted into each long fixed position connecting for 0 cycle, and the pseudo noise code inserting length 0 is mixed into the uplink burst digital electric signal of designated frame form, the burst enable signal 1(BEN1 that two optical network units (ONU) of burst light generation unit send at sequential control circuit) and the enable signal 2(BEN2 that happens suddenly) excitation under, uplink burst digital electric signal is converted to uplink burst light signal, optical module to be measured is given after the photosynthetic ripple of two-way uplink burst, optical module to be measured is under the cooperation of reset signal, the signal of telecommunication is reverted to after this uplink burst light signal is carried out opto-electronic conversion, burst extracts circuit, mask (MASK) signal sent according to sequential control circuit is treated the light-metering module recovery signal of telecommunication out and is intercepted, send needing the part of carrying out Error detection into code error detecting instrument (ED) and carry out error code comparison, complete the test of GPON OLT optical module receptivity.
The technique effect that the present invention reaches is as follows: a kind of Gigabit Passive Optical Network optical line terminal (GPONOLT) optical module burst mode code error tester, by the technical program, achieves requirement GPON OLT optical module being carried out to performance test; Test platform is built simply, realizes cost low, easy to use; Can by the adjustment of Interface of Computer realization to various parameter, the sequential relationship of various parameter can show intuitively on Interface of Computer, product of the present invention can test the sensitivity of GPON OLT optical module under different guard time (GUARD TIME), lead code (PREAMBLE BIT) length, consecutive identical code (CID) length, reset (RESET) pulse position, saturation value and dynamic range easily in a word, thus meets the needs of Gigabit Passive Optical Network optical line terminal (GPON OLT) optical module performance test.
Accompanying drawing explanation
Fig. 1 is anatomical connectivity block diagram of the present invention;
Fig. 2 is the sequential chart of timing control signal;
Fig. 3 is the syndeton block diagram of burst hybrid circuit;
Fig. 4 is the syndeton block diagram that burst extracts circuit;
Fig. 5 is the syndeton block diagram of time-base signal testing circuit;
Fig. 6 is the syndeton block diagram of sequential control circuit;
In figure,
100-burst hybrid circuit;
110-fan-out device circuit,
120-high speed OR circuit,
130-level converter circuit,
140-divider circuit,
150-high speed AND circuit.
200-burst extracts circuit;
210-high speed AND circuit,
220-level converter circuit.
300-time-base signal testing circuit;
310-envelope detector circuit,
320-skip signal latch circuit,
330-level converter circuit.
400-sequential control circuit;
500-burst light generation unit;
600-communication interface circuit;
700-power circuit;
800-pulse pattern generator;
900-optical module to be measured;
1000-code error detecting instrument;
1100-microcomputer.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention and embodiment are described further.
A kind of Gigabit Passive Optical Network optical line terminal (GPON OLT) the optical module burst mode code error tester that the present invention relates to, as shown in Figure 1, burst hybrid circuit 100, burst extraction circuit 200, time-base signal testing circuit 300, sequential control circuit 400, burst light generation unit 500, communication interface circuit 600 and power circuit 700 is comprised;
Described burst hybrid circuit 100 is connected to burst light generation unit 500, time-base signal testing circuit 300, sequential control circuit 400 and pulse pattern generator 800 respectively;
Described burst extracts circuit 200 and is connected to optical module 900 to be measured, sequential control circuit 400 and code error detecting instrument 1000 respectively;
Described time-base signal testing circuit 300 is connected with sequential control circuit 400;
Described sequential control circuit 400 is connected to burst light generation unit 500, communication interface circuit 600 and optical module to be measured 900 respectively;
Described communication interface circuit 600 is connected to microcomputer 1100 respectively;
Described power circuit 700 provides galvanic current pressure for the every circuit described in whole tester and unit.
As shown in Figures 2 and 3, described burst hybrid circuit 100 is made up of with door 150 fan-out device 110, high speed or door 120, level translator 130, frequency divider 140, high speed; Its function is for producing the upstream digital burst signal of telecommunication needed for optical module test; Fan-out device 110 is connected with high speed or door 120, time-base signal testing circuit 300 and pulse pattern generator PPG respectively, high speed or door 120 are connected with door 150 with fan-out device 110, level translator 130 and high speed respectively, level translator 130 respectively with at a high speed or door 120, the light generation unit 500 that happens suddenly be connected, frequency divider 140 is connected with door with high speed with pulse pattern generator respectively, and high speed and door 150 are connected with frequency divider 140, high speed or door 120, sequential control circuit 400 respectively.
Described fan-out device 110 is made up of chip SY58012 and conventional peripheral circuit, its function is that the pseudo noise code of the insertion long 0 produced by signal generator is divided into two-way, one tunnel is continued as high-speed data signal to subsequent conditioning circuit, time-base signal testing circuit 300 is then given on another road, for detecting non-length 0 starting point of the pseudo noise code inserting long 0.
Described high speed or door 120 are made up of chip SY58051 and conventional peripheral circuit, its function is that the pseudo noise code of belt length 0 and high speed are carried out logic OR with the preamble signal that door 150 exports, and produces the uplink burst signal of telecommunication needed for the performance test of GPON OLT optical module.
Described level translator 130 is made up of chip SY89327 and conventional peripheral circuit, and its function converts the electrical signal levels that high speed or door 120 export to ONU to launch the acceptable level of input.
Described frequency divider 140 is made up of chip MC10EP32 and conventional peripheral circuit, and its function is that the clock signal that signal generator produces is carried out 2 frequency divisions, makes the signal rate after frequency division consistent with the pseudo noise code signal rate that signal generator produces.
Described high speed is made up of chip SY58051 and conventional peripheral circuit with door 150, and its function is that the lead code enable signal that the output signal of frequency divider 140 and sequential control circuit 400 send is carried out logical AND, the preamble signal needed for generation.
As shown in Figure 4, described burst extracts circuit 200 by forming with door 210 and level translator 220 at a high speed; Its function is that the signal of telecommunication treating the output of light-metering module intercepts, and extracts the part wherein needing to carry out error code comparison; Described high speed and door 210 are connected with sequential control circuit 400, level translator 220 and optical module to be measured respectively, and level translator 220 is connected with Error Detector ED with door 210 respectively with at a high speed.
Described high speed is made up of chip SY58051 and conventional peripheral circuit with door 210, its function is that the signal extraction enable signal that the signal of telecommunication that exported by optical module to be measured and sequential control circuit 400 export carries out logical AND, intercepts out optical module to be measured and exports the signal section needing to carry out error code comparison in the signal of telecommunication; Level translator 220 is made up of chip SY89327 and conventional peripheral circuit, and its function converts the electrical signal levels exported with door 210 at a high speed to Error Detector acceptable level.
As shown in Figure 5, described time-base signal testing circuit 300 is made up of envelope detector 310, signal saltus step latch 320, level translator 330; Its function is detect non-length 0 starting point of the pseudo noise code inserting long 0; Envelope detector 310 is connected with burst hybrid circuit 100, sequential control circuit 400 respectively, skip signal latch 320 is connected with burst hybrid circuit 100, sequential control circuit 400, level translator 330 respectively, and level translator 330 is connected with signal saltus step latch 320, sequential control circuit 400 respectively.
Described envelope detector 310 is made up of chip SY88149 and conventional peripheral circuit, its function detects the envelope of the pseudo noise code inserting long 0, using the end point of the trailing edge of envelope signal as a cycle period, sequential control circuit 400 detects output latch reset signal after the trailing edge of envelope signal, resets to skip signal latch 320.
Described skip signal latch 320 is made up of chip MC100LVEL51 and conventional peripheral circuit, and its function detects the starting point of the pseudo noise code inserting long 0.The data input pin of signal saltus step latch is pulled to high level, and the pseudo noise code inserting length 0 is connected to the clock input pin of signal saltus step latch, and when clock input pin detects level saltus step, the output of signal saltus step latch also overturns.Can not self-resetting after Latch output signal overturns, the SD RESET reset signal that sequential control circuit 400 sends resets to latch, enables latch catch the starting point inserting the pseudo noise code of long 0 in next circulation.
Described level translator 330 is made up of chip SY89323 and conventional peripheral circuit, and its function converts the electrical signal levels that signal saltus step latch 320 exports to sequential control circuit 400 acceptable level.
As shown in Figure 6, described sequential control circuit 400 is made up of chip V3P250-VQ100, outer clock circuit and conventional peripheral circuit; Chip V3P250-VQ100 is the ProASIC3 series of high speed FPGA of (ACTEL company), programable nonvolatile FlashROM memory and the clock adjustment circuits based on an integrated phase lock (PLL) in the sheet that can provide 1kbit in sheet.This chip is primarily of compositions such as logical block, interconnection resource, clock source, nonvolatile memory, input/output ports; In described time-base signal testing circuit 300, the ENVELOP signal that envelope detector 310 exports and the SD signal that level translator 320 exports give sequential control circuit 400.Sequential control circuit 400 detects the end point of trailing edge as the pseudo noise code of insertion long 0 of ENVELOP signal, and produces latch reset signal to skip signal latch 320 for resetting; Sequential control circuit 400 detects the starting point of rising edge as the pseudo noise code of insertion long 0 of SD signal, OLT reset signal, signal extraction enable signal, lead code enable signal, burst enable signal 1, burst enable signal 2, using this starting point as time reference, can adjust the starting point of above-mentioned control signal and the deration of signal respectively according to the needs of test macro work schedule;
Described sequential control circuit 400 is also connected to communication interface circuit 600, host computer assigns the instruction of each timing control signal adjustment to communication interface circuit 600, and sequential control circuit 400 accepts the instruction from communication interface circuit 600 and adjusts each timing control signal.
About English explanation in Chinese in accompanying drawing of the present invention, GPON-Gigabit Passive Optical Network; FTTH-fiber to the home; P2MP-point-to-multipoint; OLT-optical line terminal; PRBS-pseudo noise code; GUARD TIME-guard time; PREAMBLE BIT-lead code; CID-consecutive identical code; RESET-reset; ONU-optical network unit; FPGA-field programmable gate array; PPG-pulse pattern generator; ED-code error detecting instrument; SD-input; MASK-mask; BEN-happen suddenly enable; PREAMBLE EN-lead code is enable; ENVELOP-envelope; PAYLOAD-payload.
The above, be only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.

Claims (4)

1. Gigabit Passive Optical Network optical line terminal (GPON OLT) optical module burst mode code error tester, it is characterized in that, comprise burst hybrid circuit, burst extracts circuit, time-base signal testing circuit, sequential control circuit, burst light generation unit, communication interface circuit and power circuit;
When carrying out testing, pulse pattern generator (PPG) is to burst hybrid circuit input two paths of signals, and a road signal is insert the long 0 signal pseudo noise code connected of fixed qty each cycle, and another road signal is clock signal, time-base signal testing circuit detects the long 0 signal pseudo noise code of insertion, exports that this pseudo noise code is non-longly connects 0, represents envelope and the starting point detection signal (SD) of (ENVELOP), represent to sequential control circuit with rising edge with logic level, this sequential control circuit is using the starting point of the rising edge of detection signal (SD) as pseudo noise code non-length 0 part, and other timing control signal is using the benchmark of this starting point as time signal, sequential control circuit will represent the end point of the trailing edge of (ENVELOP) as pseudo noise code non-length 0 part using logic level, for giving the use of detection signal (SD) detector reset, clock signal is after frequency division, under the control of lead code enable (PREAMBLE EN) signal, the signal that 0 of designated length and 1 replace is substituted into each long fixed position connecting for 0 cycle, and the pseudo noise code inserting length 0 is mixed into the uplink burst digital electric signal of designated frame form, the burst enable signal 1(BEN1 that two optical network units (ONU) of burst light generation unit send at sequential control circuit) and the enable signal 2(BEN2 that happens suddenly) excitation under, uplink burst digital electric signal is converted to uplink burst light signal, optical module to be measured is given after the photosynthetic ripple of two-way uplink burst, optical module to be measured is under the cooperation of reset signal, the signal of telecommunication is reverted to after this uplink burst light signal is carried out opto-electronic conversion, burst extracts circuit, mask (MASK) signal sent according to sequential control circuit is treated the light-metering module recovery signal of telecommunication out and is intercepted, send needing the part of carrying out Error detection into code error detecting instrument (ED) and carry out error code comparison, complete the test of GPON OLT optical module receptivity,
Described burst hybrid circuit is connected to burst light generation unit, time-base signal testing circuit, sequential control circuit and pulse pattern generator respectively;
Described burst extracts circuit and is connected to optical module to be measured, sequential control circuit and code error detecting instrument respectively;
Described time-base signal testing circuit is connected with sequential control circuit;
Described sequential control circuit is connected to burst light generation unit, communication interface circuit and optical module to be measured respectively;
Described communication interface circuit is connected to microcomputer respectively;
Described power circuit provides galvanic current pressure for the every circuit described in whole tester and unit.
2. burst mode code error tester for optical circuit terminal optical module of gigabit passive optical network according to claim 1, is characterized in that, described burst hybrid circuit is made up of with door fan-out device, high speed or door, level translator, frequency divider, high speed; Described fan-out device is connected with high speed or door, time-base signal testing circuit and pulse pattern generator respectively, high speed or door are connected with door with level translator and high speed respectively, level translator is connected with burst light generation unit respectively, frequency divider is connected with door with high speed with pulse pattern generator respectively, is connected at a high speed with door with sequential control circuit.
3. burst mode code error tester for optical circuit terminal optical module of gigabit passive optical network according to claim 1, it is characterized in that, described burst extracts circuit by forming with door and level translator at a high speed, described high speed and door are connected with optical module to be measured with sequential control circuit, level translator respectively, and level translator is connected with code error detecting instrument respectively.
4. burst mode code error tester for optical circuit terminal optical module of gigabit passive optical network according to claim 1, is characterized in that, described time-base signal testing circuit is made up of envelope detector, signal saltus step latch, level translator; Described envelope detector is connected with burst hybrid circuit, sequential control circuit respectively, and skip signal latch is connected with burst hybrid circuit, sequential control circuit, level translator respectively, and level translator is connected with sequential control circuit respectively.
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CN102832994A (en) * 2012-08-10 2012-12-19 江苏奥雷光电有限公司 Burst testing device and method in production of optical module
CN105162546A (en) * 2015-09-23 2015-12-16 成都乐维斯科技有限公司 Code pattern generation system applied to photoelectric communication
CN110350970B (en) * 2019-07-31 2024-05-17 深圳市亚派光电器件有限公司 Testing device and method for optical line terminal
CN110417465B (en) * 2019-07-31 2020-11-06 深圳市亚派光电器件有限公司 Optical signal testing method, system, device and readable storage medium
CN110445687A (en) * 2019-08-12 2019-11-12 太仓市同维电子有限公司 A kind of HGU product startup function test method and device

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CN1761181A (en) * 2005-11-04 2006-04-19 清华大学 Device for testing time characteristic of outburst and error rate in outburst optical fiber transmission system
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