CN102081680B

CN102081680B - Method for modeling P-channel metal oxide semiconductor (PMOS) one-time programmable memory (OTP) device

Info

Publication number: CN102081680B
Application number: CN2009102018812A
Authority: CN
Inventors: 王正楠
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2009-11-30
Filing date: 2009-11-30
Publication date: 2012-08-01
Anticipated expiration: 2029-11-30
Also published as: CN102081680A

Abstract

The invention discloses a method for modeling a P-channel metal oxide semiconductor (PMOS) one-time programmable memory (OTP) device. In the method, an equivalent circuit is established according to the structure and working principle of the PMOS OTP device; the structure of the equivalent circuit mainly comprises a PMOS selection transistor and a PMOS floating gate transistor, wherein the selection transistor and the floating gate transistor form a serial connection structure, and have the same bulk potential; a parasitic diode is connected between the drain terminal and bulk potential of the floating gate transistor; the gate of the floating gate transistor is connected with a voltage controlled voltage source for simulating the gate coupling voltage of the floating gate transistor; the voltage of the voltage controlled voltage source is proportional to the gate source voltage difference of the selection transistor, and the proportional coefficient is fixed; and a corresponding simulation program with integrated circuit emphasis (SPICE) macro-model is established according to the equivalent circuit. The method has physical significance while being used for well describing the electric characteristic of the PMOS OTP device.

Description

The modeling method of PMOS OTP parts

Technical field

The semiconductor system of the present invention relates to integrated circuit fields especially relates to a kind of modeling method of PMOS OTP parts

Background technology

PMOS OTP (one-time programmable memory) device is that the coupling capacitance dividing potential drop through FET realizes the novel memory device that electronics writes.Its device architecture is as shown in Figure 1; Be the series connection of two P type metal-oxide-semiconductor field effect transistors (PMOS), two PMOS devices are made in the same N trap, and left side PMOS is that PMOS selects pipe; Said PMOS selects the grid of pipe as the gate voltage input end, and it is a polysilicon gate that said PMOS selects the grid of pipe; The PMOS on the right is the PMOS floating-gate pipe, is a floating boom at the grid of said PMOS floating-gate pipe, and said floating boom is used for stored charge, and what current potential the grid of said PMOS floating-gate pipe do not take over.Said PMOS selects the drain terminal of pipe and the shared active area of source end of said PMOS floating-gate pipe, and said N type trap connects the one end.When said PMOS floating-gate pipe drain terminal and body end add fixedly voltage bias; When said PMOS selects Guan Yuanduan to add scanning voltage; Voltage difference between the grid of said PMOS floating-gate pipe and the overlap capacitance between the source can be leaked a part of source is coupled on the grid of said PMOS floating-gate pipe, thereby controls said floating gate PMOS channel current.

Said PMOS OTP parts need be realized writing through programming, thereby distinguishes the store status of said PMOS OTP parts.Program conditions is that said PMOS selects pipe grid end and source end to keep zero potential, and at voltage pulse signal of body end input, voltage amplitude is 8V, and the burst length is 100 microseconds.Channel electrons is written in the floating boom of said PMOS floating-gate pipe through this pulse signal; The floating boom negative charge is increased; Thereby reduced the cut-in voltage of said PMOS floating-gate pipe, can strengthen of the control of the grid coupled voltages of said PMOS floating-gate pipe said PMOS floating-gate pipe channel current.Shown in Fig. 2 A; Be the input curve of PMOS OTP parts before programming; Gate voltage shown in its horizontal ordinate is that said PMOS selects the gate source voltage of pipe poor, and ordinate is represented the channel current of device, and different curve representations are the current conditions under the consubstantiality terminal voltage bias condition not; Owing to do not have electronics to write in the floating boom of said PMOS floating-gate pipe before the programming; Raceway groove cut-in voltage under the floating boom is higher, and the raceway groove below the grid coupled voltages of said PMOS floating-gate pipe makes is in critical unlatching or inferior opening all the time, so this channel resistance changes along with the variation of the grid coupled voltages of PMOS floating-gate pipe; If bulk potential adds positive voltage bias simultaneously, it is just very little then to flow through channel current.Shown in Fig. 2 B, be the input curve of PMOS OTP parts before programming, after programming; Electronics is written on the floating boom of said PMOS floating-gate pipe; Because negative charge increases in the floating boom, the raceway groove cut-in voltage below making diminishes, and this causes the grid coupled voltages of said PMOS floating-gate pipe different to the control situation meeting of its raceway groove; This moment, floating-gate device was operated in linear district, so channel current becomes big.Channel current before and after the programming can be different fully thus, thereby reach information storage function.The PMOS OTP parts has area little; Advantages such as the write time is short; But its device property is very different with conventional FET; Common FET SPICE model can't be applicable to again describes this device, therefore is necessary to develop a kind of novel equivalent-circuit model and comes described.

Summary of the invention

Technical matters to be solved by this invention provides a kind of modeling method of PMOS OTP parts, and the electrical characteristics of description PMOS OTP parts that can be good have physical significance simultaneously again.

For solving the problems of the technologies described above; The present invention provides a kind of modeling method of PMOS OTP parts; Said PMOS OTP parts comprises PMOS and selects pipe and a PMOS floating-gate pipe, and said PMOS selects to manage and the PMOS floating-gate pipe is together in series and be produced in the same N type trap, with said PMOS floating-gate pipe as storage unit; Said PMOS selects the drain terminal of pipe and the shared active area of source end of said PMOS floating-gate pipe, and said N type trap connects the one end.What current potential the grid of said PMOS floating-gate pipe do not take over during work, and the voltage between leak in the source that will be added in through the overlap capacitance between the source grid of said PMOS floating-gate pipe is coupled in the grid of said PMOS floating boom, thereby controls said PMOS floating-gate pipe channel current.The modeling method of PMOS OTP parts of the present invention comprises the steps:

Step 1, set up a cover equivalent electrical circuit according to the structure of said PMOS OTP parts and principle of work; Equivalent circuit structure comprises: a PMOS selection pipe, a PMOS floating-gate pipe, the cascaded structure that the drain terminal of said PMOS selection pipe and a PMOS selection of PMOS floating-gate pipe formation pipe and the source end of PMOS floating-gate pipe are connected; Said PMOS selects the bulk potential series connection of pipe and PMOS floating-gate pipe, and said PMOS selects termination source, source voltage, the grid of pipe to connect grid voltage; The drain terminal of said PMOS floating-gate pipe connects drain voltage and between drain terminal and said bulk potential, inserts a parasitic diode; The grid of said PMOS floating-gate pipe connect a VCVS; Simulate the grid coupled voltages of said PMOS floating-gate pipe with said VCVS, the voltage of said VCVS and said PMOS select the gate source voltage difference of pipe to be directly proportional and scale-up factor is fixed;

Step 2, set up corresponding SPICE macro model according to said equivalent electrical circuit; Confirm the voltage of said VCVS and the scale-up factor that said PMOS selects the gate source voltage difference of pipe to be directly proportional through the match of emulation and real data, and said PMOS selects the model parameter of pipe, PMOS floating-gate pipe, parasitic diode.

Step 2 is said to be set up corresponding SPICE macro model according to equivalent electrical circuit and comprises: through the HSPICE language and adopt the macro model structure to be write said equivalent electrical circuit as the electronic circuit statement form; Electronic circuit is updated to model extracts in the software, extract correlation parameter through the match of emulation and measured data; Select the BSIM4 parameter of pipe to come the said PMOS OTP parts of match subthreshold current through regulating said PMOS; Regulate the electric current of the said PMOS OTP parts of BSIM4 parameter fitting of said PMOS floating-gate pipe, regulate the scale-up factor that voltage and the said PMOS of said VCVS select the gate source voltage difference of pipe to be directly proportional simultaneously and control the current slope of said PMOS OTP parts in the high gate voltage zone in the grid voltage upper zone.

The present invention can be good the electrical characteristics of description PMOS OTP parts have simultaneously physical significance again

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:

Fig. 1 is a PMOS OTP parts structural drawing;

Fig. 2 A-Fig. 2 B is the input curve before and after the programming of PMOS OTP parts;

Fig. 3 is the process flow diagram of the modeling method of PMOS OTP parts of the present invention;

Fig. 4 is the equivalent-circuit model synoptic diagram of the PMOS OTP parts of the embodiment of the invention;

Fig. 5 A-Fig. 5 B is the emulation fitting result of input curve of PMOS OTP parts SPICE electronic circuit macro model before and after programming of the foundation of the embodiment of the invention.

Embodiment

Be illustrated in figure 3 as the process flow diagram of the modeling method of PMOS OTP parts of the present invention, the present invention includes following steps:

Step 1, set up a cover equivalent electrical circuit according to the structure of said PMOS OTP parts and principle of work.As shown in Figure 4, equivalent circuit structure comprises: a PMOS selection pipe, a PMOS floating-gate pipe, the cascaded structure that the drain terminal of said PMOS selection pipe and a PMOS selection of PMOS floating-gate pipe formation pipe and the source end of PMOS floating-gate pipe are connected; Said PMOS selects the bulk potential series connection of pipe and PMOS floating-gate pipe, and said PMOS selects termination source, source voltage, the grid of pipe to connect grid voltage; The drain terminal of said PMOS floating-gate pipe connects drain voltage and between drain terminal and said bulk potential, inserts a parasitic diode; The grid of said PMOS floating-gate pipe connect a VCVS; Simulate the grid coupled voltages of said PMOS floating-gate pipe with said VCVS, the voltage of said VCVS and said PMOS select the gate source voltage difference of pipe to be directly proportional and scale-up factor is fixed.

Step 2, set up corresponding SPICE macro model according to said equivalent electrical circuit; Confirm the voltage of said VCVS and the scale-up factor that said PMOS selects the gate source voltage difference of pipe to be directly proportional through the match of emulation and real data, and said PMOS selects the model parameter of pipe, PMOS floating-gate pipe, parasitic diode.Be through the HSPICE language in the present embodiment and adopt the macro model structure to be write said equivalent electrical circuit as the electronic circuit statement form; The SPICE electronic circuit macro model that obtains is updated to membranous type extracts in the software, extract correlation parameter through the match of emulation and measured data; Select the BSIM4 parameter of pipe to come the said PMOS OTP parts of match subthreshold current through regulating said PMOS; Regulate the electric current of the said PMOS OTP parts of BSIM4 parameter fitting of said PMOS floating-gate pipe, regulate the scale-up factor that voltage and the said PMOS of said VCVS select the gate source voltage difference of pipe to be directly proportional simultaneously and control the current slope of said PMOS OTP parts in the high gate voltage zone in the grid voltage upper zone.

Be respectively the emulation fitting result of the input curve of PMOS OTP parts SPICE electronic circuit macro model before and after programming of the foundation of the embodiment of the invention like Fig. 5 A and Fig. 5 B; Gate voltage shown in its horizontal ordinate is that said PMOS selects the gate source voltage of pipe poor; Ordinate is represented the channel current of device; The ordinate of left figure is a linear coordinate, and the ordinate of right figure is logarithmic coordinate, and different curve representations are the current conditions under the consubstantiality terminal voltage bias condition not; Its dotted line is represented measured data, realizes the result who obtains after the representative model emulation.Shown in Fig. 5 A, before programming, M2 raceway groove cut-in voltage in this device is because higher, and the raceway groove below coupling voltage of float grating makes is in critical unlatching and inferior opening all the time, so the electric current of device is very little.Shown in Fig. 5 B, after the programming, owing to writing of electronics in the floating boom, the raceway groove cut-in voltage below making diminishes, and makes floating-gate device be operated in linear district.This shows that this set of model can both satisfy the precision characteristic requirement before programming with after the programming, conform to actual conditions fully.

More than through specific embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.

Claims

1. the modeling method of a PMOS OTP parts; Said PMOS OTP parts comprises a PMOS and selects pipe and a PMOS floating-gate pipe; Said PMOS selects pipe and PMOS floating-gate pipe to be together in series and is produced in the same N type trap; As storage unit, said PMOS selects the drain terminal of pipe and the shared active area of source end of said PMOS floating-gate pipe with said PMOS floating-gate pipe, and said N type trap connects the one end; What current potential the grid of said PMOS floating-gate pipe do not take over during work, and the voltage between leak in the source that will be added in through the overlap capacitance between the source grid of said PMOS floating-gate pipe is coupled in the grid of said PMOS floating boom, thereby controls said PMOS floating-gate pipe channel current; It is characterized in that, comprise step:

2. the modeling method of PMOS OTP parts according to claim 1 is characterized in that: step 2 is said to be set up corresponding SPICE macro model according to equivalent electrical circuit and comprises:

Through the HSPICE language and adopt the macro model structure to be write said equivalent electrical circuit as the electronic circuit statement form;

Electronic circuit is updated to model extracts in the software, extract correlation parameter through the match of emulation and measured data; Select the BSIM4 parameter of pipe to come the said PMOS OTP parts of match subthreshold current through regulating said PMOS; Regulate the electric current of the said PMOS OTP parts of BSIM4 parameter fitting of said PMOS floating-gate pipe, regulate the scale-up factor that voltage and the said PMOS of said VCVS select the gate source voltage difference of pipe to be directly proportional simultaneously and control the current slope of said PMOS OTP parts in the high gate voltage zone in the grid voltage upper zone.