CN102081582A - Method for operating flash memory on bus - Google Patents
Method for operating flash memory on bus Download PDFInfo
- Publication number
- CN102081582A CN102081582A CN2011100200659A CN201110020065A CN102081582A CN 102081582 A CN102081582 A CN 102081582A CN 2011100200659 A CN2011100200659 A CN 2011100200659A CN 201110020065 A CN201110020065 A CN 201110020065A CN 102081582 A CN102081582 A CN 102081582A
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- CN
- China
- Prior art keywords
- flash memory
- data
- reading command
- activation
- read
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 230000015654 memory Effects 0.000 title claims abstract description 142
- 238000000034 method Methods 0.000 title claims abstract description 28
- 230000004913 activation Effects 0.000 claims description 50
- 238000010586 diagram Methods 0.000 description 6
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
Abstract
The invention discloses a method for operating a flash memory on a bus, which comprises the following steps: enabling a reading command of a first flash memory, and entering a busy waiting time by a ready/busy signal of the first flash memory when the reading command of the first flash memory is finished. When the read command of the first flash memory is enabled, the read command of a second flash memory is enabled. When the busy waiting time is over, the data of the first flash memory is read. When the data reading of the first flash memory is finished, the reading instruction of the first flash memory is enabled again. When the read command of the first flash memory is enabled again, the data of the second flash memory is read. And when the data reading of the second flash memory is finished, enabling the reading instruction of the second flash memory again.
Description
Technical field
The present invention is meant a kind of method of operating two flash memories on a bus especially relevant for a kind of method of operating flash memory.
Background technology
Please refer to Fig. 1, Fig. 1 reads when moving for a flash memory being done when main frame (host) in explanation on the time shaft, ready/busy commonplace (ready/busy) signal, reads the synoptic diagram of activation (read enable) and chip enable (chipenable) signal.As shown in Figure 1, when the reading command of main frame activation finishes, ready/busy commonplace (ready/busy) signal R/B can enter the busy waiting time (busy waiting time) T2.After busy waiting time T 2 finished, main frame began to switch (toggle) and reads enable signal RE.And enable signal RE is once read in every switching, can read the data that store in the flash memory according to the data storing position (address) in the reading command.When beginning to switch when reading enable signal RE, chip enable signal CE transfers logic low potential to by logic high potential.In addition, in the working specification of flash memory, the time T 3 of reading of data is greater than busy waiting time T 2, and busy waiting time T 2 is greater than the time T 1 of reading command.
Please refer to Fig. 2, Fig. 2 utilizes the time interval of busy waiting time for explanation prior art on time shaft, and main frame is made the synoptic diagram that reads action to two flash memories simultaneously.As shown in Figure 2, when on bus, finishing corresponding to the reading command A of first flash memory, because commonplace signal ch0AR/B enters busy waiting time BWT1 corresponding to the ready/busy of first flash memory, so main frame can utilize the time interval of busy waiting time BWT1, activation is corresponding to the reading command B of second flash memory.After busy waiting time BWT1 finished, main frame began to read the data F1Data that stores in first flash memory.When main frame finishes to read the data F1Data that stores in first flash memory, also finish corresponding to the busy waiting time BWT2 of second flash memory, so main frame can read the data F2Data that stores in second flash memory at once.When main frame finishes to read the data F2Data that stores in second flash memory, main frame activation reading command once more A.So, repeat above-mentioned steps, main frame can be operated two flash memories on same bus.
Though main frame sees through above-mentioned prior art can operate two flash memories on same bus.But as shown in Figure 2, the data of on bus, being transmitted arrange undertighten, that is bus has some standby times.Therefore, the operating efficiency of prior art does not reach the optimum efficiency of two flash memories of operation on same bus.
Summary of the invention
One embodiment of the invention provide a kind of method of operating flash memory.This method comprises the reading command of activation one first flash memory, so that the commonplace signal of the ready/busy of this first flash memory enters the busy waiting time; After the reading command of this first flash memory is finished activation, the reading command of activation one second flash memory; When this busy waiting time finishes, begin to read the data of this first flash memory; When the data read of this first flash memory finishes, the reading command of this first flash memory of activation again; When the reading command of this first flash memory is finished activation again, begin to read the data of this second flash memory; Reach when the data read of this second flash memory finishes, again the reading command of this second flash memory of activation.
A kind of method of operating flash memory provided by the present invention, this method is operated the order of two flash memories for being the reading command of activation one first flash memory, the reading command of activation one second flash memory at the beginning, all is the step of the reading command of the data that repeat to read this first flash memory, the reading command of this first flash memory of activation, the data that read this second flash memory and this second flash memory of activation backward.Therefore, the data that the present invention is transmitted on a bus can be arranged closelyr than prior art, and are more efficient.
Description of drawings
Fig. 1 reads when moving for a flash memory being done when main frame in explanation on the time shaft, the commonplace signal of ready/busy, reads the synoptic diagram of activation and chip enable signal;
Fig. 2 utilizes the time interval of busy waiting time for explanation prior art on time shaft, and main frame is made the synoptic diagram that reads action to two flash memories simultaneously;
Fig. 3 provides a kind of process flow diagram of operating the method for two flash memories on a bus for one embodiment of the invention;
Fig. 4 is the sequential chart of Fig. 3 method.
Wherein, Reference numeral:
The T1 reading command time
T2, BWT1, BWT2 busy waiting time
The T3 reading of data time
R/B, ch0AR/B, the commonplace signal of ch0BR/B ready/busy
RE, REA, REB read enable signal
CE, CEA, CEB chip enable signal
F1Data, F2Data data
The 30-40 step
Δ T1, Δ T2 cycle
Embodiment
Please refer to Fig. 3 and Fig. 4, Fig. 3 provides a kind of process flow diagram of operating the method for two flash memories on a bus for one embodiment of the invention, and Fig. 4 is the sequential chart of Fig. 3 method.The detailed step of the method for Fig. 3 is as follows:
Step 30: beginning;
Step 32: the reading command A of main frame (host) activation first flash memory;
Step 34: after the reading command A of first flash memory finishes activation, the reading command B of main frame activation second flash memory;
Step 36: when the busy waiting time of the commonplace signal ch0AR/B of the ready/busy of first flash memory BWT1 finished, main frame began to read the data F1Data of first flash memory;
Step 38: when the data F1Data of first flash memory reads when finishing, main frame is the reading command A of activation first flash memory again;
Step 40: when the reading command A of first flash memory finished activation again, main frame began to read the data F2Data of second flash memory;
Step 42: when the data F2Data of second flash memory reads when finishing, main frame is the reading command B of activation second flash memory again;
Step 44: when the reading command B of second flash memory finished activation again, main frame began to read the data F1Data of first flash memory, rebound step 38.
In step 34, when main frame can be finished activation at the reading command A of first flash memory or the reading command A of first flash memory finish a schedule time after the activation, the reading command B of activation one second flash memory.In this embodiment, as long as the busy waiting time BWT2 of the commonplace signal ch0BR/B of ready/busy finished before the reading command A of first flash memory of main frame activation again finishes.In step 36, main frame read the data F1Data of first flash memory, and enable signal REA is read in every switching for one time first according to the data storing position that is comprised in the reading command A, and main frame promptly can read the data of one first flash memory.In step 40, main frame read the data F2Data of second flash memory, and enable signal REB is read in every switching for one time second according to the data storing position that is comprised in the reading command B, and main frame promptly can read the data of one second flash memory.In addition, when read first flash memory data F1Data the time, the chip enable signal CEA of first flash memory transfers logic low potential to by logic high potential, this moment main frame only can do the action of reading to first flash memory; When read second flash memory data F2Data the time, the chip enable signal CEB of second flash memory transfers logic low potential to by logic high potential, this moment main frame only can do the action of reading to second flash memory.
In sum, method of on a bus, operating flash memory provided by the present invention, though the same with prior art all is the time interval operation flash memory that utilizes the busy waiting time, the difference of the present invention and prior art is that the order of operation flash memory of the present invention is the reading command of the reading command of activation first flash memory, the reading command of activation second flash memory, the data that read first flash memory, the reading command of activation first flash memory, the data that read second flash memory, the reading command of activation second flash memory, the data that read first flash memory, activation first flash memory.Having only is the reading command of activation first flash memory and the reading command of activation second flash memory at the beginning, all is the step of the reading command of the data that repeat to read first flash memory, the reading command of activation first flash memory, the data that read second flash memory and activation second flash memory backward.Therefore, the data that the present invention is transmitted on bus can be arranged closelyr than prior art, and are more efficient, that is the cycle Δ T2 of operation flash memory of the present invention can be less than the cycle Δ T1 of the operation flash memory of prior art.
The above only is preferred embodiment of the present invention, and all equalizations of being made according to claim protection domain of the present invention change and revise, and all should belong to covering scope of the present invention.
Claims (11)
1. the method for an operation flash memory on a bus is characterized in that, comprises:
The reading command of activation one first flash memory is so that the commonplace signal of the ready/busy of this first flash memory enters the busy waiting time;
After the reading command of this first flash memory is finished activation, the reading command of activation one second flash memory;
When this busy waiting time finishes, begin to read the data of this first flash memory;
When the data read of this first flash memory finishes, the reading command of this first flash memory of activation again;
When the reading command of this first flash memory is finished activation again, begin to read the data of this second flash memory; And
When the data read of this second flash memory finishes, the reading command of this second flash memory of activation again.
2. the method for claim 1 is characterized in that, also comprises when the reading command of this second flash memory is finished activation again, begins to read the data of this first flash memory.
3. the method for claim 1 is characterized in that, after the reading command of this first flash memory was finished activation, the reading command of activation one second flash memory was when the reading command of this first flash memory is finished activation, the reading command of activation one second flash memory.
4. the method for claim 1, it is characterized in that, after the reading command of this first flash memory was finished activation, the reading command of activation one second flash memory was a schedule time after the reading command of this first flash memory is finished activation, the reading command of activation one second flash memory.
5. the method for claim 1 is characterized in that, the reading command of this first flash memory also comprises the data storing position of this first flash memory.
6. method as claimed in claim 5 is characterized in that, reads the data storing position of data based this first flash memory of this first flash memory, reads the data relevant for this data storing position of this first flash memory.
7. the method for claim 1 is characterized in that, the reading command of this second flash memory also comprises the data storing position of this second flash memory.
8. method as claimed in claim 7 is characterized in that, reads the data storing position of data based this second flash memory of this second flash memory, read relevant for this second flash memory the data of this data storing position.
9. the method for claim 1 is characterized in that, this first flash memory and this second flash memory are shared a bus.
10. the method for claim 1 is characterized in that, also comprises:
When reading the data of this first flash memory, switch first of this first flash memory and read enable signal; And
Once this first reads enable signal in every switching, reads the data relevant for this data storing position of this first flash memory.
11. the method for claim 1 is characterized in that, also comprises:
When reading the data of this second flash memory, switch second of this second flash memory and read enable signal; And
Once this second reads enable signal in every switching, reads the data relevant for this data storing position of this second flash memory.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099142796 | 2010-12-08 | ||
| TW099142796A TWI459206B (en) | 2010-12-08 | 2010-12-08 | Method for operating flash memories on a bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102081582A true CN102081582A (en) | 2011-06-01 |
Family
ID=44087555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100200659A Pending CN102081582A (en) | 2010-12-08 | 2011-01-13 | Method for operating flash memory on bus |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9152583B2 (en) |
| CN (1) | CN102081582A (en) |
| TW (1) | TWI459206B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103177772A (en) * | 2011-12-20 | 2013-06-26 | 绿智慧流科技公司 | Flash memory test method |
| CN116661684A (en) * | 2023-05-10 | 2023-08-29 | 珠海妙存科技有限公司 | Flash memory data reading method, system, equipment and medium |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3312883B1 (en) | 2016-10-19 | 2021-12-29 | IMEC vzw | Semiconductor devices with increased charge carrier concentration |
| TWI726541B (en) * | 2019-12-17 | 2021-05-01 | 大陸商合肥兆芯電子有限公司 | Memory management method, memory storage device and memory control circuit unit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1741193A (en) * | 2004-07-30 | 2006-03-01 | 株式会社瑞萨科技 | Nonvolatile memory apparatus |
| CN101082891A (en) * | 2007-05-10 | 2007-12-05 | 忆正存储技术(深圳)有限公司 | Paralleling flash memory controller |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5920884A (en) * | 1996-09-24 | 1999-07-06 | Hyundai Electronics America, Inc. | Nonvolatile memory interface protocol which selects a memory device, transmits an address, deselects the device, subsequently reselects the device and accesses data |
| US7853774B1 (en) * | 2005-03-25 | 2010-12-14 | Tilera Corporation | Managing buffer storage in a parallel processing environment |
| US7606992B1 (en) * | 2005-12-01 | 2009-10-20 | Chris Karabatsos | High performance data rate system for flash devices |
| US20070245061A1 (en) * | 2006-04-13 | 2007-10-18 | Intel Corporation | Multiplexing a parallel bus interface and a flash memory interface |
| US7788473B1 (en) * | 2006-12-26 | 2010-08-31 | Oracle America, Inc. | Prediction of data values read from memory by a microprocessor using the storage destination of a load operation |
| US7865644B2 (en) * | 2007-10-30 | 2011-01-04 | International Business Machines Corporation | Method and apparatus for attaching multiple slave devices to a single bus controller interface while supporting command pipelining |
| US10079048B2 (en) * | 2009-03-24 | 2018-09-18 | Western Digital Technologies, Inc. | Adjusting access of non-volatile semiconductor memory based on access time |
-
2010
- 2010-12-08 TW TW099142796A patent/TWI459206B/en not_active IP Right Cessation
-
2011
- 2011-01-13 CN CN2011100200659A patent/CN102081582A/en active Pending
- 2011-04-14 US US13/087,361 patent/US9152583B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1741193A (en) * | 2004-07-30 | 2006-03-01 | 株式会社瑞萨科技 | Nonvolatile memory apparatus |
| CN101082891A (en) * | 2007-05-10 | 2007-12-05 | 忆正存储技术(深圳)有限公司 | Paralleling flash memory controller |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103177772A (en) * | 2011-12-20 | 2013-06-26 | 绿智慧流科技公司 | Flash memory test method |
| CN116661684A (en) * | 2023-05-10 | 2023-08-29 | 珠海妙存科技有限公司 | Flash memory data reading method, system, equipment and medium |
| CN116661684B (en) * | 2023-05-10 | 2024-02-23 | 珠海妙存科技有限公司 | Flash memory data reading method, system, equipment and medium |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI459206B (en) | 2014-11-01 |
| US20120151122A1 (en) | 2012-06-14 |
| US9152583B2 (en) | 2015-10-06 |
| TW201224757A (en) | 2012-06-16 |
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Application publication date: 20110601 |