CN103426475A - Method and device for reducing chip block erasing time - Google Patents
Method and device for reducing chip block erasing time Download PDFInfo
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- CN103426475A CN103426475A CN2013103401199A CN201310340119A CN103426475A CN 103426475 A CN103426475 A CN 103426475A CN 2013103401199 A CN2013103401199 A CN 2013103401199A CN 201310340119 A CN201310340119 A CN 201310340119A CN 103426475 A CN103426475 A CN 103426475A
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Abstract
The invention provides a method for reducing chip erasing time. An erased chip is randomly refreshed, the influence of erasing on Blocks is effectively reduced, and meanwhile the refreshing time is effectively reduced. The method comprises the following steps: preprogramming a memory region needing to be erased; erasing the memory region needing to be erased; refreshing the program of other units in flash memory. The method is characterized in that the program refreshing is carried out only aiming at part of memory units, and the addresses of the memory units are randomly generated by a random-number generator. Correspondingly, the invention provides a device for shortening the chip erasing time.
Description
Technical field
The present invention relates to the flash memory field, concrete, relate to a kind of reduction NOR flash(flash memory) apparatus and method in piece erasing time.
Technical background
NOR FLASH is in the market one of main nonvolatile flash memory technology, and the transfer efficiency of NOR FLASH is very high, has very high cost benefit when the low capacity of 1～4MB.Nor Flash storage area is in order to save chip area, generally all adopt physical centralization to place, form a storage matrix, then logically be divided into a lot of pieces, this structures shape when one of them piece is carried out to erase operation, because this piece physically is connected with source region with piece drain region on every side, tend to other adjacent pieces are exerted an influence.Usually, cross and wipe for fear of piece " storage unit ", generally, before erase operation, all do pre-programmed one time, in whole " storage unit " of the piece of like this needs being wiped, be whole the becoming " 0 " of " 1 ", and then the piece that needs are wiped carry out erase operation.Because the drain region of " storage unit " between piece connects together, cause pre-programmed operation meeting to exert an influence to the adjacent blocks of data of wiping that do not need, as long as influence time has enough just changed the data of " storage unit ".
Current in the industry in order well to address this problem, generally adopt after piece is wiped, refreshed programming operation to affected, this mode can solve above problem, but refresh programming operation all affected " storage unit " require a great deal of time, indirectly increased the erasing time of chip.
Summary of the invention
The present invention proposes a kind of method that reduces the chip block erasing time, undertaken, with advancing to refresh, not only effectively having reduced to wipe the impact between storage block by the chip to after wiping, effectively reduced to refresh required time simultaneously.The method comprises the steps:
The storage area that needs are wiped carries out pre-programmed, and all storage unit in this zone all are written as to 0;
The storage area that needs are wiped is wiped, and just all storage unit in this zone all are written as 1;
Remaining element in flash memory is refreshed to programming;
It is characterized in that, describedly refresh programming and only carry out for partial memory cell, the address of this storage unit is produced at random by tandom number generator.
The present invention also provides a kind of device that reduces the chip erase time, and this device comprises:
The erase command receiver module, for receiving erase command;
The pre-programmed module, carry out pre-programmed for the storage area to needing erasing flash memory, and all storage unit in this zone all are written as to 0;
Piece is wiped module, for the storage area to needing erasing flash memory, is wiped, and just all storage unit in this zone all are written as 1;
Random number generator, need to be refreshed the address of the storage unit of programming for random generation;
Refresh programming module, for the address of the storage unit to being generated by random number generator, refreshed programming.
Much less than affected address space in described random refresh address space, because this address space is a random number, the establishment address of refreshing programming that chip is done in each erase operation like this is all random, angle from probability, this address will mean allocation in the affected address space of chip, thereby need not all to the unit of all being crosstalked, do and refresh programming at every turn, greatly saved programming time, thereby saved the time of erase operation, improved the performance of chip.
The accompanying drawing explanation
Fig. 1 is the partial circuit figure of Nor flash chip storage area;
Fig. 2 is that the present invention realizes the process flow diagram of wiping;
Fig. 3 is the structure principle chart of random number generator.
Embodiment
The invention provides a kind of method that reduces the chip erase time that the present invention proposes, undertaken, with advancing to refresh, not only effectively having reduced to wipe the impact between storage block by the chip to after wiping, effectively reduced to refresh required time simultaneously.For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.
Below describe embodiments of the invention in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label means same or similar element or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
Next will according to the process flow diagram shown in Fig. 2, the present invention is described in detail, concrete steps are as follows:
In step S101, input port information by order receiver module receiving chip, comprise erasable order and address information, decoding circuit is after receiving this signal, send corresponding order and data to pre-programmed operational module and random number generator module, thereby start piece erase status machine, produce the random number module enable signal simultaneously.
In step S110, the commencing signal sent according to S101, random number generator produces random data, the end signal sent according to S108, the random data that produce that reset, to guarantee that each random number generated is all random.
In step S102, carry out the pre-programmed operation, after the pre-programmed operational module receives the erasable order of piece of S101, all address spaces that erasable block address is wiped current needs as required carry out pre-programmed.Concrete, suppose that block address is: [A24:A12]=12 ' hFFF, the address space of pre-programmed is 24 ' hFFF000～24 ' hFFFFFF so, at first this module loads start address 24 ' hFFF000, then pass through address decoding circuitry, the storage tube that current address is selected carries out pre-programmed, after the current address programming finishes, enters the pre-programmed judge module.
In step S103, carry out the pre-programmed judgement, judge whether current address needs to carry out programming operation in advance, also judge whether current address is the maximum space in piece simultaneously, if current address is not the maximum address of current block, address adds one automatically, turns back to S102 simultaneously, carries out the pre-programmed operation of second address space.If current address is the maximum address of current block, directly return S104, completed the pre-programmed operation in block address space simultaneously, the data of the current block made are all the states of " 0 ".
In step S104, carry out the piece erase operation, according to current block address information, corresponding piece is carried out to erase operation, all control gates of current block connect negative high voltage (9.2V left and right), and substrate connects positive high voltage (6v left and right), and source region and drain region are in floating potential, omit the existence of living diode to source due to substrate, the current potential in source region and drain region approaches substrate electric potential.In this case, complete the piece erase operation of chip, enter piece simultaneously and wipe judge module.
In step S105, carry out piece and wipe judgement, judge whether the interior data of all address spaces of current block are all the states of " 1 ".If one that an address space is arranged is not the state of " 1 ", just need to return to S104, re-start erase operation.When all address spaces of judgement current block are all the state of " 1 ", enter and load the random number module.
In step S106, loaded random number, whether the random data that at first judgement loading randomizer produces is identical with the block address of current block operation, if identical, random data is added to 1, then be loaded in the block address of refresh operation, if not identical, random data directly is loaded in block address, then enters and refreshes the programming operation module.
In step S107, refreshed programming operation, after refreshing the random refresh block address that the programming operation module receives S107, all address spaces that the block address refreshed as required refreshes current needs are refreshed programming.
Concrete, suppose that random refresh block address is: [A24:A12]=12 ' h111, the address space that refreshes so programming is 24 ' h111000～24 ' h111FF, at first this module loads start address 24 ' h111000, then pass through address decoding circuitry, the storage tube that current address is selected is refreshed programming, after the current address programming finishes, enters and refreshes the programming judge module.
In step S108, refreshed the programming judge module, judge whether current address needs to be refreshed programming operation, also judge whether current address is the maximum space refreshed in piece simultaneously, if current address is not the current maximum address that refreshes piece, address adds one automatically, turns back to S107 simultaneously, carries out the programming operation that refreshes of second address space.If current address is the current maximum address that refreshes piece, directly return S109, completed the refresh operation of current block simultaneously, the affected data of the current block made have all become the state that recovers original, then produce random number module reset signal.
In step S109, end block is wiped, and the signal of coming according to step S108 feedback, finish the current block erase operation, the reseting address register, and data register and control signal, correctly used in order to next operation.
Accordingly, the invention provides the device in a kind of NOR of reduction flash piece erasing time, this device comprises: erase command receiver module, pre-programmed module, piece are wiped module, random number generator and are refreshed programming module.
Wherein said erase command receiver module, for receiving erase command; Then start the pre-programmed module storage area that needs erasing flash memory is carried out to pre-programmed, all storage unit in this zone all are written as to 0.
Then, piece is wiped module the storage area that needs erasing flash memory is wiped, and just all storage unit in this zone all are written as 1.
Then random number generator generates the address of the storage unit that need to be refreshed programming at random, by refreshing programming module, programming is refreshed in the address of the storage unit that generated by random number generator.
By method and apparatus of the present invention, the establishment address of refreshing programming that chip is done in each erase operation is all random, angle from probability, this address will mean allocation in the affected address space of chip, thereby need not all to the unit of all being crosstalked, do and refresh programming at every turn, greatly save programming time, thereby saved the time of erase operation, improved the performance of chip.
Although describe in detail about example embodiment and advantage thereof, be to be understood that and can carry out various variations, substitutions and modifications to these embodiment in the situation that do not break away from the protection domain that spirit of the present invention and claims limit.Embodiment in the present invention is exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
Claims (4)
1. a method that reduces the chip erase time, the method comprises the following steps:
A) storage area that needs erasing flash memory is carried out to pre-programmed, all storage unit in this zone all are written as to 0;
B) storage area that needs erasing flash memory is wiped, just all storage unit in this zone all are written as 1;
C) remaining element in flash memory is refreshed to programming;
It is characterized in that, describedly refresh programming and only carry out for partial memory cell, the address of this storage unit is produced at random by tandom number generator.
2. the method for reduction chip erase time according to claim 1, it is characterized in that, the production method of described random address is: after chip power, number generator produces one group of random data, after the chip pre-programmed finishes, the random number of generation is loaded in address latch, and the establishment address of programming is refreshed in this address after programming as chip erase.
3. the method for reduction chip erase time according to claim 1, is characterized in that, refreshes and finish the rear look-at-me that produces, and the random address produced in this erase process was lost efficacy.
4. a device that reduces the chip erase time, this device comprises:
The erase command receiver module, for receiving erase command;
The pre-programmed module, carry out pre-programmed for the storage area to needing erasing flash memory, and all storage unit in this zone all are written as to 0;
Piece is wiped module, for the storage area to needing erasing flash memory, is wiped, and just all storage unit in this zone all are written as 1;
Random number generator, need to be refreshed the address of the storage unit of programming for random generation;
Refresh programming module, for the address of the storage unit to being generated by random number generator, refreshed programming.
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| CN2013103401199A CN103426475A (en) | 2013-08-06 | 2013-08-06 | Method and device for reducing chip block erasing time |
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| CN2013103401199A CN103426475A (en) | 2013-08-06 | 2013-08-06 | Method and device for reducing chip block erasing time |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104751880A (en) * | 2013-12-25 | 2015-07-01 | 华邦电子股份有限公司 | Method for scrubbing parts of nonvolatile storage |
| CN111785315A (en) * | 2020-06-29 | 2020-10-16 | 深圳市芯天下技术有限公司 | Method, system, storage medium and terminal for reducing erasing interference and erasing time |
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| CN1319234A (en) * | 1998-09-17 | 2001-10-24 | 阿特梅尔股份有限公司 | Flash memory array with internal refresh |
| CN101552037A (en) * | 2009-02-11 | 2009-10-07 | 北京芯技佳易微电子科技有限公司 | Method and device for erasing nonvolatile memory |
| US7808834B1 (en) * | 2007-04-13 | 2010-10-05 | Marvell International Ltd. | Incremental memory refresh |
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2013
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5625791A (en) * | 1992-12-31 | 1997-04-29 | Gemplus Card International | Chip card with data and programs protected against ageing |
| CN1319234A (en) * | 1998-09-17 | 2001-10-24 | 阿特梅尔股份有限公司 | Flash memory array with internal refresh |
| US7808834B1 (en) * | 2007-04-13 | 2010-10-05 | Marvell International Ltd. | Incremental memory refresh |
| CN101552037A (en) * | 2009-02-11 | 2009-10-07 | 北京芯技佳易微电子科技有限公司 | Method and device for erasing nonvolatile memory |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104751880A (en) * | 2013-12-25 | 2015-07-01 | 华邦电子股份有限公司 | Method for scrubbing parts of nonvolatile storage |
| CN104751880B (en) * | 2013-12-25 | 2018-09-07 | 华邦电子股份有限公司 | Nonvolatile memory part part scrubbing method |
| CN111785315A (en) * | 2020-06-29 | 2020-10-16 | 深圳市芯天下技术有限公司 | Method, system, storage medium and terminal for reducing erasing interference and erasing time |
| CN111785315B (en) * | 2020-06-29 | 2021-03-23 | 深圳市芯天下技术有限公司 | Method, system, storage medium and terminal for reducing erasing interference and erasing time |
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Application publication date: 20131204 |