CN102077180B - Memory module and auxiliary module for memory - Google Patents
Memory module and auxiliary module for memory Download PDFInfo
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Abstract
The invention provides a memory mould and an auxiliary moulde for memory. In a memory module, even if the bit count of a bank address, the bit count of a row address, and the bit count of a column address that are output from a memory controller do not respectively match the bit count of a bank address, the bit count of a row address, and the bit count of a column address that are for identifying a memory cell subject to access, all of the memory cells of the memory module are made accessible and the memory module is allowed to operate normally. A memory module (100) comprises an SDRAM (110) and an address-generating circuit (120). Using the highest ranking bit of a row address output from a memory controller (12), the address-generating circuit (120) generates a bank address (BA2) for the missing highest ranking bit required for identifying the memory cell subject to access and outputs the generated bank address (BA2) to the SDRAM (110).
Description
Technical field
The present invention relates to a kind of memory module and storer supplementary module.
Background technology
In the past, following memory module was being popularized: a plurality of semiconductor memory chips row wiring of going forward side by side is installed on substrate, is provided with and is used for and the computing machine connection terminals.Has SDRAM (Synchronous Dynamic Random Access Memory: synchronous DRAM) at the storer that memory module possessed.In this SDRAM, inside is split into a plurality of memory banks, and each memory bank can move respectively independently.In this SDRAM, determine to become the memory cell of access object by bank-address, row address, column address.When accessing memory cells, the Memory Controller that computing machine possessed is exported these bank-address, row address and column address.In addition, the signal wire that uses bank-address to use is input to SDRAM with bank-address, uses shared signal wire that row address and column address are input to SDRAM.In addition, row address and column address are divided into twice according to the order of row address, column address and are imported into SDRAM.
In addition, be accompanied by the high capacity of the storer in the memory module, the quantity of memory cell increases.Therefore, the required bit number of required bit number, the expression column address of the required bit number of the expression bank-address of using in order to determine to become the memory cell of access object, expression row address changes according to the capacity of the storer in the memory module.For example, if the memory bank number becomes twice, then the bit number of bank-address increases by 1 bit.Therefore, under the memory module that will possess jumbo storer and situation that computing machine is connected, if the Memory Controller that this computing machine possessed is not supported the capacity of this memory module, then this computing machine can only be visited the memory cell of the part of this memory module.Promptly, under the unmatched situation of bit number of the bit number of each address that Memory Controller is exported and each address of using in order to determine to become the memory cell of access object, there are the following problems: the memory cell of the part that computing machine (Memory Controller) can only access storage module.
Therefore, a kind of technical scheme is proposed, under the situation that even this technology is not the bit number in the bit number of each address that Memory Controller is exported and each address of using in order to determine to become the memory cell of access object mates respectively, all memory cells that also can access storage module.
Patent documentation 1: TOHKEMY 2005-62914 communique
Patent documentation 2: TOHKEMY 2004-94785 communique
Summary of the invention
The problem that invention will solve
But,, also have the situation that memory module is normally moved even utilize above-mentioned conventional art.
The present invention finishes in order to address the above problem, its purpose is, even be not under the situation that the bit number from the bit number of the bit number of the bit number of the bit number of the bit number of the bank-address of Memory Controller output, row address and column address and the bank-address of using in order to determine to become the memory cell of access object, row address and column address mates respectively, all memory cells that also can access storage module, and memory module is normally moved.
In addition, the disclosure of TOHKEMY 2005-62914 communique and TOHKEMY 2004-94785 communique and be incorporated into the explanation of this book in order to reference in patented claim 2008-261516 number of Patent Office of Japan application and patented claim 2008-174799 number disclosure by Buffalo Co., Ltd..
The scheme that is used to deal with problems
The present invention can realize that following mode or application examples solve at least a portion in the problems referred to above.
[application examples 1] a kind of memory module possesses:
Storer, it has a plurality of memory banks, above-mentioned a plurality of memory bank possesses a plurality of memory cells of rectangular arrangement respectively, and above-mentioned storer determines to become the memory cell of access object according to the column address of the bit number of the row address of the bit number of the bank-address of the bit number of the regulation of being imported, regulation, regulation; And
Address generating circuit, the bank-address that it is exported respectively from Memory Controller at (i), row address, the summation of each bit number of column address with in order to determine the above-mentioned bank-address that becomes the memory cell of access object and use respectively, row address, the summation of each bit number of column address equates, and, (ii) from the bit number of the row address of above-mentioned Memory Controller output than Duo 1 bit for the bit number of definite above-mentioned row address that becomes the memory cell of access object and use, and, (iii) when the bit number of the bank-address of above-mentioned Memory Controller output lacks 1 bit than the bit number for definite above-mentioned bank-address that becomes the memory cell of access object and use, use generates for determining the above-mentioned upper bit that becomes the bank-address that is lacked the memory cell of access object from the upper bit of the row address of above-mentioned Memory Controller output, and the upper bit of this bank-address that will generate outputs to above-mentioned storer.
The memory module of application examples 1 can utilize address generating circuit to generate the upper bit of the bank-address that is lacked when following situation for determining to become the memory cell of access object, the bank-address of this generation is outputed to storer, this situation is: (i) bank-address of exporting respectively from Memory Controller, row address, the summation of each bit number of column address and the bank-address of using respectively in order to determine to become the memory cell of access object, row address, the summation of each bit number of column address equates, and, (ii) Duo 1 bit than the row address bits number that uses in order to determine to become the memory cell of access object from the bit number of the row address of Memory Controller output, and, (iii) lack 1 bit than the bit number of the bank-address of using in order to determine to become the memory cell of access object from the bit number of the bank-address of Memory Controller output.Therefore, even be not under the situation that the bit number from the bit number of each address of Memory Controller output and each address of using in order to determine to become the memory cell of access object mates respectively, under these conditions also can be from all memory cells of Memory Controller access storage module, and memory module is normally moved.
[application examples 2] is characterized in that according to application examples 1 described memory module,
Above-mentioned address generating circuit possesses:
Register, its interim storage is from the upper bit of the row address of above-mentioned Memory Controller output;
The output selection portion, it will be from the upper bit of the upper bit of the row address of above-mentioned Memory Controller output or the row address that above-mentioned register is stored as above-mentionedly becoming the upper bit of the bank-address that is lacked the memory cell of access object and output to above-mentioned storer for determining; And
Order analysis portion, it is according to rwo address strobe signals, the column address gating signal exported from above-mentioned Memory Controller and write enable signal, analyze being used to specify at the order of the access method of above-mentioned storer, this order after analyzing is outputed to above-mentioned register and above-mentioned output selection portion
Wherein, above-mentioned register root comes the upper bit of above line address is stored and reset according to the order from the input of mentioned order analysis portion,
The upper bit of the row address of being stored is exported in the order that above-mentioned output selection portion basis is imported from the mentioned order analysis portion from the upper bit of the row address of above-mentioned Memory Controller output or above-mentioned register.
[application examples 3] a kind of memory module possesses:
Storer, it has a plurality of memory banks, above-mentioned a plurality of memory bank possesses a plurality of memory cells of rectangular arrangement respectively, and above-mentioned storer determines to become the memory cell of access object according to the column address of the bit number of the row address of the bit number of the bank-address of the bit number of the regulation of being imported, regulation, regulation; And
Address generating circuit, the bank-address that it is exported respectively from Memory Controller at (i), row address, the summation of each bit number of column address with in order to determine the above-mentioned bank-address that becomes the memory cell of access object and use respectively, row address, the summation of each bit number of column address equates, and, (ii) from the bit number of the row address of above-mentioned Memory Controller output than Duo 1 bit for the bit number of definite above-mentioned row address that becomes the memory cell of access object and use, and, (iii) when the bit number of the column address of above-mentioned Memory Controller output lacks 1 bit than the bit number for definite above-mentioned column address that becomes the memory cell of access object and use, use generates for determining the above-mentioned upper bit that becomes the column address that is lacked the memory cell of access object from the upper bit of the row address of above-mentioned Memory Controller output, and the upper bit of this column address that will generate outputs to above-mentioned storer.
The memory module of application examples 3 is when following situation, can utilize address generating circuit to generate the column address upper bit that for determining to become the memory cell of access object, is lacked, the column address of this generation is outputed to storer: (i) bank-address of exporting respectively from Memory Controller, row address, the summation of each bit number of column address with divide other bank-address in order to determine to become the memory cell of access object, row address, the summation of each bit number of column address equates, and, (ii) Duo 1 bit than the row address bits number that uses in order to determine to become the memory cell of access object from the bit number of the row address of Memory Controller output, and (iii) the bit number from the column address of Memory Controller output lacks 1 bit than the column address bit number that uses in order to determine to become the memory cell of access object.Therefore, even be not under the situation that the bit number from the bit number of each address of Memory Controller output and each address of using in order to determine to become the memory cell of access object mates respectively, under these conditions also can be from all memory cells of Memory Controller access storage module, and memory module is normally moved.
[application examples 4] is characterized in that according to application examples 3 described memory modules,
Above-mentioned address generating circuit possesses:
Register, its interim storage is from the upper bit of the row address of above-mentioned Memory Controller output;
The output selection portion, it will be from the upper bit of the upper bit of the row address of above-mentioned Memory Controller output or the row address that above-mentioned register is stored as above-mentionedly becoming the upper bit of the column address that is lacked the memory cell of access object and output to above-mentioned storer for determining; And
Order analysis portion, it is according to rwo address strobe signals, the column address gating signal exported from above-mentioned Memory Controller and write enable signal, analyze being used to specify at the order of the access method of above-mentioned storer, this order after analyzing is outputed to above-mentioned register and above-mentioned output selection portion
Above-mentioned register root comes the upper bit of above line address is stored and reset according to the order from the input of mentioned order analysis portion,
The upper bit of the row address of being stored is exported in the order that above-mentioned output selection portion basis is imported from the mentioned order analysis portion from the upper bit of the row address of above-mentioned Memory Controller output or above-mentioned register.
[application examples 5] is characterized in that according to application examples 2 or 4 described memory modules,
Above-mentioned register is determined from the order of mentioned order analysis portion input at the negative edge of the chip selection signal of exporting from above-mentioned Memory Controller.
In the memory module of application examples 5, be imported into register from the chip selection signal of Memory Controller output, register is determined from the order of order analysis portion input at the negative edge of this chip selection signal, therefore, with clock signal rising edge determine that the situation of order compares, can more early moment to storing from the upper bit of the row address of Memory Controller output and resetting.
[application examples 6] is characterized in that according to application examples 2 or 4 described memory modules,
Above-mentioned register is being determined from the order of mentioned order analysis portion input from the rising edge of clock signal of above-mentioned Memory Controller output.
Memory module according to above-mentioned application examples 5, register is determined from the order of order analysis portion input at the negative edge of the chip selection signal of exporting from Memory Controller, therefore, with clock signal rising edge determine that the situation of order compares, can more early moment to storing from the upper bit of the row address of Memory Controller output and resetting.But under situation about changing more quickly than chip selection signal from the order of order analysis portion input, the situation of all orders can appear determining in register.
In the memory module of application examples 6, be imported into register from the clock signal of Memory Controller output, register is determined from the order of order analysis portion input in this rising edge of clock signal, therefore, can under situation about changing more quickly than chip selection signal, determine all orders from the order of order analysis portion input.
[application examples 7] is characterized in that according to application examples 2 or 4 described memory modules, and the mentioned order analysis portion is carried out the analysis of mentioned order at the negative edge of the chip selection signal of exporting from above-mentioned Memory Controller.
In the memory module of application examples 7, be imported into order analysis portion from the chip selection signal of Memory Controller output, order analysis portion can carry out the analysis of order at the negative edge of this chip selection signal and determine order, therefore, compare with the situation of carrying out the analysis of order in rising edge of clock signal, can determine order in the moment more early, and the order after will determining outputs to register and output selection portion.And register and output selection portion can be moved according to the order after determining.
[application examples 8] is according to each the described memory module in the application examples 1 to 7, it is characterized in that, also possesses switch, this switch is used for when following situation cutting off the output from above-mentioned address generating circuit, and this situation is: each bit number of the bank-address of exporting respectively from above-mentioned Memory Controller, row address, column address equates with each bit number of the bank-address of using respectively for the memory cell that is specified to above-mentioned access object respectively, row address, column address.
In the memory module of application examples 8, by switching above-mentioned switch, when mating respectively, the bit number from the bit number of each address of Memory Controller output and each address of using in order to determine to become the memory cell of access object cuts off output from address generating circuit, when not matching, can output to storer by the address that address generating circuit generates.
[application examples 9] a kind of storer supplementary module, this storer supplementary module and memory module, Memory Controller is connected, relaying is carried out in exchange to signal between above-mentioned Memory Controller and the above-mentioned memory module and data, this memory module possesses storer, this storer has a plurality of memory banks, above-mentioned a plurality of memory bank possesses a plurality of memory cells of rectangular arrangement respectively, above-mentioned storer is according to the bank-address of the bit number of the regulation of being imported, the column address of the row address of the bit number of regulation and the bit number of regulation determines to become the memory cell of access object, this storer is used when the following situation with supplementary module: (i) bank-address of exporting respectively from above-mentioned Memory Controller, row address, the summation of each bit number of column address with in order to determine the above-mentioned bank-address that becomes the memory cell of access object and use respectively, row address, the summation of each bit number of column address equates, and, (ii) from the bit number of the row address of above-mentioned Memory Controller output than Duo 1 bit for the bit number of definite above-mentioned row address that becomes the memory cell of access object and use, and, (iii) the bit number from the bank-address of above-mentioned Memory Controller output lacks 1 bit than the bit number for definite above-mentioned bank-address that becomes the memory cell of access object and use
This storer possesses address generating circuit with supplementary module, this address generating circuit uses from the upper bit of the row address of above-mentioned Memory Controller output and generates for determining the above-mentioned upper bit that becomes the bank-address that is lacked the memory cell of access object, and the upper bit of this bank-address of generating is outputed to above-mentioned storer.
Use in the supplementary module at the storer of application examples 9, when following situation, can utilize address generating circuit to generate the upper bit of the bank-address that for determining to become the memory cell of access object, is lacked, the bank-address of this generation is outputed to memory module, this situation is: (i) bank-address of exporting respectively from Memory Controller, row address, the summation of each bit number of column address and the bank-address of using respectively in order to determine to become the memory cell of access object, row address, the summation of each bit number of column address equates, and, (ii) Duo 1 bit than the bit number of the row address that uses in order to determine to become the memory cell of access object from the bit number of the row address of Memory Controller output, and, (iii) lack 1 bit than the bit number of the bank-address of using in order to determine to become the memory cell of access object from the bit number of the bank-address of Memory Controller output.Therefore, even be not under the situation that the bit number from the bit number of each address of Memory Controller output and each address of using in order to determine to become the memory cell of access object mates respectively, under these conditions also can be from all memory cells of Memory Controller access storage module, and memory module is normally moved.In addition, various add ons are shown before also can similarly using with the address generating circuit in the supplementary module the storer of application examples 9 with the address generating circuit in the memory module of application examples 1.
[application examples 10] a kind of storer supplementary module, this storer supplementary module and memory module, Memory Controller is connected, relaying is carried out in exchange to signal between above-mentioned Memory Controller and the above-mentioned memory module and data, this memory module possesses storer, this storer has a plurality of memory banks, above-mentioned a plurality of memory bank possesses a plurality of memory cells of rectangular arrangement respectively, above-mentioned storer is according to the bank-address of the bit number of the regulation of being imported, the column address of the row address of the bit number of regulation and the bit number of regulation determines to become the memory cell of access object, this storer is used when the following situation with supplementary module: (i) bank-address of exporting respectively from above-mentioned Memory Controller, row address, the summation of each bit number of column address with in order to determine the above-mentioned bank-address that becomes the memory cell of access object and use respectively, row address, the summation of each bit number of column address equates, and, (ii) from the bit number of the row address of above-mentioned Memory Controller output than Duo 1 bit for the bit number of definite above-mentioned row address that becomes the memory cell of access object and use, and, (iii) the bit number from the column address of above-mentioned Memory Controller output lacks 1 bit than the bit number for definite above-mentioned column address that becomes the memory cell of access object and use
This storer possesses address generating circuit with supplementary module, this address generating circuit uses the upper bit that generates the column address that is lacked from the upper bit of the row address of above-mentioned Memory Controller output for determining to become the memory cell of above-mentioned access object, and the upper bit of this column address of generating is outputed to above-mentioned storer.
Use in the supplementary module at the storer of application examples 10, when following situation, can utilize address generating circuit to generate the upper bit of the column address that for determining to become the memory cell of access object, is lacked, the column address of this generation is outputed to memory module, this situation is: (i) bank-address of exporting respectively from Memory Controller, row address, the summation of each bit number of column address and the bank-address of using respectively in order to determine to become the memory cell of access object, row address, the summation of each bit number of column address equates, and, (ii) Duo 1 bit than the row address bits number that uses in order to determine to become the memory cell of access object from the bit number of the row address of Memory Controller output, and, (iii) lack 1 bit than the bit number of the column address of using in order to determine to become the memory cell of access object from the bit number of the column address of Memory Controller output.Therefore, even be not under the situation that the bit number from the bit number of each address of Memory Controller output and each address of using in order to determine to become the memory cell of access object mates respectively, under these conditions also can be from all memory cells of Memory Controller access storage module, and memory module is normally moved.In addition, the various add ons that illustrate before also can similarly using with the address generating circuit in the supplementary module the storer of application examples 10 with the address generating circuit in the memory module of application examples 3.
The part that the present invention can suitably make up above-mentioned each feature constitutes.For example, constitute the memory module of the address generating circuit both sides in the memory module of address generating circuit in the memory module possess application examples 1 and application examples 3, also can suitably optionally use both.
Below, with reference to accompanying drawing, describe the preferred embodiment of the application's invention in detail, the above-mentioned purpose of understanding the application's invention and other purposes, structure, effect.
Description of drawings
Fig. 1 is the key diagram of expression as the summary structure of the memory module 100 of the first embodiment of the present invention.
Fig. 2 is the key diagram of expression as the summary structure of the memory module 100 of the first embodiment of the present invention.
Fig. 3 is the expression 512Mbit (key diagram of the bank structure of the DDR2SDRAM of 64Mword * 8bit).
Fig. 4 is the expression 1Gbit (key diagram of the bank structure of the DDR2SDRAM (SDRAM 110) of 64Mword * 16bit).
Fig. 5 is the process flow diagram of the initialization routine in the expression memory module 100.
Fig. 6 is the process flow diagram of an example of the common action routine in the expression memory module 100.
Fig. 7 is the summary structure of supplementary module 200 is used in expression as the storer of the second embodiment of the present invention a key diagram.
Fig. 8 is the key diagram of expression as the summary structure of the memory module 100B of first variation.
Fig. 9 is the key diagram of expression as the summary structure of the memory module 100C of second variation.
Figure 10 is the key diagram of the effect of expression memory module 100C.
Embodiment
Below, based on embodiment embodiments of the present invention are described.
A. first embodiment:
Fig. 1 and Fig. 2 are the key diagram of expression as the summary structure of the memory module 100 of the first embodiment of the present invention.State when memory module 100 is connected with Memory Controller 10 has been shown among Fig. 1.State when in addition, figure 2 illustrates memory module 100 and be connected with Memory Controller 12.Their difference of back explanation.
As shown in the figure, this memory module 100 possesses SDRAM 110 and address generating circuit 120.In the present embodiment, ((Double Data Rate 2: double data stream 2) SDRAM is as SDRAM 110 for the DDR2 of 64Mword * 16bit) to use 1Gbit.As described later, the inside of this SDRAM 110 is split into eight memory banks, and each memory bank can move respectively independently.And, (the row address of BA0～BA2), the 13 bits (column address (A0～A9), determine to become the memory cell of access object according to these addresses of A0～A12), 10 bits of the bank-address of input 3 bits in SDRAM 110.Row address and column address are used shared signal wire to be divided into twice according to the order of row address, column address and are imported into SDRAM 100.Therefore, in this manual, (for example (for example A0～A9) has added identical " A " to row address on the first place of Reference numeral for A0～A12) and column address.
In addition, among the SDRAM 110 except input has above-mentioned each address, also input chip selection signal (CS), rwo address strobe signals (RAS), column address gating signal (CAS) arranged, write enable signal (WE), not shown clock signal, employed various signals in the action of the SDRAM 110 of clock enable signal etc.In addition, memory module 100 also possesses not shown the data input and output pin and the wiring of the input and output that are used for carrying out data between Memory Controller and SDRAM 110.
As depicted in figs. 1 and 2, the memory module 100 of present embodiment can be connected with Memory Controller 10 or Memory Controller 12.
Memory Controller shown in Figure 1 10 is supported the 1Gbit (DDR2SDRAM (SDRAM 110) of 64Mword * 16bit), as shown in Figure 1, export the bank-address (row address of BA0～BA2), the 13 bits (column address of A0～A12), 10 bits (A0～A9) etc. of 3 bits.Promptly, from the bit number of each address that Memory Controller 10 is exported and the bit number coupling of each address of using in order to determine to become the memory cell of access object.
On the other hand, the inside of Memory Controller 12 shown in Figure 2 is split into four memory banks, support the 512Mbit (DDR2SDRAM of 64Mword * 8bit), as shown in Figure 2, export the bank-address (BA0, BA1) of 2 bits, the row address of the 14 bits (column address of A0～A13), 10 bits (A0～A9) etc.Promptly, do not match from the bit number of each address of Memory Controller 12 output bit number with each address of using in order to determine to become the memory cell of access object.Wherein, the summation from the bit number of each address of Memory Controller 12 output equates with the summation of the bit number of each address of using in order to determine to become the memory cell of access object among SDRAM 100.In addition, Duo 1 bit from the bit number (14 bit) of the row address of Memory Controller 12 output than the bit number (13 bit) of the row address that uses in order to determine to become the memory cell of access object.Lack 1 bit from the bit number (2 bit) of the bank-address of Memory Controller 12 output than the bit number (3 bit) of the bank-address of using in order to determine to become the memory cell of access object.When memory module 100 was connected with Memory Controller 12, the address generating circuit 120 that memory module 100 is possessed was used to eliminate not matching from the bit number of each addresses of Memory Controller 12 outputs and each address that is imported into SDRAM 110.
As depicted in figs. 1 and 2, address generating circuit 120 possesses register 122, output selection portion 124, switch 126 and order analysis portion 128.In addition, according to user's operation, switch 126 is switched to conducting/shutoff.Specifically, as shown in Figure 1, when the user is connected memory module 100 with Memory Controller 10, according to user's operation and switch 126 is set as shutoff.Consequently, be cut off from the output of address generating circuit 120 to SDRAM 110.In addition, as shown in Figure 2, when the user is connected memory module 100 with Memory Controller 12, according to user's operation and switch 126 is set as conducting.Consequently, can export to SDRAM110 from address generating circuit 120.
In addition, as mentioned above, when memory module 100 was connected with Memory Controller 10, switch 126 was set as shutoff (with reference to Fig. 1).And when memory module 100 was connected with Memory Controller 12, switch 126 was set as conducting (with reference to Fig. 2).Therefore, only when memory module 100 was connected with Memory Controller 12, the upper bit of row address was output to SDRAM 110 as the upper bit (BA2) of bank-address.
Fig. 3 is the expression 512Mbit (key diagram of the bank structure of the DDR2SDRAM of 64Mword * 8bit).SDRAM shown in Figure 3 is the SDRAM of the structure that employed SDRAM 110 is different in the explanation that has with Fig. 1 and Fig. 2, and is the SDRAM that Memory Controller 12 (Fig. 2) is supported.As shown in the figure, the inside of SDRAM is split into four memory banks (Bank0～Bank3).In addition, each memory bank possesses not shown row decoder, column decoder, detecting amplifier etc. so that each memory bank can move respectively.And, Memory Controller 12 determines to have the memory bank of the memory cell that becomes access object from four memory banks according to bank-address BA0, the BA1 of 2 bits, and, according to row address (A0～A13) and the column address (memory cell (with reference to Fig. 2) in the memory bank that A0～A9) has determined to be determined.
Fig. 4 is the expression 1Gbit (key diagram of the bank structure of the DDR2SDRAM of 64Mword * 16bit).SDRAM shown in Figure 4 is employed SDRAM 110 in the explanation of Fig. 1 and Fig. 2, and is the SDRAM that Memory Controller 10 (Fig. 1) is supported.As shown in the figure, 110 of SDRAM inside is split into eight memory banks (Bank0～Bank7).In addition, each memory bank possesses not shown row decoder, column decoder, detecting amplifier etc. so that each memory bank can move respectively independently.
SDRAM shown in Figure 4 110 directly is connected with Memory Controller 12, promptly not by address generating circuit 120 with situation that Memory Controller 12 is connected under, as previously described above, bit number (bank-address: 2 bits from each address that Memory Controller 12 is exported, row address: 14 bits, column address: 10 bits) with the bit number (bank-address: 3 bits of each address of using in order to determine to become the memory cell of access object, row address: 13 bits, column address: 10 bits) do not match.Therefore, Memory Controller 12 can't make SDRAM 110 normally move.
The memory module 100 of present embodiment except possess 1Gbit shown in Figure 4 (the DDR2SDRAM of 64Mword * 16bit), illustrated address generating circuit 120 (seeing figures.1.and.2) before also possessing.Therefore, Memory Controller 12 is identical when being connected with memory module, the SDRAM 110 (with reference to Fig. 2) that can access storage module 100 be possessed, this memory module possess as shown in Figure 3, inside be split into four memory banks, the 512Mbit (DDR2SDRAM of 64Mword * 8bit).
Promptly, in the present embodiment, the Memory Controller 12 of bank-address of exporting 2 bits is by address generating circuit 120, can will be handled as a memory bank by the Bank0 of the inside of SDRAM 110 and the piece that Bank4 constitutes.Equally, the piece that is made of Bank1 and Bank5 can be handled as a memory bank.The piece that is made of Bank2 and Bank6 can be handled as a memory bank.The piece that is made of Bank3 and Bank7 can be handled as a memory bank.Consequently, Memory Controller 12 can be with eight memory banks (Bank0～Bank7) handle as four memory banks of SDRAM 110.
For example, be respectively under the situation of BA0=0, BA1=0 at bank-address BA0, BA1 from Memory Controller 12 outputs, Memory Controller 12 will be handled as a memory bank by the piece that Bank0 and Bank4 constitute.On the other hand, in SDRAM 110, determine piece according to bank-address B0, B1 from Memory Controller 12 outputs, and, according to determining some memory banks that piece is interior from the bank-address BA2 of address generating circuit 120 (output selection portion 124) output (from the upper bit A 13 of the row address of Memory Controller 12 outputs).
Fig. 5 is the process flow diagram of the initialization routine in the expression memory module 100.Carry out this initialization routine during each memory module 100 energized.At this, the initialization routine of (with reference to Fig. 2) described when memory module 100 was connected in Memory Controller 12.
At first, when sending " all memory bank precharge " order from Memory Controller 12, SDRAM 110 carries out the precharge (step S100) of whole memory banks.At this moment, to be reset be zero to the value of the register 122 (with reference to Fig. 2) that possessed of address generating circuit 120.Next, when sending " refreshing " order from Memory Controller 12, SDRAM 110 carries out refresh activity (step S110).Next, when sending " mode register setting " order from Memory Controller 12, SDRAM 110 bit arrangement according to the address of being imported come pattern is switched (step S120).At this moment, the output selection portion 124 (with reference to Fig. 2) that possessed of address generating circuit 120 outputs to SDRAM 110 with the value (zero) of register 122 as BA2.By above action, initialization routine finishes, and SDRAM 110 is an idle condition.
Fig. 6 is the process flow diagram of an example of the common action routine in the expression memory module 100.After finishing, carries out above-mentioned initialization routine action routine usually.At this, the common action routine when memory module 100 is connected in Memory Controller 12 describes.
At first, when sending from Memory Controller 12 " activation " when order, activate SDRAM 110 (step S200) according to the bank-address BA2 of output selection portion 124 outputs that possessed from bank-address BA0, the BA1 of Memory Controller 12 outputs, row address A0～A12 and from address generating circuit 120 (from the upper bit A 13 of the row address of Memory Controller 12 outputs) (with reference to Fig. 2).At this moment, 122 pairs of upper bit A 13 from the row address of Memory Controller 12 outputs of the register that possessed of address generating circuit 120 are stored.
Next, when sending " reading " order or " writing " order from Memory Controller 12, SDRAM 110 reads from the data of the memory cell that is confirmed as access object or to the memory cell that is confirmed as access object and writes data (step S210).Read from the data of this memory cell or to write data to memory cell be to carry out in the following way: determine memory cell as access object according to the bank-address BA2 (the upper bit A 13 of the row address of being stored the register 122) of output selection portion 124 outputs that possessed from bank-address BA0, the BA1 of Memory Controller 12 outputs, column address A0～A9 and from address generating circuit 120.
Next, when sending " precharge of designated store body " order from Memory Controller 12 (step S220: be), SDRAM 110 carries out the precharge (step S230) of appointed memory bank.The precharge of memory bank is carried out in the following way: according to determining memory bank from bank-address BA0, the BA1 of Memory Controller 12 outputs and the bank-address BA2 (the upper bit A 13 of the row address of being stored the register 122) that exports from the output selection portion 124 that address generating circuit 120 is possessed.In addition, when sending " all memory bank precharge " order from Memory Controller 12 (step S220: be), SDRAM 110 carries out the precharge (step S230) of whole memory banks.At this moment, to be reset be zero to the value of the register 122 that possessed of address generating circuit 120.When the release of step S230, SDRAM 110 is an idle condition.
On the other hand, then after the step S210, (step S220: deny) returns step S210 under the situation of sending " reading " order or " writing " order from Memory Controller 12.
Memory module 100 according to first embodiment discussed above, (i) from the bit number (2 bit) of the bank-address of Memory Controller 12 output, the bit number of row address (14 bit), the bit number (3 bit) of the summation (26 bit) of the bit number of column address (10 bit) and the bank-address of using in order to determine to become the memory cell of access object, the bit number of row address (13 bit), the summation (26 bit) of the bit number of column address (10 bit) equates, and, (ii) Duo 1 bit than the bit number (13 bit) of the row address that uses in order to determine to become the memory cell of access object from the bit number (14 bit) of the row address of Memory Controller 12 output, and, (iii) to lack 1 bit than the bit number (3 bit) of the bank-address of using in order determining to become the memory cell of access object, when above situation, to carry out following processing from the bit number (2 bit) of the bank-address of Memory Controller 12 output.Promptly, can utilize address generating circuit 120 to generate the bank-address BA2 of the upper bit that for determining to become the memory cell of access object, is lacked, the bank-address BA2 of this generation is outputed to SDRAM 110.Therefore, even be not from the bit number of each address of Memory Controller output with for the memory cell of determining to become access object and use under the situation that the bit number of each address mates respectively, under these conditions also can be from all memory cells of Memory Controller access storage module 100, and memory module 100 is normally moved.
B. second embodiment:
Fig. 7 is the summary structure of supplementary module 200 is used in expression as the storer of the second embodiment of the present invention a key diagram.
This storer is to use under the situation that the SDRAM 110 that the user wants to utilize the Memory Controller 12 of not supporting SDRAM 110 that memory module 100A is possessed moves with supplementary module 200.As shown in Figure 7, storer is connected with memory module 100A with Memory Controller 12 with supplementary module 200, and relaying is carried out in the exchange of signal between Memory Controller 12 and the memory module 100A and data.And, memory module 100A be remove address generating circuit 120 the memory module 100 (with reference to Fig. 1, Fig. 2) from first embodiment and memory module.Other parts of memory module 100A are identical with the memory module 100 of first embodiment.
Storer is the adapters that possess the address generating circuit 120 in the memory module 100 of first embodiment with supplementary module 200.And storer is the modules that connected when utilizing Memory Controller 12 that memory module 100A is moved with supplementary module 200.Therefore, the address generating circuit 120 that possessed with supplementary module 200 of storer does not possess the switch 126 (with reference to Fig. 1, Fig. 2) in the address generating circuit 120 that the memory module 100 of first embodiment possessed.Storer is identical with the address generating circuit 120 that the memory module 100 of first embodiment is possessed with other parts of the address generating circuit 120 that supplementary module 200 is possessed.
In addition, in a second embodiment, the action of the SDRAM 110 that possessed of the action of the address generating circuit 120 that possessed with supplementary module 200 of the SDRAM110 that possessed of memory module 100A and storer and the memory module 100 of first embodiment and address generating circuit 120 is identical.Therefore, in the present embodiment, omit explanation to these actions.
Storer supplementary module 200 according to second embodiment discussed above, under following situation, can utilize address generating circuit 120 to generate the bank-address BA2 of the upper bit that for determining to become the memory cell of access object, is lacked, and the bank-address BA2 that is generated is outputed to memory module 100A.This following situation is meant meet the following conditions (i), (ii) and situation (iii).(i) from the summation (26 bit) of the bit number (10 bit) of the bit number (14 bit) of the bit number (2 bit) of the bank-address of Memory Controller 12 output, row address, column address with for the memory cell of determining to become access object and the summation (26 bit) of the bit number (10 bit) of the bit number (13 bit) of the bit number (3 bit) of use bank-address, row address, column address equates.(ii) Duo 1 bit than the bit number of the row address that uses in order to determine to become the memory cell of access object from the bit number of the row address of Memory Controller 12 output.(iii) lack 1 bit than the bit number of the bank-address of using in order to determine to become the memory cell of access object from the bit number of the bank-address of Memory Controller 12 output.
Storer supplementary module 200 according to second embodiment, satisfying under the situation of above-mentioned condition, can utilize address generating circuit 120 to generate the bank-address BA2 of the upper bit that for determining to become the memory cell of access object, is lacked, and the bank-address BA2 that will generate output to memory module 100A.Therefore, even be not under the situation that the bit number from the bit number of each address of Memory Controller output and each address of the memory cell that is used to determine to become access object mates respectively, under these conditions also can be from all memory cells of Memory Controller access storage module 100A, and memory module 100A is normally moved.
C. variation:
More than, several embodiments of the present invention is illustrated, still, the present invention is not limited by these embodiments, can implement in every way in the scope that does not break away from its aim.For example, can carry out following this distortion.
C1. variation 1:
Fig. 8 is the key diagram of expression as the summary structure of the memory module 100B of first variation.In the memory module 100 (with reference to Fig. 1, Fig. 2) of the first illustrated before embodiment, to the register 122 input chip selection signals (CS) that address generating circuit 120 is possessed, register 122 is determined from the order of order analysis portion 128 inputs at the negative edge of the chip selection signal of being imported (CS).Relative therewith, in the memory module 100B of present embodiment, to the 128B of the order analysis portion input chip selection signal (CS) that address generating circuit 120B is possessed.The 128B of order analysis portion carries out order analysis and order is determined at the negative edge of the chip selection signal of being imported (CS), and the order after determining is outputed to register 122B and output selection portion 124.
Other parts of the memory module 100B of variation 1 are identical with the memory module 100 of first embodiment.Memory module 100B by this variation also can access the effect identical with the memory module 100 of first embodiment.
In addition, in the memory module 100B of the memory module 100 of above-mentioned first embodiment and this variation, carry out determining of order at the negative edge of chip selection signal (CS).But the present invention is not limited to this, for example, also can substitute chip selection signal (CS) to register 122 or the 128B of order analysis portion input clock signal, carries out determining of order in the rising edge of clock signal of being imported.Wherein, register 122 or the 128B of order analysis portion carry out determining of order by the negative edge at chip selection signal (CS), with carry out order phasing ratio really in rising edge of clock signal, can determine order in the moment more early, thereby register 122,122B or output selection portion 124 are moved.
C2. variation 2:
Fig. 9 is the key diagram of expression as the summary structure of the memory module 100C of second variation.In the memory module 100 (with reference to Fig. 1, Fig. 2) of the first illustrated before embodiment, to the register 122 input chip selection signals (CS) that address generating circuit 120 is possessed, register 122 is confirmed the order of importing from order analysis portion 128 at the negative edge of the chip selection signal of being imported (CS).Relative therewith, in the memory module 100C of this variation, the register 122C input clock signal (CLK) and the chip selection signal (CS) that are possessed to address generating circuit 120C.Register 122C to determining from the order of order analysis portion 128C input, outputs to output selection portion 124 with the order of having determined at the rising edge of the clock signal of being imported (CLK).In addition, chip selection signal (CS) also can be imported into the 128C of order analysis portion and comes alternative registers 122C.
In addition, the address generating circuit 120C among the memory module 100C of this variation possesses the switch 126 (with reference to Fig. 1, Fig. 2) in the memory module 100 that switch 126C substitutes first embodiment.And.In this switch 126C, be (to support 1Gbit (64Mword * 16bit) DDR2SDRAM) to be connected or (support 512Mbit (64Mword * 8bit) DDR2SDRAM) is connected to come two-way contact with Memory Controller 12 with Memory Controller 10 according to memory module 100C.Other parts of the memory module 100C of variation 2 are identical with the memory module 100 of first embodiment.
Figure 10 is the key diagram of the effect of expression memory module 100C.(a) of Figure 10 shows the sequential chart that is imported into each signal in the register that address generating circuit possesses in the memory module 100 (with reference to Fig. 1, Fig. 2) at first embodiment.Shown in Figure 10 (a), each command address (RAS, CAS, WE) that is input in the register 122 that switches, chip selection signal (CS) also switches, in this case, utilize the memory module 100 of first embodiment, SDRAM 110 is normally moved.Promptly, in illustrated example, register 122 can moment t1 and constantly each negative edge of the chip selection signal (CS) during t2 determine " order A " and " order B " respectively.
But, negative edge at chip selection signal (CS) carries out under the situation about determining of order, shown in Figure 10 (b), between illustrated moment t1～t2, promptly, produce the order that register 122 can't be determined in illustrated example between the negative edge of chip selection signal (CS) repeatedly under the situation of (being twice) switching command address.Promptly in illustrated example, register 122 can't be determined " order B ".
Be imported into the sequential chart of each signal among the register 122C that address generating circuit possesses among the memory module 100C (with reference to Fig. 9) that (c) of Figure 10 shows in variation 2.In the memory module 100C of variation 2, register 122C determines the order of importing from order analysis portion 128C at the rising edge of clock signal (CLK).Therefore, even, also can determine each order reliably between the negative edge of chip selection signal (CS) repeatedly under the situation of switching command address.Promptly in illustrated example, each rising edge of the clock signal (CLK) when moment t1, t2, t3 can be determined " order A " " order B " " order C " respectively.
C3. variation 3:
For example, in the above-described embodiments, following mode is illustrated: (a) from the bit number of the bank-address of Memory Controller output, the bit number of row address, the summation of the bit number of column address with for the memory cell of determining to become access object and use the bit number of bank-address, the bit number of row address, the summation of the bit number of column address equates, and, (b) Duo 1 bit from the bit number of the row address of Memory Controller output than the bit number of the row address that uses in order to determine to become the memory cell of access object, and, (c) lack 1 bit than the bit number of the bank-address of using for the memory cell of determining to become access object from the bit number of the bank-address of Memory Controller output.But the present invention is not limited to this.
Though omitted diagram and detailed explanation, but, the present invention also can be applied to following situation: from the bit number of the bank-address of Memory Controller output, the bit number of row address, the bit number of the summation of the bit number of column address and the bank-address of the memory cell that uses in order to determine to become access object, the bit number of row address, the summation of the bit number of column address equates, and, Duo 1 bit from the bit number of the row address of Memory Controller output than the row address bits number that uses in order to determine to become the memory cell of access object, and, from the bit number of the column address of Memory Controller output than for the memory cell of determining to become access object and the bit number of use column address lacks 1 bit.
In this case, as long as address generating circuit can use the column address that generates the upper bit that is lacked from the upper bit of the row address of Memory Controller output for determining to become the memory cell of access object, and the upper bit of the column address that generated is outputed to SDRAM get final product.So also can access effect same as the previously described embodiments.Even promptly be not under the situation that the bit number from the bit number of each address of Memory Controller output and each address of using in order to determine to become the memory cell of access object mates respectively, under these conditions also can be from all memory cells of Memory Controller access storage module, and memory module is normally moved.
C4. variation 4:
In the memory module 100 of the foregoing description, used DDR2SDRAM as SDRAM 110, still, the present invention is not limited to this.For example, also can use other the SDRAM of DDRSDRAM, DDR3SDRAM etc. to substitute DDR2SDRAM with a plurality of memory banks.
C5. variation 5:
In addition, computer program product can accomplished in various ways.For example following mode.
Computer-readable recording medium.For example, floppy disk, CD, semiconductor storage body etc.
The computing machine that comprises computer-readable recording mediums such as disk, semiconductor memory.
By data transmission interim computing machine of preserving computer program in storer.
More than, describe the present invention in detail with reference to the preferred illustrative embodiment of the application's invention.But the application's invention is not to be defined in embodiment discussed above, structure.And the application's invention comprises various distortion or equivalent configurations.And the various key elements of invention disclosed disclose by various combinations and structure, and still, these are exemplary, and each key element can also be more or still less.And, also can be a key element.These modes are included in the application's the invention scope.
Claims (14)
1. memory module possesses:
Storer, it has a plurality of memory banks, above-mentioned a plurality of memory bank possesses a plurality of memory cells of rectangular arrangement respectively, and above-mentioned storer determines to become the memory cell of access object according to the column address of the bit number of the row address of the bit number of the bank-address of the bit number of the regulation of being imported, regulation, regulation; And
Address generating circuit, the bank-address that it is exported respectively from Memory Controller at (i), row address, the summation of each bit number of column address with in order to determine the above-mentioned bank-address that becomes the memory cell of access object and use respectively, row address, the summation of each bit number of column address equates, and, (ii) from the bit number of the row address of above-mentioned Memory Controller output than Duo 1 bit for the bit number of definite above-mentioned row address that becomes the memory cell of access object and use, and, (iii) when the bit number of the bank-address of above-mentioned Memory Controller output lacks 1 bit than the bit number for definite above-mentioned bank-address that becomes the memory cell of access object and use, use generates for determining the above-mentioned upper bit that becomes the bank-address that is lacked the memory cell of access object from the upper bit of the row address of above-mentioned Memory Controller output, and the upper bit of this bank-address that will generate outputs to above-mentioned storer.
2. memory module according to claim 1 is characterized in that,
Above-mentioned address generating circuit possesses:
Register, its interim storage is from the upper bit of the row address of above-mentioned Memory Controller output;
The output selection portion, it will be from the upper bit of the upper bit of the row address of above-mentioned Memory Controller output or the row address that above-mentioned register is stored as above-mentionedly becoming the upper bit of the bank-address that is lacked the memory cell of access object and output to above-mentioned storer for determining; And
Order analysis portion, it is according to rwo address strobe signals, the column address gating signal exported from above-mentioned Memory Controller and write enable signal, analyze being used to specify at the order of the access method of above-mentioned storer, this order after analyzing is outputed to above-mentioned register and above-mentioned output selection portion
Wherein, above-mentioned register root comes the upper bit of above line address is stored and reset according to the order from the input of mentioned order analysis portion,
The upper bit of the row address of being stored is exported in the order that above-mentioned output selection portion basis is imported from the mentioned order analysis portion from the upper bit of the row address of above-mentioned Memory Controller output or above-mentioned register.
3. memory module according to claim 2 is characterized in that,
Above-mentioned register is determined from the order of mentioned order analysis portion input at the negative edge of the chip selection signal of exporting from above-mentioned Memory Controller.
4. memory module according to claim 2 is characterized in that,
Above-mentioned register is being determined from the order of mentioned order analysis portion input from the rising edge of clock signal of above-mentioned Memory Controller output.
5. memory module according to claim 2 is characterized in that,
The mentioned order analysis portion is carried out the analysis of mentioned order at the negative edge of the chip selection signal of exporting from above-mentioned Memory Controller.
6. according to each the described memory module in the claim 1 to 5, it is characterized in that,
Also possesses switch, this switch is used for when following situation cutting off the output from above-mentioned address generating circuit, and this situation is: each bit number of the bank-address of exporting respectively from above-mentioned Memory Controller, row address, column address equates respectively with each bit number of the bank-address of using for definite above-mentioned memory cell that becomes access object, row address, column address.
7. memory module possesses:
Storer, it has a plurality of memory banks, above-mentioned a plurality of memory bank possesses a plurality of memory cells of rectangular arrangement respectively, and above-mentioned storer determines to become the memory cell of access object according to the column address of the bit number of the row address of the bit number of the bank-address of the bit number of the regulation of being imported, regulation, regulation; And
Address generating circuit, the bank-address that it is exported respectively from Memory Controller at (i), row address, the summation of each bit number of column address with in order to determine the above-mentioned bank-address that becomes the memory cell of access object and use respectively, row address, the summation of each bit number of column address equates, and, (ii) from the bit number of the row address of above-mentioned Memory Controller output than Duo 1 bit for the bit number of definite above-mentioned row address that becomes the memory cell of access object and use, and, (iii) when the bit number of the column address of above-mentioned Memory Controller output lacks 1 bit than the bit number for definite above-mentioned column address that becomes the memory cell of access object and use, use generates for determining the above-mentioned upper bit that becomes the column address that is lacked the memory cell of access object from the upper bit of the row address of above-mentioned Memory Controller output, and the upper bit of this column address that will generate outputs to above-mentioned storer.
8. memory module according to claim 7 is characterized in that,
Above-mentioned address generating circuit possesses:
Register, its interim storage is from the upper bit of the row address of above-mentioned Memory Controller output;
The output selection portion, it will be from the upper bit of the upper bit of the row address of above-mentioned Memory Controller output or the row address that above-mentioned register is stored as above-mentionedly becoming the upper bit of the column address that is lacked the memory cell of access object and output to above-mentioned storer for determining; And
Order analysis portion, it is according to rwo address strobe signals, the column address gating signal exported from above-mentioned Memory Controller and write enable signal, analyze being used to specify at the order of the access method of above-mentioned storer, this order after analyzing is outputed to above-mentioned register and above-mentioned output selection portion
Above-mentioned register root comes the upper bit of above line address is stored and reset according to the order from the input of mentioned order analysis portion,
The upper bit of the row address of being stored is exported in the order that above-mentioned output selection portion basis is imported from the mentioned order analysis portion from the upper bit of the row address of above-mentioned Memory Controller output or above-mentioned register.
9. memory module according to claim 8 is characterized in that,
Above-mentioned register is determined from the order of mentioned order analysis portion input at the negative edge of the chip selection signal of exporting from above-mentioned Memory Controller.
10. memory module according to claim 8 is characterized in that,
Above-mentioned register is being determined from the order of mentioned order analysis portion input from the rising edge of clock signal of above-mentioned Memory Controller output.
11. memory module according to claim 8 is characterized in that,
The mentioned order analysis portion is carried out the analysis of mentioned order at the negative edge of the chip selection signal of exporting from above-mentioned Memory Controller.
12. each the described memory module according in the claim 7 to 11 is characterized in that,
Also possesses switch, this switch is used for when following situation cutting off the output from above-mentioned address generating circuit, and this situation is: each bit number of the bank-address of exporting respectively from above-mentioned Memory Controller, row address, column address equates respectively with each bit number of the bank-address of using for definite above-mentioned memory cell that becomes access object, row address, column address.
13. storer supplementary module, this storer supplementary module and memory module, Memory Controller is connected, relaying is carried out in exchange to signal between above-mentioned Memory Controller and the above-mentioned memory module and data, this memory module possesses storer, this storer has a plurality of memory banks, above-mentioned a plurality of memory bank possesses a plurality of memory cells of rectangular arrangement respectively, above-mentioned storer is according to the bank-address of the bit number of the regulation of being imported, the column address of the row address of the bit number of regulation and the bit number of regulation determines to become the memory cell of access object, this storer is used when the following situation with supplementary module: (i) bank-address of exporting respectively from above-mentioned Memory Controller, row address, the summation of each bit number of column address with in order to determine the above-mentioned bank-address that becomes the memory cell of access object and use respectively, row address, the summation of each bit number of column address equates, and, (ii) from the bit number of the row address of above-mentioned Memory Controller output than Duo 1 bit for the bit number of definite above-mentioned row address that becomes the memory cell of access object and use, and, (iii) the bit number from the bank-address of above-mentioned Memory Controller output lacks 1 bit than the bit number for definite above-mentioned bank-address that becomes the memory cell of access object and use
This storer possesses address generating circuit with supplementary module, this address generating circuit uses from the upper bit of the row address of above-mentioned Memory Controller output and generates for determining the above-mentioned upper bit that becomes the bank-address that is lacked the memory cell of access object, and the upper bit of this bank-address of generating is outputed to above-mentioned storer.
14. storer supplementary module, this storer supplementary module and memory module, Memory Controller is connected, relaying is carried out in exchange to signal between above-mentioned Memory Controller and the above-mentioned memory module and data, this memory module possesses storer, this storer has a plurality of memory banks, above-mentioned a plurality of memory bank possesses a plurality of memory cells of rectangular arrangement respectively, above-mentioned storer is according to the bank-address of the bit number of the regulation of being imported, the column address of the row address of the bit number of regulation and the bit number of regulation determines to become the memory cell of access object, this storer is used when the following situation with supplementary module: (i) bank-address of exporting respectively from above-mentioned Memory Controller, row address, the summation of each bit number of column address with in order to determine the above-mentioned bank-address that becomes the memory cell of access object and use respectively, row address, the summation of each bit number of column address equates, and, (ii) from the bit number of the row address of above-mentioned Memory Controller output than Duo 1 bit for the bit number of definite above-mentioned row address that becomes the memory cell of access object and use, and, (iii) the bit number from the column address of above-mentioned Memory Controller output lacks 1 bit than the bit number for definite above-mentioned column address that becomes the memory cell of access object and use
This storer possesses address generating circuit with supplementary module, this address generating circuit uses the upper bit that generates the column address that is lacked from the upper bit of the row address of above-mentioned Memory Controller output for determining to become the memory cell of above-mentioned access object, and the upper bit of this column address of generating is outputed to above-mentioned storer.
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| JP2008261516A JP5363060B2 (en) | 2008-07-03 | 2008-10-08 | Memory module and memory auxiliary module |
| JP2008-261516 | 2008-10-08 | ||
| PCT/JP2009/003102 WO2010001622A1 (en) | 2008-07-03 | 2009-07-03 | Memory module and auxiliary module for memory |
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| JP特许3540388B2 2004.07.07 |
| JP特许3600830B2 2004.12.15 |
| JP特许3635899B2 2005.04.06 |
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| Publication number | Publication date |
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| JP2010033533A (en) | 2010-02-12 |
| JP5363060B2 (en) | 2013-12-11 |
| CN102077180A (en) | 2011-05-25 |
| WO2010001622A1 (en) | 2010-01-07 |
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