JP5621409B2 - Memory module - Google Patents

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JP5621409B2
JP5621409B2 JP2010186059A JP2010186059A JP5621409B2 JP 5621409 B2 JP5621409 B2 JP 5621409B2 JP 2010186059 A JP2010186059 A JP 2010186059A JP 2010186059 A JP2010186059 A JP 2010186059A JP 5621409 B2 JP5621409 B2 JP 5621409B2
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memory
power supply
operation mode
unit
data
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JP2012043342A (en
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陽信 倉重
陽信 倉重
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株式会社バッファロー
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Description

  The present invention relates to a memory module equipped with a semiconductor memory and a nonvolatile memory.

  2. Description of the Related Art Conventionally, a memory module in which a plurality of semiconductor memory chips are mounted on a substrate, wired, and provided with connection terminals for connection to a computer has become widespread. As a memory provided in this memory module, there is an SDRAM (Synchronous Dynamic Random Access Memory). In the SDRAM, the inside is divided into a plurality of banks, and each bank can operate independently. By the way, as the memory capacity of the memory module increases, it is necessary to specify the memory cell to be accessed in response to the increase in the number of memory cells. However, the recognizable address may differ depending on the computer specifications. . In order to address these issues, the memory module is equipped with an EEPROM (Electric Erasable Programmable ROM), which is a volatile memory, and SPD (Serial Presence Detection), which is information on memory capacity, data width, control line, speed, etc. A technique is known in which data (hereinafter referred to as specific data) is stored in advance and the specific data is used to switch the access range of all memories in accordance with computer specifications (Patent Document 1). .

  However, even with the technique described in Patent Document 1, the memory module may not be able to operate normally.

JP 2010-92261 A

  An object of the present invention is to provide a memory module that allows all memory cells to be accessed and can be operated normally in light of solving the above-described problems of the prior art.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.
According to a first aspect of the present invention, a semiconductor memory and a non-volatile memory that stores specific data are mounted and connected to a memory control unit of a computer, and the semiconductor memory is connected to the semiconductor memory corresponding to the operation mode of the memory control unit. A memory module that changes the address of
A first power supply terminal for supplying a first supply voltage to the semiconductor memory;
A second power supply terminal for supplying a second supply voltage to the nonvolatile memory;
A data terminal for accessing the semiconductor memory and the nonvolatile memory to exchange data;
An address generation circuit connected to the data terminal and generating an address to the semiconductor memory corresponding to the operation mode;
An operation mode setting unit that is connected to the data terminal and sets the operation mode by an initialization process that selectively reads a plurality of specific data based on selection data stored in the nonvolatile memory;
A power supply unit connected to the first and second power supply terminals and supplying a drive voltage generated from the first or second supply voltage to the operation mode setting unit and the nonvolatile memory;
With
The power supply unit preferentially uses the first supply voltage from the first power supply terminal over the second supply voltage from the second power supply terminal.

[Application Example 1]
Application Example 1 includes a semiconductor memory and a nonvolatile memory that stores specific data connected to a memory control unit of a computer, and changes an address to the semiconductor memory in accordance with an operation mode of the memory control unit. A memory module,
A first power supply terminal for supplying a first supply voltage to the semiconductor memory;
A second power supply terminal for supplying a second supply voltage to the nonvolatile memory;
A data terminal for accessing the semiconductor memory and the nonvolatile memory to exchange data;
An address generation circuit connected to the data terminal and generating an address to the semiconductor memory corresponding to the operation mode;
An operation mode setting unit that is connected to the data terminal and sets the operation mode by an initialization process that selectively reads a plurality of specific data based on selection data stored in the nonvolatile memory;
A power supply unit connected to the first and second power supply terminals and supplying a drive voltage generated from the first or second supply voltage to the operation mode setting unit and the nonvolatile memory;
It is provided with.

  The memory module according to Application Example 1 is connected to a memory control unit of a computer, supplied with power from the computer, and drives a semiconductor memory based on specific data in the nonvolatile memory. That is, the power supply unit of the memory module is connected to the first and second power supply terminals. The power supply unit supplies a drive voltage to the operation mode setting unit and the non-volatile memory when receiving either one of the first and second supply voltages from the computer via the first or second power supply terminal. . The operation mode setting unit accesses the non-volatile memory, accesses identification data for determining the usage pattern of the semiconductor memory, and selectively reads specific data based on the determination result and sends it to the memory control unit. . The computer is permitted to use the semiconductor memory through the memory control unit.

  At this time, the power supply unit uses the second supply voltage from the second power supply terminal even if power is not supplied to the first power supply terminal, and even if power is not supplied to the second power supply terminal. By using the supply voltage from the first power supply terminal, the initialization process of the operation mode setting unit can be executed. Therefore, the initialization process can be executed even if the first supply voltage to the first power supply terminal is delayed from the second supply voltage to the second power supply terminal due to the specifications of the computer. Allows the use of memory modules.

[Application Example 2]
The power supply unit of Application Example 2 can be configured to preferentially use the first supply voltage from the first power supply terminal over the second supply voltage from the second power supply terminal. Accordingly, since power is supplied only from the first power supply terminal having a large power supply capacity, the operation mode setting unit can be stably operated.

[Application Example 3]
In Application Example 3, the nonvolatile memory includes a plurality of storage units each capable of reading and writing the specific data, and further includes a switch circuit interposed between the plurality of storage units and a data terminal, The switch circuit can be configured to selectively access the plurality of storage units by a switching signal from the operation mode setting unit.

[Application Example 4]
In Application Example 4, the nonvolatile memory is a storage unit that can be accessed by a clock signal and a data signal, and the switch circuit can be configured to switch at least the clock signal.

[Application Example 5]
In Application Example 5, the plurality of storage units include first and second storage units that store specific data, and a third storage unit that stores the selection data. The third storage unit includes: The operation mode setting unit may be connected so as to be directly accessible.

[Application Example 6]
Furthermore, the memory module of Application Example 6 includes a signal level conversion unit that converts signals input / output between the data terminal and the operation mode setting unit according to the voltage levels of the first and second supply voltages. Can be configured.

It is explanatory drawing explaining the computer which uses the memory module concerning one Example of this invention. It is explanatory drawing explaining the circuit of a power supply part. It is explanatory drawing explaining the circuit of a signal level conversion part. It is explanatory drawing explaining an operation mode setting part. It is explanatory drawing which shows the detection method of the operation mode of a memory control part. It is a flowchart explaining the recognition process of a memory module. It is a flowchart explaining an operation mode update process. It is explanatory drawing explaining operation | movement of a power supply part. It is explanatory drawing explaining the principal part of the memory module concerning another Example.

(1) Schematic Configuration of Memory Module FIG. 1 is an explanatory diagram for explaining a computer that uses a memory module according to an embodiment of the present invention. In FIG. 1, a computer 10 includes a central control unit 12 including a CPU, a computer main body 11 having a memory control unit 14 connected to the central control unit 12, and a memory control unit 14 connected to the memory control unit 14 and set in a memory slot. And a memory module 20. The memory module 20 includes a control circuit 21, a semiconductor memory 22, and a nonvolatile memory 23 for storing SPD data. The semiconductor memory 22 is an SRAM divided into 8 banks. The non-volatile memory 23 includes a first storage unit 23a and a second storage unit 23b configured from an EEPROM. The first storage unit 23a stores the first specific data SPD1 and the selection data SPDs, and the second storage unit 23b stores the second specific data SPD2. Here, the first specific data SPD1 includes data that causes the semiconductor memory 22 to operate in a virtual mode that is divided into 512 megabit addresses and accessed, and the second specific data SPD2 is an address of the 1 gigabit semiconductor memory 22 Corresponding to the space, the memory control unit 14 includes data for operating the semiconductor memory 22 in the normal mode in which all addresses are accessed. The memory control unit 14 selects the first specific data SPD1 or the second specific data SPD2 based on the selection data SPDs stored in the first storage unit 23a under the control of the control circuit 21, and selects the virtual mode or the normal mode. Thus, the memory module 20 is used by accessing the semiconductor memory 22.

(2) Configuration of Each Unit The control circuit 21 includes an address generation circuit 24, a power supply unit 25, a signal level conversion unit 26, an operation mode setting unit 27, and a reset unit 28.
When the memory module 20 is connected to the memory control unit 14, the address generation circuit 24 corresponds to each address output from the memory control unit 14 and each address input to the semiconductor memory 22 according to the capacity of the semiconductor memory 22. Is a circuit for generating an address for eliminating a mismatch in the number of bits. That is, even when the address generation circuit 24 is connected to the memory control unit 14 that does not support the semiconductor memory 22 (1 gigabit (64 megawords × 16 bits) DDR2 SDRAM), Each address for specifying a memory cell to be accessed is created.

  FIG. 2 is an explanatory diagram for explaining a circuit of the power supply unit 25. The power supply unit 25 includes a first power supply terminal 25a and a second power supply terminal 25b connected to a power supply terminal of the computer 10, and a first supply voltage Va (SDRAM power supply) and a second supply voltage supplied to each terminal. A circuit that adjusts Vb (SPD power supply) and outputs a drive voltage Vd to the operation mode setting unit 27 and the nonvolatile memory 23, and includes a backflow prevention diode 25c, a boosting unit 25d, a step-down unit 25e, And a switch 25f. 1.7 to 1.9V for the semiconductor memory 22 is supplied to the first power supply terminal 25a, and 1.7 to 3.6V for the nonvolatile memory 23 is supplied to the second power supply terminal 25b. .

  The operation of the power supply unit 25 will be described. When 1.7 to 1.9V is supplied to the first power supply terminal 25a, the voltage drops to 1.3 to 1.6V by passing through the diode 25c, but is boosted by the boosting unit 25d. The pressure is regulated to 1.7 to 1.9V. On the other hand, when 1.7 to 3.6 V is supplied to the second power supply terminal 25b, the voltage is regulated to 1.3 to 1.6 V by the step-down unit 25e, passes through the switch 25f, and further rises. The voltage is increased by 25d and regulated to 1.7 to 1.9V. When power is supplied from the second power supply terminal 25b and voltage is also supplied from the first power supply terminal 25a, the switch 25f is turned off and power supply from the second power supply terminal 25b is stopped. Then, power is supplied only from the first power supply terminal 25a. This is because the power source is selected based on the power source capacity difference supplied from the computer 10. That is, the second power supply terminal 25b only accesses the nonvolatile memory 23, and supplies power with a small capacity of several mA, whereas the first power supply terminal 25a accesses the semiconductor memory 22. This is because power having a large capacity of 2 to 3 A can be supplied, and the power from the first power supply terminal 25a is given priority and stable operation is performed. Therefore, if a voltage is supplied from either one of the terminals, the power supply unit 25 outputs the drive voltage Vd, and the first power supply terminal 25a side is given priority as the supply power.

  FIG. 3 is an explanatory diagram for explaining a circuit of the signal level conversion unit 26. The signal level conversion unit 26 is a level conversion circuit for matching the signal levels of the computer main body 11 side and the nonvolatile memory 23 of the memory module 20 with the voltage levels of the computer main body 11 and the memory module 20 side, respectively. This is a so-called open drain circuit. The signal level conversion unit 26 is used for SCL (clock signal) and SDA (data signal), respectively, but since it is the same circuit, the case of SDA (data signal) will be described. The signal level conversion unit 26 includes an nMOS transistor including a transistor element 26a and a diode element 26b, and a bias resistor. The transistor element 26 a has a drain D side connected to the data terminal of the computer main body 11 and a source S side connected to the operation mode setting unit 27. The source S side is connected to the output side of the power supply unit 25 via a resistor, the gate G side is connected to the output side of the power supply unit 25 via a resistor, and the drain D side is connected to the second supply voltage Vb. It is connected.

The operation of the signal level conversion unit 26 will be described. When the voltage level of the data terminal of the computer main body 11 and the operation mode setting unit 27 is “H”, the transistor element 26 a is turned off, and the drain D and the source S side are connected to the second supply voltage Vb and the power supply unit 25. The signal has a voltage level corresponding to the power supply voltage.
When the data terminal on the computer main body 11 side becomes “L” at 0V, a current flows through the diode element 26b, the voltage of the source S decreases, the voltage Vgs between the gate G and the source S of the diode element 26b increases, and the transistor The element 26a is turned on. As a result, the drain D and the source S are brought into conduction, and the voltage of the data terminal on the operation mode setting unit 27 side becomes “L” at 0 V which is the same as the data terminal of the computer main body 11. On the other hand, when the operation mode setting unit 27 side becomes “L” at 0 V, the gate G becomes 1.7 to 1.9 V, the source S becomes 0 V, and the transistor element 26 a is turned on. As a result, the drain D and the source S are conducted, and the data terminal on the computer 10 side becomes “L” at 0 V, which is the same as the data terminal on the computer main body 11 side.

  FIG. 4 is an explanatory diagram for explaining the operation mode setting unit 27. The operation mode setting unit 27 has a function of selecting an access method of the semiconductor memory 22 based on the selection data SPDs of the first storage unit 23a of the nonvolatile memory 23, and includes an operation mode detection unit 27a and a switch control unit 27b. And.

  The operation mode detection unit 27a detects the operation mode (1T operation / 2T operation) of the memory control unit 14. Here, the 1T operation is an operation mode capable of relatively high-speed access, while the 2T operation is an operation mode having a relatively low access speed. FIG. 5 is an explanatory diagram showing a method for detecting the operation mode of the memory control unit 14. The operation mode detection unit 27a sequentially acquires the chip select signal (CS) and the command address (RAS, CAS, WE) at each rising edge of the clock signal (CLK), and holds the command address for three times. These are sequentially compared to detect the operation mode of the memory control unit 14.

  That is, as shown in FIG. 5A, the operation mode detection unit 27a obtains the command address acquired at time t (0) when the acquired chip select signal (CS) is “L” at the previous time t When the command address acquired in (-1) is different, it is determined that the operation mode of the memory control unit 14 is 1T operation. In addition, as shown in FIG. 5B, the operation mode detection unit 27a determines that the command address acquired at time t (0) when the acquired chip select signal (CS) is “L” is the previous time t When the command address acquired in (-1) is the same as the command address acquired in t (-1) and is different from the command address acquired in t (-2), the memory control unit 14 It is determined that the operation mode is 2T operation.

  In FIG. 1, a reset unit 28 sends a reset signal to the operation mode setting unit 27 by power supply from the computer main body 11 side, and starts the operation mode setting unit 27.

(3) Operation of Memory Module 20 FIG. 6 is a flowchart for explaining recognition processing of the memory module 20. 1 is turned on, when power is supplied to the reset unit 28 via the central control unit 12, the memory control unit 14, and the power supply unit 25 of the memory module 20, the reset unit 28 A reset signal is sent to the operation mode setting unit 27 (step S102), and the register of the operation mode detection unit 27a is initialized (step S104). Subsequently, the operation mode setting unit 27 illustrated in FIG. 4 reads the selection data SPDs stored in advance in the first storage unit 23a. The selection data SPDs are stored in a register, and the operation mode is set by switching the switch 27c according to the selection data SPDs (step S108). As a result, the initialization process ends. After this initialization processing, the memory control unit 14 of the computer main body 11 determines the first or second identification of either the first storage unit 23a or the second storage unit 23b of the nonvolatile memory 23 according to the switching destination of the switch 27c. Data SPD1 and SPD2 are read (step S110). Subsequently, the computer main body 11 starts access to the semiconductor memory 22 by the memory control unit 14 and checks the semiconductor memory 22 (step S112). Thereby, the recognition process of the semiconductor memory 22 is completed.

  As shown in the flowchart of FIG. 7, the operation mode setting unit 27 monitors the command from the memory control unit 14 (step S120), and as described with reference to FIG. 5, the operation mode 1T or 2T is selected. Is determined (step S122), and it is determined whether or not the operation mode is the same as the selection data SPDs stored in advance in the first storage unit 23a (step S124). Update (step S126) and use the updated data in the next processing.

(4) According to the above embodiment, the following operations and effects are achieved.
(4) -1 The memory module 20 can selectively read the first and second specific data SPD1, SPD2 on the basis of the selection data SPDs, and can select an optimal usage method according to the specifications of the computer 10. .

(4) -2 FIG. 8 is an explanatory diagram for explaining the operation of the power supply unit 25. In FIG. 1, the power supply unit 25 of the memory module 20 supplies power from either the first supply voltage Va used for the semiconductor memory 22 or the second supply voltage Vb used for the nonvolatile memory 23 from the computer main body 11. Then, since the drive voltage Vd is supplied to the operation mode setting unit 27 and the nonvolatile memory 23, the initialization process of the operation mode setting unit 27 can be reliably executed. That is, the power supply unit 25 uses the second supply voltage Vb from the second power supply terminal 25b even if the first supply voltage Va is not supplied to the first power supply terminal 25a, and also applies to the second power supply terminal 25b. Even if the second supply voltage Vb is not supplied, the drive voltage Vd is generated using the first supply voltage Va, and is supplied to the operation mode setting unit 27 and the nonvolatile memory 23 to execute the initialization process. To do. Therefore, there is no problem in accessing the nonvolatile memory 23 and the semiconductor memory 22 after the initialization process.

(4) -3 As shown in FIG. 2, the power supply unit 25 is supplied with power from the second power supply terminal 25b, and when voltage is also supplied from the first power supply terminal 25a, Since power supply from the two power supply terminals 25b is stopped and power is supplied only from the first power supply terminal 25a having a larger current capacity than the second power supply terminal 25b, the operation mode setting unit 27 can be stably operated.

(4) -4 As shown in FIG. 3, the signal level conversion unit 26 converts the signal level between the computer main body 11 side and the nonvolatile memory 23 of the memory module 20 to the voltage level between the computer main body 11 and the memory module 20 side. Therefore, stable operation can be obtained.

  The present invention is not limited to the above-described embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

  FIG. 9 is an explanatory diagram for explaining a main part of a memory module according to another embodiment. This embodiment is characterized by a configuration for inputting / outputting specific data of a nonvolatile memory to / from a data terminal. The memory module 20B includes a nonvolatile memory 23B, a switch circuit 30, and an operation mode setting unit 27B having the same configuration as that of the embodiment of FIG. The nonvolatile memory 23B is an EEPROM that can be accessed by the clock signal SCL and the data signal SDA, and the first and second storage units 23Ba and 23Bb that store specific data and the third data that stores the selection data SPDs. And a storage unit 23Bc. The first and second storage units 23Ba and 23Bb are connected to the computer main body 11 via the switch circuit 30, and the third storage unit 23Bc is connected to the operation mode setting unit 27B so as to be directly accessible.

  The switch circuit 30 includes a switching control unit 31 that receives a switching signal from the operation mode setting unit 27B, and a first switch 32a and a second switch 32b that are alternatively switched by the switching control unit 31, and these are nMOSs. -It is composed of digital circuits centering on FET type transistors. The first switch 32a is connected to the clock signal SCL of the first storage unit 23Ba, and the second storage unit 23Bb is connected to the clock signal SCL of the second storage unit 23Bb, and is connected to the computer main body 11 via the data terminal. Has been. The switch circuit 30 alternatively outputs the data signal SDA of the first storage unit 23Ba or the second storage unit 23Bb according to the switching signal from the operation mode setting unit 27B. The data signal SDA is directly connected to the computer main body 11 via the data terminal from the first and second storage units 23Ba and 23Bb.

  The reason why such a switch circuit 30 is used is as follows. In the control circuit 21 of FIG. 1, when the current value of the data signal SDA input from the computer main body 11 is large and the voltage level from the nonvolatile memory 23 is “L”, the operation mode setting unit 27 and the signal level When the voltage level rises due to the internal resistance of the conversion unit 26 and reaches the computer main body 11, the signal level may exceed the threshold of the voltage level “L” of the computer main body 11 and the signal may become unstable.

  In the present embodiment, the first and second storage units 23Ba and 23Bb can directly access the computer main body 11 via the switch circuit 30 having a small internal resistance and switching only the clock signal SCL, that is, an operation mode having a large resistance value. Even when the current value of the data signal SDA input from the computer main body 11 is large because it does not go through the setting unit 27B, when the voltage levels of the first and second storage units 23Ba and 23Bb are “L”, An accurate signal can be obtained without exceeding the threshold of the voltage level “L” of the computer main body 11.

In addition, the nonvolatile memory 23B does not operate even when the clock signal SCL is at the voltage level “H” or “L”, and the voltage level of the data signal SDA changes to “H” or “L”. The switch circuit 30 may be a circuit that switches only the clock signal SCL and has a simple configuration.
Further, the third storage unit 23Bc does not need to be accessed with the computer main body 11, and since the operation mode setting unit 27B is directly accessed, the control and circuit of the memory module 20B can be simplified.

  In the embodiment of FIG. 9, the example of the nMOS type transistor digital switch has been described as the switch circuit 30. However, the present invention is not limited to this, and an analog switch (for example, FSUB30 (trade name: manufactured by FAIRCHILD)) may be used. The same action and effect are exhibited.

DESCRIPTION OF SYMBOLS 10 ... Computer 11 ... Computer main body 12 ... Central control part 14 ... Memory control part 20 ... Memory module 20B ... Memory module 21 ... Control circuit 22 ... Semiconductor memory 23 ... Non-volatile memory 23a ... 1st memory | storage part 23b ... 2nd memory | storage part 23B ... Non-volatile memory 23Ba ... First storage unit 23Bb ... Second storage unit 23Bc ... Third storage unit 24 ... Address generation circuit 25 ... Power supply unit 25a ... First power supply terminal 25b ... Second power supply terminal 25c ... Diode 25d ... Step-up unit 25e ... Step-down unit 25f ... Switch 26 ... Signal level conversion unit 26a ... Transistor element 26b ... Diode element 27 ... Operation mode setting unit 27B ... Operation mode setting unit 27a ... Operation mode detection unit 27b ... Switch control unit 27c ... Switch 28 ... Reset unit 30 ... Switch circuit 31 Switching controller 32a ... first switch 32 b ... second switch

Claims (5)

  1. A memory module that is connected to a memory control unit of a computer and includes a semiconductor memory and a non-volatile memory that stores specific data, and changes an address to the semiconductor memory in accordance with an operation mode of the memory control unit. And
    A first power supply terminal for supplying a first supply voltage to the semiconductor memory;
    A second power supply terminal for supplying a second supply voltage to the nonvolatile memory;
    A data terminal for accessing the semiconductor memory and the nonvolatile memory to exchange data;
    An address generation circuit connected to the data terminal and generating an address to the semiconductor memory corresponding to the operation mode;
    An operation mode setting unit that is connected to the data terminal and sets the operation mode by an initialization process that selectively reads a plurality of specific data based on selection data stored in the nonvolatile memory;
    A power supply unit connected to the first and second power supply terminals and supplying a drive voltage generated from the first or second supply voltage to the operation mode setting unit and the nonvolatile memory;
    Equipped with a,
    The power supply unit preferentially uses the first supply voltage from the first power supply terminal over the second supply voltage from the second power supply terminal .
  2. The memory module according to claim 1 ,
    The non-volatile memory has a plurality of storage units each capable of reading and writing the specific data,
    Furthermore, a switch circuit interposed between the plurality of storage units and the data terminal is provided, and the switch circuit can selectively access the plurality of storage units by a switching signal from the operation mode setting unit. A memory module that is configured to.
  3. The memory module according to claim 2 ,
    The non-volatile memory is a storage unit that is accessible by a clock signal and a data signal, and the switch circuit is configured to switch at least the clock signal.
  4. The memory module according to claim 2 or claim 3 ,
    The plurality of storage units include first and second storage units that store specific data, and a third storage unit that stores the selection data. The third storage unit is configured to set the operation mode. Memory module that is connected so that it can be accessed directly.
  5. The memory module according to claim 1 ,
    Furthermore, a memory module comprising a signal level conversion unit that converts signals input and output between the data terminal and the operation mode setting unit according to the voltage levels of the first and second supply voltages.
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JPH04260128A (en) * 1991-02-15 1992-09-16 Sharp Corp Specifications setting device for electric appliance
JPH1173368A (en) * 1997-08-28 1999-03-16 Seiko Epson Corp Memory module, method for control information processor and recording medium
JP3871853B2 (en) * 2000-05-26 2007-01-24 株式会社ルネサステクノロジ Semiconductor device and operation method thereof
JP4017177B2 (en) * 2001-02-28 2007-12-05 スパンション エルエルシー Memory device
JP4024123B2 (en) * 2002-10-10 2007-12-19 株式会社リコー Memory card control method and electronic device
JP4346369B2 (en) * 2003-08-08 2009-10-21 株式会社メルコホールディングス Memory module and memory auxiliary module
JP3120096U (en) * 2005-12-28 2006-03-23 センチュリーマイクロ株式会社 Memory module
JP2008276305A (en) * 2007-04-25 2008-11-13 Buffalo Inc Memory module, module and control method thereof
JP5363060B2 (en) * 2008-07-03 2013-12-11 株式会社バッファロー Memory module and memory auxiliary module
JP5481823B2 (en) * 2008-10-08 2014-04-23 株式会社バッファロー Memory module and memory auxiliary module
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