CN102056404B - Method for neutralizing capacitance of through hole - Google Patents

Abstract

The invention provides a method for neutralizing the capacitance of a through hole. The method is characterized in that in the design process of a printed circuit board (PCB), transmission lines at two sides of a through hole are thinned to be increased in inductance and reduced in capacitance relative to the original transmission lines, thereby being equivalent to that two small inductors are used for neutralizing the capacitance of the through hole; and by adding an inductive series mode around the through hole to neutralize the capacitance of the through hole, the inductance and the capacitance are mutually neutralized.

Description

In a kind of and the method for via hole capacitive

Technical field

The present invention relates generally to the signal integrity field, comprises that all signal speeds surpass 1Gbps, the high speed signal that transmits at printed circuit board (PCB) (PCB).

Background technology

At present, the continuous lifting of the speed of high speed signal, from the 2.5Gbps of Gen 1, the 5Gbps of Gen 2 has risen to the 8Gbps of PCIe Gen3 such as the speed of PCIe bus; Usb bus has risen to the 5Gbps of USB3.0 from the 480MHZ of USB2.0; The SAS signal has risen to 6Gbps from 1.5Gbps, 3Gbps; The speed of network chip has broken through the 10Gbps high point already ... the speed of signal is more and more higher, and the importance of signal integrity has more and more caused electronic design engineering teacher's attention.

But along with the raising of complexity in circuits, multiple-plate use, HW High Way unavoidably need be walked via hole, via hole on the impact of signal integrity also along with the lifting of signal speed becomes more and more obvious.

In and the via hole parasitic capacitance impact of signal integrity is become an importance improving signal quality.We will focus on research a kind of in and the method for via hole capacitive.

Summary of the invention

The purpose of this invention is to provide a kind of in and the method for via hole capacitive.

The objective of the invention is to realize in the following manner, in the design process of printing board PCB, offset the capacitive of via hole by the mode that around via hole, adds the perception series connection, perception and capacitive are cancelled out each other, concrete steps are that the transmission line on via hole both sides is attenuated, and make it with respect to original transmission line, present the increase of perception, the minimizing of capacitive so just is equivalent to use two small inductors to neutralize the electric capacity of via hole;

The every section following calculating of length of transmission line that presents perception in via hole both sides:

$L=\frac{Z_x}{T_x}\×\frac{C}{{\left(\frac{Z_x}{Z_o}\right)}^2-1}$

Wherein: Tx=L/670 presents the time delay of perceptual transmission line

Zx=presents the characteristic impedance Ohm of the transmission line of perception,

The characteristic impedance Ohm of the original transmission line of Zo=,

The Tx=signal is at the transmission time ns of transmission line that presents perception,

The parasitic capacitance pF of C=via hole

L=presents the length m il of the transmission line of perception

The maximum L that calculates gained must be so that Tx＜Trise, and namely the Tx time should be less than the rise time of signal.

Can impedance in the process that pcb board is propagated continuous in order to guarantee high speed signal, undistorted, in multiple sliding cover, can overcome the discontinuous impact that causes of capacitive reactances of via hole, need to carry out neutralisation treatment to the parasitic capacitance of via hole, reduce the impact that via hole causes.

The impact that method emphasis on analyzing via hole of the present invention causes, the PCB impedance requires continuously and the cabling mode of the mistake of pcb board is improved in order to obtain meeting, thereby obtain meeting the cabling mode of impedance code requirement, and then reach assurance signal integrity and EMI requirement.

Method of the present invention is compared with existing technology, beneficial effect is: by relatively finding out in the via hole capacitive and front and back: before adjustment, the impedance that is caused by the capacitive of via hole departs from scope and has reached-16%, do not satisfy us to the requirement of impedance management and control scope 10% or 15%, and its excursion only is 4.8% after adjusting.

Only by the improvement to Layout, without any need for the increase of cost, we are significantly improved at the signal integrity quality, are conducive to improve the signal integrity quality, reduce EMI.

Description of drawings

Fig. 1 is the cabling mode that improves the via hole capacitive;

Fig. 2 improves the theoretical model of via hole;

Fig. 3 improves the TDR analysis waveform curve before and after the via hole cabling.

Embodiment

Explain below with reference to Figure of description method of the present invention being done.

In order to understand the via hole parasitic capacitance to the impact of signal integrity, we at first use HSpice to do Time Domain Reflectometry simulation analysis, have a look the via hole parasitic capacitance to transmission line impedance cause discontinuous.

Improving front waveform Curves such as Fig. 3 and show, is to have added a TDR waveform that via hole obtains, the voltage waveform that the via hole that waveform modelling is seen from transmitting terminal reflects in the 50Ohms of 13.4Inch center of transmission line position.

Improve front wavy curve from Fig. 3 and can find out crossing the hole site reflected voltage and significantly decrease, illustrate that the characteristic impedance of transmission line has significant decline, caused impedance discontinuity, do not meet us to the requirement of signal integrity.In order to improve signal quality, improve signal integrity, in the design process of printing board PCB, we must try every possible means the capacitive of via hole parasitic capacitance is neutralized, and perhaps make and reduce by some way its impact.

The appearance value computing formula of via hole parasitic capacitance is as follows:

$C=\frac{{1.41\mathrm{\ϵ}}_{r}T{D}_1}{D_2-D_1}$

Wherein: the diameter of mesopore Antipad (inch) on the D2=ground level,

D1=is around the diameter (inch) of the pad Pad of through hole,

The thickness of T=circuit board (inch),

The relative dielectric constant of Er=circuit board

The parasitic capacitance of C=through hole (pF)

Embodiment

A Pad is 20mil, and Antipad is 30mil, and thickness of slab is 20mil, and dielectric constant is 4 through hole, is 0.2256pF by calculating its parasitic capacitance.

We can offset the capacitive of via hole by the mode that adds the perception series connection around via hole, perception and capacitive are cancelled out each other, improving rear waveform Curves such as Fig. 3 shows: the transmission line on via hole both sides is attenuated, make it with respect to original transmission line, present the increase of perception, the minimizing of capacitive uses two small inductors to neutralize the electric capacity of via hole.

The every section following calculating of length of transmission line that presents perception in via hole both sides:

$L=\frac{Z_x}{T_x}\×\frac{C}{{\left(\frac{Z_x}{Z_o}\right)}^2-1}$

Wherein: Tx=L/670 presents the time delay of perceptual transmission line

Zx=presents the characteristic impedance (Ohm) of the transmission line of perception,

The characteristic impedance of the original transmission line of Zo=(Ohm),

The Tx=signal is in the transmission time (ns) of transmission line that presents perception,

The parasitic capacitance of C=via hole (pF)

L=presents the length (mil) of the transmission line of perception

The maximum L that calculates gained must be so that Tx＜Trise, be that the Tx time should be less than the rise time of signal, structure can be thought lump so as shown in Figure 1, otherwise can cause jingle bell, and can not obtain capacitive and perceptual neutralization that we want, actual conditions also are easy to realize, can find out by following test data contrast.

Data before and after table 1 via hole improves relatively

Center voltage voltage deviation value presents impedance and departs from scope

Without Adjusting 514mV -45mV 42.0Ohms -16％

After Adjusting 511mV 12mV 52.4Ohms 4.8％

Emulation and test environment

TDR simulation software: HSpice

Impedance simulation software: SI9000

Except the described technical characterictic of specification, be the known technology of those skilled in the art.

Claims (1)

1. method of via hole capacitive that neutralizes, it is characterized in that, in the design process of printing board PCB, the transmission line on via hole both sides is attenuated, make it with respect to original transmission line, present the increase of perception, the minimizing of capacitive so just is equivalent to use two small inductors to neutralize the electric capacity of via hole; By around via hole, adding in the perceptual mode of connecting and the capacitive of via hole, perception and capacitive are neutralized mutually, the every section following calculating of length of transmission line that presents perception in via hole both sides:

Wherein: Tx=L/670 presents the time delay of perceptual transmission line

Zx=presents the characteristic impedance Ohm of the transmission line of perception,

The characteristic impedance Ohm of the original transmission line of Zo=,

The Tx=signal is at the transmission time ns of transmission line that presents perception,

The parasitic capacitance pF of C=via hole

L=presents the length m il of the transmission line of perception

The maximum L that calculates gained must be so that Tx＜Trise, and namely the Tx time should be less than the rise time of signal;

In order to improve signal quality, improve signal integrity, in the design process of printing board PCB, the capacitive of via hole parasitic capacitance is neutralized, perhaps make and reduce by some way its impact;

The appearance value computing formula of via hole parasitic capacitance is as follows:

Wherein: D ₂The diameter of mesopore Antipad (inch) on=ground level,

D ₁=around the diameter (inch) of the pad Pad of through hole,

The thickness of T=circuit board (inch),

ε _rThe relative dielectric constant of=circuit board

The parasitic capacitance of C=through hole (pF).

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