CN102054775A - Method for manufacturing semiconductor structure - Google Patents
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- CN102054775A CN102054775A CN 200910209357 CN200910209357A CN102054775A CN 102054775 A CN102054775 A CN 102054775A CN 200910209357 CN200910209357 CN 200910209357 CN 200910209357 A CN200910209357 A CN 200910209357A CN 102054775 A CN102054775 A CN 102054775A
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Abstract
The invention provides a method for manufacturing a semiconductor structure, which comprises the following steps of: providing a metal oxide semiconductor (MOS) device, wherein a dielectric layer, and first and second contact holes penetrating the dielectric layer are formed in a first diffusion region and a gate region, and the second contact holes is less than the first contact holes; forming a metal layer until the first and second contact holes are completely filled so as to form a first interconnecting plug in the first diffusion region and a second interconnecting plug in the gate region; chemically and mechanically polishing the metal layer; etching the dielectric layer; forming a first diffusion region metal pad on the dielectric layer corresponding to the first diffusion region and the first interconnecting plug, and forming a gate metal pad on the dielectric layer corresponding to the gate region and the second interconnecting plug. The packaging yield of the semiconductor device is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of semiconductor structure.
Background technology
Along with the making of integrated circuit develops to very lagre scale integrated circuit (VLSIC), the current densities of IC interior is increasing, and the number of elements that is comprised is also more and more, and described element need pass through metal interconnecting wires or metal interconnected connector conductive interconnection.
In the application of semiconductor device, the DMOS transistor comprises high current driving ability, low on-resistance and high-breakdown-voltage etc. owing to have lot of advantages, therefore obtains using more widely.DMOS mainly contains two types, vertical double-diffusion metal-oxide-semiconductor field effect transistor (verticaldouble-diffused MOSFET, be called for short VDMOSFET) and lateral double diffusion metal oxide semiconductor field effect transistor (1ateral double-dif fused MOSFET is called for short LDMOSFET).VDMOS is a kind of power device of vertical double diffusion structure, and it comprises a plurality of vdmos transistors of arrayed, and the grid of described vdmos transistor all is connected to a gate liner, and the source electrode of described vdmos transistor all is connected to a source pad.Described connection is by metal interconnected connector conductive interconnection.
In being 200610030809.4 Chinese patent literature, application number can find more formation scheme about existing interconnection connector.Fig. 1 to Fig. 6 is the schematic diagram of the interconnection connector between the existing formation two metal layers.To shown in Figure 6, at first provide Semiconductor substrate as Fig. 1 with first conductive layer 10; Then on first conductive layer 10, form dielectric layer 20; Then the dielectric layer on first conductive layer 10 20 is carried out etching, form contact hole 30 in dielectric layer 20, this contact hole 30 exposes first conductive layer 10; Then form metal in dielectric layer 20 and contact hole 30, for example tungsten is filled up to contact hole; Then carry out cmp, grind and to stop at the dielectric layer surface, thereby make contact hole on the dielectric layer 20 be removed with the metal of external position, so just formed interconnection connector 40, i.e. tungsten plug, and dielectric layer and tungsten plug upper surface are flat surfaces; Then form metal gasket 50 at dielectric layer and tungsten plug upper strata, for example concrete gate liner that on grid, forms with the grid conductive interconnection, on the diffusion region, source area for example forms the diffusion region liner with the diffusion region conductive interconnection, for example source pad; Then the device of again manufacturing being finished encapsulates, and has just obtained semiconductor device.
But the problem that prior art exists is, when the DMOS semiconductor device that utilizes the said method manufacturing to finish is encapsulated, owing to do not have aberration between gate liner and the diffusion region liner, wherein the diffusion region liner comprises source pad and drain pad, therefore traditional sealed in unit can't be distinguished diffusion region liner and gate liner, therefore be easy to cause encapsulation to lose efficacy, thereby the yield of encapsulation is very low.
Summary of the invention
The technical problem that the present invention solves is to improve the encapsulation yield of semiconductor device.
In order to address the above problem, the invention provides a kind of manufacture method of semiconductor structure, comprise step:
MOS is provided device, described MOS device comprises at least two MOS transistor of arrayed, described MOS transistor comprises Semiconductor substrate, first diffusion region, second diffusion region and gate regions, described first diffusion region and second diffusion region are conduction type of the same race, on described first diffusion region and gate regions, has dielectric layer, and have first and second contact holes that run through described dielectric layer respectively, the described second contact hole quantity is less than the described first contact hole quantity;
Form to cover the metal level of described first diffusion region and gate regions, up to described first and second contact holes by complete filling;
Described metal level is carried out cmp, and the metal level on described dielectric layer is removed fully, so far, forms the first interconnection connector and the second interconnection connector respectively in first contact hole and second contact hole;
Described dielectric layer is carried out etching, remove the dielectric layer of segment thickness, make the dielectric layer surface be lower than the surface of the above-mentioned first interconnection connector and the second interconnection connector;
On the dielectric layer of the first diffusion region correspondence and the first interconnection connector, form the first diffusion region metal gasket, on the dielectric layer of gate regions correspondence and the second interconnection connector, form the gate metal liner.
Preferably, described first diffusion region is a source area, and described second diffusion region is the drain region.
Preferably, near the surface, and first diffusion region, second diffusion region and gate regions arrange side by side in described Semiconductor substrate for described first diffusion region, second diffusion region and gate region, and described second diffusion region and first diffusion region lay respectively at the both sides of gate regions.
Preferably, described dielectric layer also covers described second diffusion region, has the 3rd contact hole that runs through dielectric layer on described second diffusion region;
Form in the step of the metal level that covers described first diffusion region, described metal level also covers second diffusion region, and forms the 3rd interconnection connector;
After described dielectric layer is carried out etch step, also be included on the dielectric layer of the second diffusion region correspondence and the 3rd interconnection connector and form the second diffusion region metal gasket.
Preferably, described MOS device is the VDMOS device, and described MOS transistor is a vdmos transistor.
Preferably, described first diffusion region is the drain region, and described second diffusion region is a source area.
Preferably, described dielectric layer is an oxide.
The thickness of the described dielectric layer that preferably, etches away is 1800 dust to 2000 dusts.
Preferably, described MOS device is the LDMOS device, and described MOS transistor is a ldmos transistor.
Compared with prior art, the present invention mainly has the following advantages:
The present invention is by improving production process of semiconductor device, in interconnection connector forming process, increase the etch step of a step after the chemical mechanical milling tech again to dielectric layer, thereby make the top of interconnection connector expose, like this after forming the interconnection liner, because the interconnection connector under the gate metal liner is different with the interconnection connector number under the first diffusion region metal gasket, therefore the first diffusion region metal gasket that forms is different with the surface flatness of gate metal liner, make the gate metal liner present different aberration like this with the first diffusion region metal gasket, the gate metal liner and the first diffusion region metal gasket are distinguished easily when making encapsulation, have improved the encapsulation yield.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 to Fig. 6 is the schematic diagram of the interconnection connector between the existing formation two metal layers;
Fig. 7 is the flow chart of the manufacture method of semiconductor structure of the present invention;
Fig. 8 to Figure 12 is the schematic diagram of manufacture method first embodiment of semiconductor structure of the present invention;
Figure 13 is the schematic diagram of manufacture method second embodiment of semiconductor structure of the present invention.
Embodiment
By background technology as can be known, in the prior art, because will have the surface treatment of the semiconductor structure of interconnection connector before the formation metal gasket is flat surfaces, therefore the metal gasket surface that forms on the semiconductor structure surface like this is a flat surfaces, therefore there is not aberration between diffusion region metal gasket and the gate metal liner, for example gate metal liner and source metal liner do not have aberration between gate metal liner and the drain metal liner.In encapsulation, just be not easy to distinguish diffusion region metal gasket and gate metal liner like this, thereby be easy to cause encapsulation to lose efficacy, thereby the yield of encapsulation is very low.
The present inventor thinks through a large amount of experimental studies, if want to overcome the problems referred to above in the prior art, usually adopt two kinds of methods, a kind of is by improving on the encapsulation condition, improve the discrimination ability of sealed in unit, discern diffusion region metal gasket and gate metal liner, but need the higher sealed in unit of precision like this, thereby raise the cost; Another kind is by revising the domain of device, for example increase the distance of gate metal liner and diffusion region metal gasket, encapsulate thereby be convenient to sealed in unit, but can waste chip area like this, thereby device size being excessive.
The inventor is through discovering, the MOS transistor diffusion region of the arrayed that has is by interconnection connector conductive interconnection, so the diffusion region has more interconnection connector, and gate regions itself is the integral body that is communicated with, and does not therefore have the interconnection connector.The inventor also finds then can bring aberration if the flatness on gate metal pad surfaces and metal gasket surface, diffusion region is different.Therefore, the inventor provides a kind of manufacture method of semiconductor structure, by production process of semiconductor device is improved, in interconnection connector forming process, increase the etch step of a step after the chemical mechanical milling tech again to dielectric layer, thereby make the top of interconnection connector expose, like this after forming metal gasket, because the interconnection connector under the gate metal liner is different with the interconnection connector number under the metal gasket of diffusion region, therefore the diffusion region metal gasket that forms is different with the surface flatness of gate metal liner, make the gate metal liner present different aberration like this with the diffusion region metal gasket, gate metal liner and diffusion region metal gasket are distinguished easily when making encapsulation, have improved the encapsulation yield.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 7 is the flow chart of the manufacture method of semiconductor structure of the present invention, and Fig. 8 to Figure 12 is the schematic diagram of manufacture method first embodiment of semiconductor structure of the present invention.
Manufacture method below in conjunction with Fig. 7 to 12 pair of semiconductor structure of the present invention describes, and is example with the VDMOS device wherein.Comprise step:
S10: MOS is provided device.
Wherein, described MOS device comprises at least two MOS transistor of arrayed, described MOS transistor comprises Semiconductor substrate, first diffusion region, second diffusion region and gate regions, described first diffusion region and second diffusion region are conduction type of the same race, described first diffusion region and gate region are in the close surface of described Semiconductor substrate, and arrange side by side, on described first diffusion region and gate regions, has dielectric layer, and have first and second contact holes that run through described dielectric layer respectively, the described first contact hole quantity is less than the described second contact hole quantity.
Below with reference to Fig. 8, be illustrated, described MOS transistor is the vdmos transistor of vertical proliferation, and arrayed successively.Vdmos transistor has the second diffusion region metal gasket 110, i.e. drain metal liner.Have Semiconductor substrate 115 on the drain metal liner 110, described Semiconductor substrate comprises: second diffusion region 120, epitaxial loayer 130, tagma 140 and first diffusion region 150.
Described second diffusion region 120 is positioned on the second diffusion region metal gasket 110, and described second diffusion trivial 120 is a heavily doped layer, has first conduction type.Can inject formation by carry out high concentration n type ion to polysilicon layer, dopant ion can be arsenic or antimony or phosphorus etc.Described second diffusion region 120 is the drain region.
Described epitaxial loayer 130 is positioned on second diffusion region 120, has concentration and is lower than described heavily doped layer ion concentration.Can be on n type second diffusion region 120 epitaxial growth n type doped regions, as epitaxial loayer 130.
Described tagma 140 has second conduction type, and described second conduction type and first conductivity type opposite are positioned on the described epitaxial loayer 130.Specifically, can on epitaxial loayer 130, pass through method growth oxide layers such as physical deposition or chemical deposition earlier; Then, can inject by carry out ion to described oxide layer surface, for example the boron ion; Then, by High temperature diffusion, form the tagma 140 that the p type mixes.
Described first diffusion region 150 is positioned on the tagma 140, has high-dopant concentration, has first conduction type, and described first diffusion region 150 is source area.Specifically, first etching forms source area injection window; Then, carry out the ion injection by inject window to source area, the ion that is injected can be arsenic or antimony or phosphorus etc., forms to have the heavily doped source area of n type.
The gate regions 160 of described vdmos transistor is passed described first diffusion region 150 and described tagma 140 and is arrived described epitaxial loayer 130.Specifically, can utilize following method to form: etching forms passes first diffusion region 150 and tagma 140, and arrives the groove of epitaxial loayer 130; Then, in formed groove,, in flute surfaces, form gate insulation layer 160a, for example silica by modes such as thermal oxidation or chemical vapour deposition (CVD)s; Then,, on gate insulation layer, form polysilicon, make polysilicon fill with groove, and, form gate regions 160 by mode place to go grooves such as cmp outer silica and polysilicon by modes such as chemical vapour deposition (CVD)s.
Has dielectric layer 170 on described first diffusion region 150 and the gate regions 160, concrete can be by modes such as thermal oxidation or chemical vapour deposition (CVD)s, form silicon dioxide or silicon nitride in first diffusion region and gate regions 160 surfaces, constitute the dielectric layer 170 that covers first diffusion region 150 and gate regions 160.Described dielectric layer 170 plays isolation and the insulating effect between the different device layers.In the present embodiment, described dielectric layer 170 is an oxide, and for example the material of dielectric layer 170 can be selected from SiO
2The perhaps SiO of Can Zaing
2As USG (Undoped silicon glass, the silex glass that does not have doping), BPSG (Borophosphosilicate glass, the silex glass of boron phosphorus doped), BSG (borosilicate glass, the silex glass of doped with boron), PSG (Phosphosilitcate Glass, the silex glass of Doping Phosphorus) etc.
Have first contact hole 182 in first diffusion region 150 and the dielectric layer 170 on it, concrete can be to pass described dielectric layer 170 and described first diffusion region 150, and runs through first contact hole 182 that dielectric layer 170 arrives described tagma 140.
The gate regions 160 of at least two described MOS transistor links to each other, for example can link to each other with the gate regions of the vdmos transistor of delegation or same row, perhaps whole vdmos transistor gate regions links to each other, and has second contact hole 184 that runs through dielectric layer in gate regions 160 that links to each other and the dielectric layer 170 on it.Described second contact hole, 184 quantity are less than described first contact hole, 182 quantity.For example in the VDMOS device, all gate regions with the vdmos transistor of delegation or same row link to each other, and in same grid production process, form, therefore as long as on a gate regions that links to each other, form second contact hole 184, just can realize the interconnection with the subsequent gate metal gasket, and the connection between first diffusion region (source area) of different vdmos transistors is to realize by the interconnection connector that first contact hole 182 forms.That is to say, the number of the vdmos transistor that the second contact hole number on the gate regions of VDMOS device comprises less than the VDMOS device, for example has 1 second contact hole 184 in the gate regions of VDMOS device, and for whole VDMOS device, the number of first contact hole should be greater than or equal to the number of vdmos transistor in first diffusion region, and therefore described second contact hole, 184 quantity are less than described first contact hole, 182 quantity.
Specifically, at first, etching forms first contact hole 182 and second contact hole 184, dielectric layer 170 and first diffusion region 150 and arrival tagma 140 are slightly passed in the bottom of this first contact hole 182, the bottom of second contact hole 184 is slightly passed dielectric layer 170 backs and is arrived gate regions 160, described etching can be dry etching, and etching gas can adopt and comprise carbon tetrafluoride CF
4Etching gas.
Preferably, has the heavily doped regional 115a of second conduction type in described first contact hole 182 bottoms.For example can carry out ion in first contact hole, 182 bottoms and inject, to form p type heavily doped region.For example, dopant ion is for can be the boron ion, and doping content can be 3 * 10
15/ cm
3, the injection energy is 25KeV.
S20: form to cover the metal level 190 of described first diffusion region 150 and gate regions 160, up to described first contact hole 182 and second contact hole 184 by complete filling.
Concrete, this step can adopt method well known to those skilled in the art, for example with reference to figure 9, plated metal on the diffusion region, for example can be by the mode of chemical vapour deposition (CVD), adopt the mist of tungsten fluoride, silane and hydrogen, carry out the deposit of tungsten, and make it fill with first contact hole 182 and second contact hole 184.
S30: described metal level 190 is carried out cmp, and the metal level 190 on described dielectric layer 170 is removed fully, so far, forms the first interconnection connector 180a and the second interconnection connector 180c respectively in first contact hole 182 and second contact hole 184.
Concrete, this step can adopt method well known to those skilled in the art, and for example with reference to Figure 10, the concrete parameter of described chemico-mechanical polishing is: select SiO for use
2Polishing fluid, the pH value of polishing fluid is 10 to 11.5, the flow of polishing fluid is 120 milliliters of per minute to 170 milliliter per minutes, the rotating speed of grinding pad is 65 rpms to 80 rpms in the glossing, the rotating speed of grinding head is 55 rpms to 70 rpms, and the pressure of glossing is 200 handkerchief to 350 handkerchiefs.
S40: described dielectric layer 170 is carried out etching, remove the dielectric layer 170 of segment thickness.
Concrete, this step can adopt method well known to those skilled in the art, for example with reference to Figure 11, described etching dielectric layer can be any conventional lithographic technique, such as chemical etching technology or plasma etching technology, in the present embodiment, the using plasma lithographic technique.
The for example concrete inductively coupled plasma type etching apparatus of selecting for use, the etching apparatus chamber pressure is 10 millitorr to 50 millitorrs, the top radio-frequency power is 200 watts to 500 watts, the bottom radio-frequency power is 150 watts to 300 watts, the C4F8 flow is that per minute 10 standard cubic centimeters (10SCCM) are to per minute 50 standard cubic centimeters, the CO flow is that per minute 100 standard cubic centimeters are to per minute 200 standard cubic centimeters, the Ar flow is that per minute 300 standard cubic centimeters are to per minute 600 standard cubic centimeters, the O2 flow be per minute 10 standard cubic centimeters to per minute 50 standard cubic centimeters, etching dielectric layer 200 is until first and second contact holes that form exposing metal layer 110.Described etching technics can also carry out in other etching apparatuss, as capacitance coupling plasma type etching apparatus, inductive couple plasma etching apparatus.
In the present embodiment, the thickness of the described dielectric layer that etches away is 1800 dust to 2000 dusts, for example 1850 dusts, 1900 dusts, 1950 dusts.
S50: on the dielectric layer 170 of first diffusion region, 150 correspondences and the first interconnection connector 180a, form the first diffusion region metal gasket 210, on the dielectric layer 170 of gate regions 160 correspondences and the second interconnection connector 180c, form gate metal liner 220.
Concrete, this step can adopt method well known to those skilled in the art, for example with reference to Figure 12, the concrete process conditions of described formation comprise: physical vapor deposition target material material is an aluminium, reaction temperature is 250 degrees centigrade to 500 degrees centigrade, chamber pressure is 10 millitorr to 18 millitorrs, and direct current power is 10000 watts to 40000 watts, and argon flow amount is that per minute 2 standard cubic centimeters are to per minute 20 standard cubic centimeters.
Only utilize cmp to remove metal level 190 in the prior art, therefore the surface after grinding is a flat surfaces, when forming the first diffusion region metal gasket 210 and gate metal liner 220, be not easy to distinguish the position that forms the first diffusion region metal gasket 210 and gate metal liner 220, and in the present invention because increased the step of etching dielectric layer again after the cmp, therefore the first interconnection connector 180a protrudes out from the semiconductor structure surface before forming the first diffusion region metal gasket 210, therefore when this step forms the first diffusion region metal gasket 210, the first diffusion region metal gasket 210 has projection 230 in the position of the first interconnection connector 180a, because first diffusion region has very many interconnection connectors, therefore the first diffusion region metal gasket 210 has more projection 230.And gate metal liner 220 because of following interconnection connector seldom, so the projection of gate metal liner just seldom, perhaps only has at the edge.So just make win diffusion region metal gasket 210 and gate metal liner 220 present aberration.
Therefore in encapsulation, the gate metal liner and the first diffusion region metal gasket are distinguished easily when making encapsulation, have improved the encapsulation yield.
Above-mentioned steps S10 does not limit the formation method of appropriate section to step S50, or also can adopt other technology or other reactant and other concentration and realize, those skilled in the art will be understood that each or several conversion to the step S50 does not impact the present invention's design about described step S10.
In other embodiments, can described first diffusion region be the drain region also, described second diffusion region is a source area.
Figure 13 is the schematic diagram of manufacture method second embodiment of semiconductor structure of the present invention.Because second embodiment and first embodiment are similar, therefore second embodiment part identical with first embodiment repeats no more, and difference is:
In the present embodiment, described MOS device comprises at least two ldmos transistors of arrayed, described ldmos transistor comprises Semiconductor substrate 330, first diffusion region 320, second diffusion region 350 and gate regions 340, described first diffusion region 320 and second diffusion region 350 are conduction type of the same race, described first diffusion region 320 and gate regions 340 are positioned at described Semiconductor substrate 330 near the surface, and arrange side by side, on described first diffusion region 320 and gate regions 340, has dielectric layer 360, in first diffusion region 320 and the dielectric layer 360 on it, has first contact hole, the gate regions 340 of LDMOS device links to each other, and have second contact hole in gate regions 340 and the dielectric layer 360 on it, the second contact hole quantity is less than the first contact hole quantity.
Described second diffusion region 350 is positioned at described Semiconductor substrate 330 near the surface, and arranges side by side with gate regions 340, and described second diffusion region 350 and first diffusion region 320 lay respectively at the both sides of gate regions 340.
Described dielectric layer 360 also covers on 350, the second diffusion regions 350, described second diffusion region has the 3rd contact hole that runs through described dielectric layer 360.
Form in the step of the metal level that covers described first diffusion region 320, described metal level also covers second diffusion region 350, and forms the 3rd interconnection connector 390, and metal level is covering gate polar region 340 also, and forms the second interconnection connector 395.
After described dielectric layer 360 is carried out etch step, also be included on the dielectric layer 360 of second diffusion region, 350 correspondences and the 3rd interconnection connector 390 and form the second diffusion region metal gasket 400, also be included on the dielectric layer 360 of gate regions 340 correspondences and the 3rd interconnection connector 395 and form gate metal liner 450.Because the gate regions of at least two ldmos transistors links to each other, and the gate regions that links to each other is connected to gate metal liner 450 by one the 3rd interconnection connector 395, and for example the gate regions of whole ldmos transistors links to each other and is connected to gate metal liner 450 by the second interconnection connector 395 that is positioned at the LDMOS device edge as shown in figure 13.
Wherein, first diffusion region 320 is a source area, and second diffusion region is the drain region.Can first diffusion region 320 be the drain region also in other embodiments, second diffusion region be a source area.
Because the interconnection connector protrudes out from the semiconductor structure surface before forming the first diffusion region metal gasket, therefore when this step forms the first diffusion region metal gasket, the first diffusion region metal gasket has projection in the position of interconnection connector, because first diffusion region has very many interconnection connectors, therefore the first diffusion region metal gasket has more projection, and the same second diffusion region metal gasket has more projection.And the gate metal liner because of following interconnection connector seldom, so the projection of gate metal liner just seldom, perhaps only has at the edge.So just make win diffusion region metal gasket and gate metal liner present aberration, the second diffusion region metal gasket and gate metal liner present aberration.
So in encapsulation, the gate metal liner and the first diffusion region metal gasket when making encapsulation, the gate metal liner and the second diffusion region metal gasket are distinguished easily, have improved the encapsulation yield.
In other embodiments, also the step that forms the first diffusion region metal gasket and the second diffusion region metal gasket can be separated, for example only the described dielectric layer on first diffusion region or second diffusion region be carried out etching; Thereby only form projection at the first diffusion region metal gasket or metal gasket surface, second diffusion region.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (9)
1. the manufacture method of a semiconductor structure is characterized in that, comprises step:
MOS is provided device, described MOS device comprises at least two MOS transistor of arrayed, described MOS transistor comprises Semiconductor substrate, first diffusion region, second diffusion region and gate regions, described first diffusion region and second diffusion region are conduction type of the same race, on described first diffusion region and gate regions, has dielectric layer, and have first and second contact holes that run through described dielectric layer respectively, the described second contact hole quantity is less than the described first contact hole quantity;
Form to cover the metal level of described first diffusion region and gate regions, up to described first and second contact holes by complete filling;
Described metal level is carried out cmp, and the metal level on described dielectric layer is removed fully, so far, forms the first interconnection connector and the second interconnection connector respectively in first contact hole and second contact hole;
Described dielectric layer is carried out etching, remove the dielectric layer of segment thickness, make the dielectric layer surface be lower than the surface of the above-mentioned first interconnection connector and the second interconnection connector;
On the dielectric layer of the first diffusion region correspondence and the first interconnection connector, form the first diffusion region metal gasket, on the dielectric layer of gate regions correspondence and the second interconnection connector, form the gate metal liner.
2. the manufacture method of semiconductor structure according to claim 1 is characterized in that, described first diffusion region is a source area, and described second diffusion region is the drain region.
3. the manufacture method of semiconductor structure according to claim 2, it is characterized in that, described first diffusion region, second diffusion region and gate region are in the close surface of described Semiconductor substrate, and first diffusion region, second diffusion region and gate regions are arranged side by side, and described second diffusion region and first diffusion region lay respectively at the both sides of gate regions.
4. the manufacture method of semiconductor structure according to claim 3 is characterized in that, described dielectric layer also covers described second diffusion region, has the 3rd contact hole that runs through dielectric layer on described second diffusion region.
Form in the step of the metal level that covers described first diffusion region, described metal level also covers second diffusion region, and forms the 3rd interconnection connector;
After described dielectric layer is carried out etch step, also be included on the dielectric layer of the second diffusion region correspondence and the 3rd interconnection connector and form the second diffusion region metal gasket.
5. the manufacture method of semiconductor structure according to claim 2 is characterized in that, described MOS device is the VDMOS device, and described MOS transistor is a vdmos transistor.
6. the manufacture method of semiconductor structure according to claim 1 is characterized in that, described first diffusion region is the drain region, and described second diffusion region is a source area.
7. the manufacture method of semiconductor structure according to claim 1 is characterized in that, described dielectric layer is an oxide.
8. the manufacture method of semiconductor structure according to claim 7 is characterized in that, the thickness of the described dielectric layer that etches away is 1800 dust to 2000 dusts.
9. the manufacture method of semiconductor structure according to claim 1 is characterized in that, described MOS device is the LDMOS device, and described MOS transistor is a ldmos transistor.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094111A (en) * | 2011-10-31 | 2013-05-08 | 无锡华润上华科技有限公司 | Double diffusion metal oxide semi-conductor (DMOS) device and manufacturing method thereof |
| CN103824776A (en) * | 2012-11-16 | 2014-05-28 | 无锡华润上华科技有限公司 | Dmos device and manufacturing method thereof |
| CN107104120A (en) * | 2017-05-24 | 2017-08-29 | 成都线易科技有限责任公司 | Magnetic induction device and manufacture method |
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| US7759731B2 (en) * | 2006-08-28 | 2010-07-20 | Advanced Analogic Technologies, Inc. | Lateral trench MOSFET with direct trench polysilicon contact and method of forming the same |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094111A (en) * | 2011-10-31 | 2013-05-08 | 无锡华润上华科技有限公司 | Double diffusion metal oxide semi-conductor (DMOS) device and manufacturing method thereof |
| WO2013064015A1 (en) * | 2011-10-31 | 2013-05-10 | 无锡华润上华科技有限公司 | Dmos device and manufacturing method for same |
| CN103094111B (en) * | 2011-10-31 | 2016-04-06 | 无锡华润上华科技有限公司 | DMOS device and manufacture method thereof |
| CN103824776A (en) * | 2012-11-16 | 2014-05-28 | 无锡华润上华科技有限公司 | Dmos device and manufacturing method thereof |
| CN103824776B (en) * | 2012-11-16 | 2016-12-21 | 无锡华润上华科技有限公司 | DMOS device and manufacture method thereof |
| CN107104120A (en) * | 2017-05-24 | 2017-08-29 | 成都线易科技有限责任公司 | Magnetic induction device and manufacture method |
| CN107104120B (en) * | 2017-05-24 | 2019-03-15 | 成都线易科技有限责任公司 | Magnetic induction device and manufacturing method |
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