CN103824776B - DMOS device and manufacture method thereof - Google Patents
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- CN103824776B CN103824776B CN201210465871.1A CN201210465871A CN103824776B CN 103824776 B CN103824776 B CN 103824776B CN 201210465871 A CN201210465871 A CN 201210465871A CN 103824776 B CN103824776 B CN 103824776B
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Abstract
The invention discloses a kind of DMOS device making method, including: providing substrate, include source region and the inter-level dielectric ILD layer being positioned in surfaces of active regions, the ILD layer being positioned in surfaces of active regions has tungsten plug, ILD layer surface and tungsten plug flush；Get rid of the ILD layer material of preset thickness, make ILD layer and tungsten plug surface have difference in height；Using EKC solution 65 70 DEG C to clean 5 30min, the EKC solution of residual removed by isopropanol, and bath repeatedly, dries；There is ILD layer and the tungsten plug forming metal layer on surface of difference in height, entering metal interconnection process, after completing metal interconnection process, form pressure welding point on the metal layer, carry out low-temperature alloy technique, complete the manufacturing process of DMOS device.The present invention, by increasing EKC cleaning step, eliminates the polymer produced after ILD layer returns quarter, makes ILD layer and metal interface more tight, and the metal level being subsequently formed will not peel off after packaging.
Description
Technical field
The invention belongs to technical field of manufacturing semiconductors, be specifically related to a kind of DMOS device and manufacture method thereof.
Background technology
After the manufacturing process of semiconductor chip completes, it is accomplished by carrying out the assembling of one single chip by the silicon chip of electrical testing
And encapsulation, these operations carried out in final assembling and encapsulation, it being referred to as later process, later process also includes level package
With second level package etc..Wherein level package includes thinning back side, burst, shelves and the technical process such as wire bonding.At lead-in wire
In bonding process, need to enter the electrode on the metal pressure point of chip surface and lead frame or on pedestal inner (also referred to as post)
Row is electrically connected with, and before this, for DMOS device, needs grid region and the source region of first recognition means, afterwards, then uses metal to draw
Line will be located in the metal pressure point on device gate region, source region and surface, drain region and has been connected with the electrode the inner on lead frame or pedestal
Come.
The many aberration by the two of equipment in prior art being identified grid region and the source region of DMOS device are known
In actual production process, not, find, during identifying, often occur source region and grid region are identified unclear problem, once
Identify unclear to source region and grid region, then the probability in the appearance connection error of follow-up wire bonding process is the biggest, thus
Cause product rejection.Application (Application No. 201110338198.0) before applicant, by, after forming tungsten plug, i.e. entering
Go after the cmp of tungsten, added process at quarter that ILD layer is returned, carved process through this time so that tungsten plug
Surface and ILD layer surface no longer flush, so that after being subsequently formed metal level and pressure welding point, source region position and position, grid region
The metallic region on surface is the most concordant, owing to the tungsten plug quantity in grid region and the tungsten plug quantity of source region are different, so that grid region
The section shape of the metallic region on surface is different from the section shape of the metallic region of area surface, and then makes surface, grid region
Metallic region is different from the reflecting power of the metallic region on surface, district so that when being identified, and identifies that light beam gets to product brilliant
After on sheet, there is aberration in grid region and source region such that it is able to clearly identified grid region and the source region of DMOS device by aberration, improves
The accuracy of follow-up wire bonding process.
Although applicant finds that above-mentioned technical scheme can clearly identify grid region and the source region of DMOS device in practice,
Improve the accuracy of follow-up wire bonding process, but owing to partial encapsulation equipment is old, use the Cu line that relative hardness is higher
During encapsulation, encapsulation back pull test occurs the phenomenon that cover layer peels off often, and in die area, last layer of metal is pulled up,
Source electrode and grid all have aluminum to peel off, routing regional metal defect time slight, serious time domain metal defect.
Summary of the invention
For solving above-mentioned technical problem, the invention provides DMOS device and the manufacture method thereof of a kind of improvement, overcome
Encapsulation back pull test occurs the product defects problem that cover layer peels off often.
For realizing above-mentioned purpose, the technical scheme is that
A kind of DMOS device making method, comprises the following steps:
1, providing substrate, described substrate includes source region and the inter-level dielectric ILD layer being positioned in described surfaces of active regions, its
In, the ILD layer being positioned in surfaces of active regions has tungsten plug, described ILD layer surface and described tungsten plug flush.
2, the ILD layer material of preset thickness is got rid of, so that ILD layer and described tungsten plug surface have difference in height.
Preferably, the process of the ILD layer material of preset thickness is got rid of specifically, use anisotropic etch process to remove
Fall the ILD layer material of preset thickness.
Preferably, described preset thickness is
Preferably, described preset thickness is
Further, the etching gas that described anisotropic etch process is used is CF4、CHF3And argon.
Particularly, CF in the etching gas that described anisotropic etch process is used4Volume flow be 16sccm-
20sccm, CHF3Volume flow be 60sccm-80sccm, the volume flow of argon is 80sccm-120sccm.
Preferably, the etch period of described anisotropic etch process is 60s.
3, using EKC solution 65-70 DEG C to clean 5-30min, the EKC solution of residual removed by isopropanol, and bath repeatedly, is got rid of
Dry.
4, there is the ILD layer of difference in height and described tungsten plug forming metal layer on surface, entering metal interconnection process, complete gold
After belonging to interconnection process, form pressure welding point on the metal layer, carry out low-temperature alloy technique, complete the manufacturing process of DMOS device.
The invention also discloses the DMOS device using said method to manufacture.
Compared with prior art, technique scheme has the advantage that
Technical scheme provided by the present invention, can not only clearly identify grid region and the source region of DMOS device, after improve
The accuracy of continuous wire bonding process, and by increasing EKC cleaning step, eliminate the polymer produced after ILD layer returns quarter,
Making ILD layer and metal interface more tight, the metal level being subsequently formed will not peel off after packaging.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to
Other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is the electron micrograph of the DMOS device profile after forming tungsten plug in prior art；
Electron micrograph when Fig. 2 is to be identified DMOS device of the prior art；
Fig. 3-Fig. 5 is the profile of DMOS device making method disclosed in the embodiment of the present invention
Fig. 6 is that comparative example of the present invention is provided without EKC cleaning gained DMOS device FIB figure；
Fig. 7 is the electron micrograph of the DMOS device that the method for the embodiment of the present invention is produced；
Electron micrograph when Fig. 8 is to be identified the DMOS device in the present embodiment.
Detailed description of the invention
As it is shown in figure 1, the electron micrograph that Fig. 1 is the chip profile after forming tungsten plug, as can be seen from the figure it is positioned at
The surface of the tungsten plug at source region position is substantially flush with ILD layer surface, surface, grid region, and therefore when being identified, the light of identification is got to
After chip surface, grid region and source region differ the least to the reflectance of light, thus cause being difficult to find out source region and grid by aberration
The difference in district, as in figure 2 it is shown, the electron micrograph of chip when Fig. 2 is to be identified, is difficult to distinguish source region and grid from figure
District.
Embodiments providing a kind of DMOS device and preparation method thereof, the method comprises the following steps:
1, providing substrate, described substrate includes source region and the inter-level dielectric ILD layer being positioned in described surfaces of active regions, its
In, the ILD layer being positioned in surfaces of active regions has tungsten plug, described ILD layer surface and described tungsten plug flush.
2, the ILD layer material of preset thickness is got rid of, so that ILD layer and described tungsten plug surface have difference in height.
Preferably, the process of the ILD layer material of preset thickness is got rid of specifically, use anisotropic etch process to remove
Fall the ILD layer material of preset thickness.
Preferably, described preset thickness is
Preferably, described preset thickness is
Further, the etching gas that described anisotropic etch process is used is CF4、CHF3And argon.
Particularly, CF in the etching gas that described anisotropic etch process is used4Volume flow be 16sccm-
20sccm, CHF3Volume flow be 60sccm-80sccm, the volume flow of argon is 80sccm-120sccm.
Preferably, the etch period of described anisotropic etch process is 60s.
3, using EKC solution 65-70 DEG C to clean 5-30min, the EKC solution of residual removed by isopropanol, and bath repeatedly, is got rid of
Dry.
4, there is the ILD layer of difference in height and described tungsten plug forming metal layer on surface, entering metal interconnection process, complete gold
After belonging to interconnection process, form pressure welding point on the metal layer, carry out low-temperature alloy technique, complete the manufacturing process of DMOS device.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of protection of the invention.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention is all right
Using other to be different from alternate manner described here to implement, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Secondly, the present invention combines schematic diagram and is described in detail, when describing the embodiment of the present invention in detail, for purposes of illustration only, table
Showing that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not at this
Limit the scope of protection of the invention.Additionally, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Embodiment
The profile of each step of DMOS device making method disclosed in the embodiment of the present invention as shown in Figure 3 and Figure 4, including with
Lower step:
Step 1: provide substrate, described substrate includes source region and the inter-level dielectric ILD being positioned in described surfaces of active regions
Layer 109, wherein, the ILD layer being positioned in surfaces of active regions has tungsten plug 108, described ILD layer 109 surface and described tungsten plug 108
Flush；
It should be noted that the substrate in the present embodiment can include that semiconductor element, such as monocrystalline, polycrystalline or amorphous are tied
The silicon of structure or SiGe (SiGe), it is also possible to include the semiconductor structure of mixing, such as carborundum, indium antimonide, lead telluride, arsenic
Indium, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or a combination thereof；Can also be silicon-on-insulator (SOI).Additionally, partly lead
Body substrate can also include the multiple structure of other material, such as epitaxial layer or buried layer.Can be with shape although there is described herein
Become several examples of the material of substrate, but spirit and the model of the present invention can be each fallen within as any material of semiconductor base
Enclose.
Concrete, as it is shown on figure 3, substrate described in the present embodiment includes following structure:
Body layer 101, described body layer includes drain region (not shown)；
The epitaxial layer 102 being positioned on body layer surface；
It is positioned at the well region 103 on epitaxial layer 102 surface and is positioned at the source region 104 of well region 103；
Being positioned at the grid region 106 on epitaxial layer 102 surface, grid region 106 is generally gate oxide by gate dielectric layer 105() bag
Enclosing, described active area includes source region 104 and grid region 106；
It is positioned at the field oxide 110 on epitaxial layer 102 surface, with isolating device；
The inter-level dielectric I LD layer 109 being positioned in described surfaces of active regions, wherein, is positioned at ILD layer 109 on area surface
There is tungsten plug 108, described ILD layer 109 surface and described tungsten plug 108 flush.
Wherein, the technical process forming above underlying structure is as follows:
Epitaxial layer 102 in the present embodiment can be outside N-type or the p-type using the once property growth in body layer of CVD technique
Prolonging layer, the thickness of epitaxial layer can determine according to the concrete application requirement of device.Body layer 101 in the present embodiment can be silicon lining
The end.
Afterwards, epitaxial layer grows one layer of thin oxide layer as implant blocking layer (not shown), implant blocking layer
Effect be during carrying out ion implanting, prevent foreign atom or ion from spreading out from the silicon of epitaxial layer；Described
Implant blocking layer can use CVD or thermal oxidation technology to be formed.
The process forming well region and source region in the present embodiment is as follows, first spin coating photoresist layer on implant blocking layer, in order to
Ensure exposure accuracy, also can form anti-reflecting layer (not shown) between photoresist layer and implant blocking layer, to reduce not
Necessary reflection；Use the mask plate with well region figure that photoresist layer is exposed afterwards, shape on described photoresist layer
Become well region pattern, afterwards with there is well region pattern photoresist layer be mask use ion implanting mode formed well region from
Sub-implanted layer, removes photoresist layer afterwards, uses thermal anneal process, advances the ion implanted layer of well region and activate injection
P-type or N-type impurity, formed well region, the thermal anneal process of this step may be used without rapid thermal anneal process.
Same, after forming well region, photoetching process can be used to form the photoetching agent pattern of source region, afterwards to have source region figure
The photoresist layer of case is mask, uses the mode of ion implanting to form the ion implanted layer of source region, uses thermal anneal process afterwards
Advance and activate the impurity of injection, form well region similar with the technical process of source region, repeat no more here.
After forming source region, using photoetching and etching technics, in well region surface, position, grid region forms groove, afterwards, at ditch
Rooved face use thermal oxidation technology formed gate dielectric layer 105, use CVD(chemical vapor deposition), PECVD(plasma chemistry
Vapor deposition), HDP(high-density plasma chemical vapor deposition) or PVD(physical vapor deposition) etc. technique, fill out in groove
Fill grid region material, remove the outer unnecessary grid region material of groove, make epi-layer surface flush, thus form grid region 106.
Wherein, gate dielectric layer material can be SrTiO3、HfO2、ZrO2, silicon oxide etc., the present embodiment is preferably oxidation
Silicon, grid region material can be gate polysilicon or metal, is preferably gate polysilicon in the present embodiment.
It should be noted that the process of grid region formed above and source region can be exchanged, grid region, rear shape i.e. can also be initially formed
Become source region, can be according to concrete technology situation depending on, this is not done too much restriction by the present embodiment.
After forming grid region 106 and source region 104, forming ILD layer 109 and tungsten plug 108, its process is as follows: have grid region and
ILD layer is formed on the substrate surface of source region, the method such as CVD, LPTEOS, PECVD or HDP in the present embodiment, form I LD layer, should
I LD layer material can be the one in silica glass (being called for short USG), boron-phosphorosilicate glass (being called for short BPSG) or combination.Afterwards, in order to protect
Demonstrate,prove the smooth of ILD layer surface, then use the methods such as CMP to be ground by described ILD layer material.
The process forming tungsten plug 108 is: form through hole in the ILD layer above source region 104 and grid region 106, concrete, can
Form through hole in using photoetching process and etching technics ILD layer above source region, use PVD at described through hole afterwards
Bottom and sidewall deposit a thin layer Titanium, to serve as the adhesive between tungsten and area material (generally silicon oxide), exist afterwards
The surface deposition titanium nitride of Titanium, to serve as the diffusion impervious layer of tungsten.After completing the deposit of Titanium and titanium nitride,
Typically need to carry out rapid thermal anneal step, so that Titanium and titanium nitride surface become smooth and uniform；
Afterwards, mode filler metal tungsten in described through hole of chemical vapor deposition can be used, use the side of CMP the most again
Method gets rid of the outer unnecessary tungsten of through hole, and to form tungsten plug 108, this CMP process can get rid of certain thickness ILD layer simultaneously
Material, this time after CMP, tungsten plug surface and ILD layer flush, as it is shown in figure 1, the ILD layer in the present embodiment and the thickness of tungsten plug
Depending on degree can be according to the concrete condition of device, the present embodiment does not do too much restriction.
Above-described " in epi-layer surface " refers to the region of the certain depth downwardly extended by epi-layer surface, this district
Territory belongs to a part for epitaxial layer；Described " on extension surface layer by layer " refers to that this region is not by epi-layer surface region upwards
Belong to epitaxial layer itself.
Step 2: as shown in Figure 4, gets rid of the ILD layer material of preset thickness, so that ILD layer 109 and described tungsten plug 108 table
Mask has difference in height.
The present embodiment can use the anisotropic etch process in dry etching get rid of the ILD layer material of preset thickness
Material, described preset thickness isI.e. ILD layer surface ratio tungsten plug surface is lowThickness
Degree, it is preferred that described preset thickness is
Concrete, the etching gas that described anisotropic etch process is used includes CF4、CHF3And argon, wherein, CF4
Volume flow be 16sccm-20sccm, CHF3Volume flow be 60sccm-80sccm, the volume flow of argon is
80sccm-120sccm, the etch period of described anisotropic etch process is 60s.
Step 3: using EKC solution 65 DEG C to clean 30min, the EKC solution of residual removed by isopropanol, washes by water 10 times, dries.
The main component of EKC solution: azanol (HDA), 2-(2-amino ethoxy) ethanol (DGA), catechol
(Catechol) and water, the polymer (polymer) that etching process stays can well be removed.
Step: 4: as it is shown in figure 5, have the I LD layer of difference in height and described tungsten plug forming metal layer on surface, enters gold
Belong to interconnection process, and at the drain region splash-proofing sputtering metal of described body layer, to form drain electrode (not shown)；
Described metal level can be the metal level of sandwich structure, concrete, first forms sediment on the I LD layer surface have tungsten plug
Long-pending Titanium, as the adhesive between tungsten plug and the metal forming electrode, deposits aluminium copper, finally afterwards on Titanium
Depositing titanium nitride on aluminum-copper alloy layer, above-mentioned three-layer metal thin film is referred to as sandwich structure.Generally, use physics more
The mode of vapor deposition forms each metal level of sandwich structure.
Carry out photoetching and the etch step of sandwich structure metal level afterwards, remove the metal level material outside source region and grid region
Material, to form grid on described grid region, forms source electrode in described source region.After performing etching, typically need to carry out in diffusion
Heating in stove, to reduce contact resistance, period also can be passed through nitrogen, to ensure the safety of process of heating.
After completing metal interconnection process, form pressure welding point on the metal layer；
Forming passivation layer on layer on surface of metal, described passivation layer covers other metal layer region in addition to pressure welding point；
Carry out low-temperature alloy technique, complete the manufacturing process of DMOS device.
Comparative example
1, providing substrate, described substrate includes source region and the inter-level dielectric ILD layer being positioned in described surfaces of active regions, its
In, the ILD layer being positioned in surfaces of active regions has tungsten plug, described ILD layer surface and described tungsten plug flush.
2, the ILD layer material of described substrate preset thickness is got rid of, so that ILD layer and described tungsten plug surface have height
Difference.
3, there is the ILD layer of difference in height and described tungsten plug forming metal layer on surface, entering metal interconnection process, complete gold
After belonging to interconnection process, form pressure welding point on the metal layer, carry out low-temperature alloy technique, complete the manufacturing process of DMOS device.
This comparative example is to lack the step for that EKC cleans relative to embodiment difference, can from Fig. 6 FIB picture
Peeling in the middle of aluminum layer is clearly.
In the embodiment of the present invention after forming tungsten plug, carry out back ILD layer carving so that tungsten plug surface and ILD layer surface are not
Flush again, so that after being subsequently formed metal level and pressure welding point, the metallic region of source region position and grid region portion faces is also
It is the most concordant, as it is shown in figure 5, the metallic region of i.e. grid region and area surface becomes uneven, due to the tungsten plug number in grid region
Measuring different from the tungsten plug quantity of source region, in the present embodiment, the tungsten plug quantity in grid region is less than the tungsten plug quantity of source region, so that grid
The section shape of the metallic region 111 on surface, district is different from the section shape of the metallic region 112 of area surface, and then makes grid
The metallic region 111 on surface, district is different from the reflecting power of the metallic region 112 of area surface so that when being identified, and knows
After other light beam is got on product wafer, there is aberration in grid region and source region, can clearly be identified the grid of DMOS device by aberration
District and source region, improve the accuracy of follow-up wire bonding process.
Wire bonding process described in the present embodiment can use the works such as thermocompression bonding, ultrasonic bond, Thermosonic-bonding
Skill, the lead-in wire wherein used can be aluminum steel, copper cash or gold thread etc., and subsequent encapsulating process is not specifically limited by the present embodiment.
Another embodiment of the present invention discloses the DMOS device that a kind of method used described in above example makes, specifically
, this DMOS device includes: active area and the inter-level dielectric ILD layer being positioned in described surfaces of active regions, wherein, is positioned at source region table
There is in ILD layer on face tungsten plug, ILD layer and tungsten plug surface there is difference in height.
As it is shown in fig. 7, be that the DMOS device using the method for the embodiment of the present invention to produce is after time quarter carrying out ILD
Microphotograph, is as can be seen from the figure positioned at the reflecting power of the metallic region on surface, grid region and the metallic region on surface, district not
With, therefore when being identified, after the light of identification gets to chip surface, grid region and source region there will be aberration, such that it is able to pass through
Aberration identification source region and grid region, as shown in Figure 8, electron microscopic when Fig. 8 is to be identified the DMOS device in the present embodiment
Photo, is easy to tell source region 1 and grid region 2 from figure.
By increasing EKC cleaning step, eliminate the polymer produced after ILD layer returns quarter, make ILD layer with metal interface more
Adding closely, the metal level being subsequently formed will not peel off after packaging.
In this specification, various piece uses the mode gone forward one by one to describe, and what each some importance illustrated is and other parts
Difference, between various piece, identical similar portion sees mutually.Described above to the disclosed embodiments, makes
Professional and technical personnel in the field are capable of or use the present invention.To the multiple amendment of these embodiments professional skill to this area
Will be apparent from for art personnel, generic principles defined herein can be without departing from the spirit or scope of the present invention
In the case of, realize in other embodiments.Therefore, the present invention is not intended to be limited to embodiment illustrated herein, and is intended to
Meet the widest scope consistent with principles disclosed herein and features of novelty.
Claims (7)
1. the manufacture method of a DMOS device, it is characterised in that including:
A, offer substrate, described substrate includes source region and the inter-level dielectric ILD layer being positioned in described surfaces of active regions, is positioned at and has
There is in ILD layer on area surface tungsten plug, described ILD layer surface and described tungsten plug flush；
B, get rid of the ILD layer material of preset thickness, so that ILD layer and described tungsten plug surface have difference in height；
C, employing EKC solution, clean 5-30min under conditions of 65-70 DEG C, uses isopropanol to remove the EKC solution of residual, rushes
Water repeatedly, dries；
D, there is the ILD layer of difference in height and described tungsten plug forming metal layer on surface, entering metal interconnection process, complete metal mutual
Even after process, form pressure welding point on the metal layer, carry out low-temperature alloy technique, complete the manufacturing process of DMOS device.
The manufacture method of DMOS device the most according to claim 1, it is characterised in that: step b is got rid of preset thickness
The process of ILD layer material specifically, use anisotropic etch process to get rid of the ILD layer material of preset thickness.
The manufacture method of DMOS device the most according to claim 1 and 2, it is characterised in that: described preset thickness is
The manufacture method of DMOS device the most according to claim 3, it is characterised in that: described preset thickness is
The manufacture method of DMOS device the most according to claim 2, it is characterised in that: described anisotropic etch process institute
The etching gas used is CF4、CHF3And argon.
The manufacture method of DMOS device the most according to claim 5, it is characterised in that: described anisotropic etch process institute
CF in the etching gas used4Volume flow be 16sccm-20sccm, CHF3Volume flow be 60sccm-80sccm, argon
The volume flow of gas is 80sccm-120sccm.
The manufacture method of DMOS device the most according to claim 2, it is characterised in that: described anisotropic etch process
Etch period is 60s.
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| CN201210465871.1A CN103824776B (en) | 2012-11-16 | 2012-11-16 | DMOS device and manufacture method thereof |
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|---|---|---|---|
| CN201210465871.1A CN103824776B (en) | 2012-11-16 | 2012-11-16 | DMOS device and manufacture method thereof |
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| CN102054775A (en) * | 2009-11-04 | 2011-05-11 | 无锡华润上华半导体有限公司 | Method for manufacturing semiconductor structure |
| CN102237297A (en) * | 2010-04-29 | 2011-11-09 | 武汉新芯集成电路制造有限公司 | Manufacturing method and planarization process of metal interconnection structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102054775A (en) * | 2009-11-04 | 2011-05-11 | 无锡华润上华半导体有限公司 | Method for manufacturing semiconductor structure |
| CN102237297A (en) * | 2010-04-29 | 2011-11-09 | 武汉新芯集成电路制造有限公司 | Manufacturing method and planarization process of metal interconnection structure |
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