CN102810477B - Semiconductor device and method for forming same - Google Patents
Semiconductor device and method for forming same Download PDFInfo
- Publication number
- CN102810477B CN102810477B CN201110145354.1A CN201110145354A CN102810477B CN 102810477 B CN102810477 B CN 102810477B CN 201110145354 A CN201110145354 A CN 201110145354A CN 102810477 B CN102810477 B CN 102810477B
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- interlayer dielectric
- layer
- metal
- metal gates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a semiconductor device and a method for forming the same. The semiconductor device comprises a substrate, a first interlayer dielectric layer, a metal grid, side walls, a second interlayer dielectric layer and a conductive plug, wherein the first interlayer dielectric layer is positioned on the substrate; the metal grid is positioned on the substrate and is formed in the first interlayer dielectric layer; the side walls are positioned on the substrate and are arranged on two sides of the metal grid; the second interlayer dielectric layer is positioned on the first interlayer dielectric layer and covers the metal grid and the side walls; the conductive plug is positioned in the second interlayer dielectric layer; and a protecting layer is arranged between the metal grid and the second interlayer dielectric layer and is communicated with the conductive plug. The phenomenon that the surface conductivity of the metal grid becomes poor so that the resistance of the conductive plug connected with the metal grid is reduced is effectively prevented, and the reliability and the electrical property of the semiconductor device are improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to semiconductor device comprising metal gates and forming method thereof.
Background technology
Along with improving constantly of semiconductor device integrated level, the reduction of technology node, traditional gate dielectric layer is constantly thinning, and transistor leakage amount increases thereupon, causes the problems such as semiconductor device power wastage.For solving the problem, prior art provides a kind of solution metal gates being substituted polysilicon gate.Wherein, " post tensioned unbonded prestressed concrete (gate last) " technique is the main technique forming metal gates.
In US Patent No. 6664195, provide a kind of " post tensioned unbonded prestressed concrete " technique that uses form the semiconductor device method comprising metal gates, comprise: Semiconductor substrate is provided, described Semiconductor substrate is formed with alternative gate structure and is positioned at the first interlayer dielectric layer described Semiconductor substrate covering described alternative gate structure; Using described alternative gate structure as stop-layer, CMP (Chemical Mechanical Polishing) process is carried out to described first interlayer dielectric layer; Groove is formed after removing described alternative gate structure; In described groove, metal is filled, to form metal gate electrode layer by PVD method; With chemical mechanical milling method (CMP) abrasive metal gate electrode layer to exposing the first interlayer dielectric layer, form metal gates; The second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the second interlayer dielectric layer covering metal grid; In the second interlayer dielectric layer, form the conductive plunger running through its thickness, described conductive plunger and metal gates are electrically connected.
Find in practical application, in the semiconductor device formed by technique scheme, metal gates top is easily oxidized, causes metal gates surface conductance performance to be deteriorated, and then the conductive plunger resistance be connected with metal gates is improved.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor device comprising metal gates and forming method thereof, prevents metal gates surface oxidized.
For solving the problem, the formation method of a kind of semiconductor device of the present invention, comprising: provide substrate, forms replacement gate structure at described substrate surface, replacement gate structure both sides are formed with side wall, described substrate are also formed with the first interlayer dielectric layer flushed with replacement gate structural top; With the first interlayer dielectric layer for mask, remove replacement gate structure, form groove; After channel bottom forms gate dielectric layer, on the first interlayer dielectric layer, form metal level, and described metal level fills full groove; Grinding metal layer, to after exposing the first interlayer dielectric layer, crosses grinding metal layer, and form metal gates, the height of described metal gates is lower than the first interlayer dielectric layer; Protective layer is formed on the first interlayer dielectric layer and metal gates; Grinding protection layer is to exposing the first interlayer dielectric layer; After first interlayer dielectric layer and protective layer are formed the second interlayer dielectric layer, in described second interlayer dielectric layer, form the conductive plunger running through its thickness, described conductive plunger is communicated with protective layer.
The present invention also provides a kind of semiconductor device; comprise: substrate; be positioned at the first interlayer dielectric layer on substrate; to be positioned on substrate and to be formed at the metal gates of the first interlayer dielectric layer; to be positioned on substrate and side wall in metal gates both sides, to be positioned at the second interlayer dielectric layer of covering metal grid and side wall on the first interlayer dielectric layer, to be positioned at the conductive plunger of the second interlayer dielectric layer; have protective layer between described metal gates and the second interlayer dielectric layer, described protective layer is communicated with conductive plunger.
Compared with prior art; the present invention has the following advantages: technical solution of the present invention forms protective layer on metal gates; oxygen in the process of follow-up formation second interlayer dielectric layer is avoided to be oxidized metal gates surface; metal gates surface conductance performance is effectively prevented to be deteriorated; and then the follow-up conductive plunger resistance be connected with metal gates is reduced, improve reliability and the electrical property of semiconductor device.
Further; adopt TiN or Ti or Ta or TaN as protective layer; both oxygen in the process of follow-up formation second interlayer dielectric layer can have been avoided to be oxidized metal gates surface; that can not reduce again with subsequent conductive connector is in electrical contact; ensure that the resistivity of conductive plunger, improve the electrical property of semiconductor device.
Accompanying drawing explanation
Fig. 1 is that the present invention forms the semiconductor device embodiment schematic flow sheet comprising metal gates;
Fig. 2 to Figure 10 is the example structure schematic diagram that the present invention forms the semiconductor device comprising metal gates.
Embodiment
Learnt by background technology, the reliability comprising the semiconductor device of metal gates obtained by prior art is poor.
The present inventor finds through research, the reliability of semiconductor device is poor is cause because the resistance value of metal gates is too high, when research finds to deposit formation the second interlayer dielectric layer on the first interlayer dielectric layer and metal gates further again, oxygen passes into and is easy to make metal gates surface oxidized, cause metal gates surface conductance performance to be deteriorated, and then the conductive plunger resistance be connected with metal gates is improved.
For solving the problem, the invention provides the semiconductor device embodiment that a kind of formation comprises metal gates, idiographic flow is as follows: perform step S11, substrate is provided, replacement gate structure is formed at described substrate surface, replacement gate structure both sides are formed with side wall, described substrate are also formed with the first interlayer dielectric layer flushed with replacement gate structural top; Perform step S12, with the first interlayer dielectric layer for mask, remove replacement gate structure, form groove; Perform step S13, after channel bottom forms gate dielectric layer, on the first interlayer dielectric layer, form metal level, and described metal level fills full groove; Perform step S14, grinding metal layer, to after exposing the first interlayer dielectric layer, crosses grinding metal layer, and form metal gates, the height of described metal gates is lower than the first interlayer dielectric layer; Perform step S15, on the first interlayer dielectric layer and metal gates, form protective layer; Perform step S16, grinding protection layer is to exposing the first interlayer dielectric layer; Perform step S17, after the first interlayer dielectric layer and protective layer are formed the second interlayer dielectric layer, in described second interlayer dielectric layer, form the conductive plunger running through its thickness, described conductive plunger is communicated with protective layer.
Based on the semiconductor device that above-mentioned execution mode is formed, comprising: substrate; Be positioned at the first interlayer dielectric layer on substrate; To be positioned on substrate and to be formed at the metal gates of the first interlayer dielectric layer; To be positioned on substrate and side wall in metal gates both sides, described side wall is positioned at the first interlayer dielectric layer; Be positioned at the protective layer on metal gates, described protective layer top flushes with dielectric layer surface between ground floor; To be positioned on the first interlayer dielectric layer and the second interlayer dielectric layer of protective mulch and side wall; Be positioned at the conductive plunger of the second interlayer dielectric layer, described conductive plunger is communicated with protective layer.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 2 to Figure 10 is the example structure schematic diagram that the present invention forms the transistor comprising metal gates.As shown in Figure 2, Semiconductor substrate 100 is provided; Be formed with isolated area 112 and the active area between isolated area in described Semiconductor substrate 100, wherein isolated area 112 can be shallow trench isolation from, also can be LOCOS isolation; The Semiconductor substrate 100 of active area is formed alternative gate dielectric layer 101 and alternative gate electrode layer 102 successively, described alternative gate dielectric layer 101 and alternative gate electrode layer 102 form replacement gate structure, concrete formation alternative gate electrode layer 102 technique is as follows: form alternative gate dielectric layer 101 on a semiconductor substrate 100, alternative gate dielectric layer 101 forms polysilicon layer, forms photoresist layer on the polysilicon layer; Exposure imaging is carried out to photoresist layer, forms gate patterns; With patterned photo glue-line for mask, etches polycrystalline silicon layer and alternative gate dielectric layer 101 are to exposing Semiconductor substrate 100.
In the present embodiment, described Semiconductor substrate 100 can be selected from the silicon (SOI) on silicon base, insulating barrier or can also be other material, the III-V such as such as GaAs.
In the present embodiment, the material of described alternative gate dielectric layer 101 can be silica or oxide-nitride-oxide, and the method forming alternative gate dielectric layer 101 is thermal oxidation method or chemical vapour deposition technique; Along with the reduction of technology node, in order to obtain enough thin alternative gate dielectric layer 101, thermal oxidation method oxide-semiconductor substrate 100 is usually adopted to be formed.
In the present embodiment, described polysilicon layer can adopt boiler tube depositing operation to be formed, and its deposit thickness determines the height of alternative gate electrode layer 102, the height of the metal gates of also i.e. follow-up formation.
As shown in Figure 3, with alternative gate electrode layer 102 for mask, the injection of shallow doped region is carried out to described Semiconductor substrate 100, form lightly doped drain 104.For nmos device, injection be N-shaped ion; For PMOS device, injection be p-type ion.Afterwards, described Semiconductor substrate 100 is heat-treated, the injection ion in lightly doped drain 104 is occurred longitudinally and horizontal even diffusion.
In the present embodiment, described Technology for Heating Processing can adopt rapid thermal annealing, pulse annealing or laser annealing.The Technology for Heating Processing of this step can be carried out together with the annealing process after making source/drain and being complete.
Except the present embodiment, some technique can not form lightly doped drain 104, and directly forms source/drain.
Continue with reference to figure 3, at described replacement gate structure both sides formation side wall 106, form described side wall 106 technique and can adopt existing deposition and etching technics, the material forming described side wall 106 can select silicon nitride or silicon dioxide or both combinations.
As shown in Figure 4, with alternative gate electrode layer 102 and side wall 106 for mask, carry out heavily doped region injection to described Semiconductor substrate 100, form source electrode 108 and drain electrode 108, the degree of depth of described source electrode 108 and drain electrode 108 is deeper than lightly doped drain 104.After injection ion, described Semiconductor substrate 100 is heat-treated, make source electrode 108 and the injection ion in drain electrode 108 that even diffusion that is longitudinal and transverse direction occur.
In the present embodiment, in formation PMOS transistor region, what inject in Semiconductor substrate 100 is p-type ion, as boron ion etc.
In the present embodiment, at formation nmos transistor region, what inject in Semiconductor substrate 100 is N-shaped ion, as phosphonium ion or arsenic ion etc.
In the present embodiment, described Technology for Heating Processing can adopt rapid thermal annealing, pulse annealing or laser annealing.
With reference to figure 5, described Semiconductor substrate 100 deposits the first interlayer dielectric layer 113, described first interlayer dielectric layer 113 covers described replacement gate structure and side wall 106; Adopt chemical mechanical milling method planarization first interlayer dielectric layer 113 to exposing replacement gate structural top.
In the present embodiment, the material of described first interlayer dielectric layer 113 is silica or silicon oxynitride or tetraethoxysilane etc.
As shown in Figure 6, with the first interlayer dielectric layer 113 for mask, remove alternative gate electrode layer and alternative gate dielectric layer by dry etching method or wet etching method etching, form groove.
In another example of the present embodiment, if the employing of described alternative gate dielectric layer 101 is high-g value, then can not be etched removal, remaines in the Semiconductor substrate in groove.
Continue with reference to figure 6, the Semiconductor substrate 100 in described groove forms gate dielectric layer 114.
In the present embodiment, described gate dielectric layer 114 is the gate dielectric layer of metal gate structure, as embodiment, high K dielectric can be adopted as the gate dielectric layer of metal gates, and described high K dielectric can be the one such as hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc.
After forming described gate dielectric layer 114, can also carry out other process to described gate dielectric layer 114, such as annealing process, to improve the quality of gate dielectric layer 114.
As shown in Figure 7, on the first interlayer dielectric layer 113, form metal level with chemical vapour deposition technique, and metal level is filled full groove.Then, with chemical mechanical milling method grinding metal layer to exposing the first interlayer dielectric layer 113; Continuation chemical mechanical milling method carried out grinding to metal level, made the height of metal level lower than first interlayer dielectric layer 113 surface 0 ~ 20nm, formed metal gates 115, and described metal gates 115 forms metal gate structure with gate dielectric layer 114.
In the present embodiment, the material of described metal level is Al.
As shown in Figure 8, metal gates 115 forms protective layer 116, the surface of described protective layer 116 flushes with the surface of the first interlayer dielectric layer 113.Concrete formation method is as follows: on the first interlayer dielectric layer 113 and metal gates 115, form protective layer with physical vaporous deposition or chemical vapour deposition technique; By chemical mechanical milling method grinding protection layer 116 to exposing the first interlayer dielectric layer 113; After grinding protection layer 116.
In the present embodiment, the material of described protective layer 116 is TiN or Ti or Ta or TaN, and thickness is 1 ~ 15nm.
In the present embodiment; cross grinding protection layer 116; make the height loss of the first interlayer dielectric layer 113 be 0 ~ 5nm, with guarantee the upper surface of protective layer 116 lower than or be parallel to the surface of the first interlayer dielectric layer 113, the thickness finally staying the protective layer 116 above metal gates is about 1 ~ 15nm.
In the present embodiment; adopt TiN or Ti or Ta or TaN as protective layer 116; both oxygen in the process of follow-up formation second interlayer dielectric layer can have been avoided to be oxidized metal gates 115 surface; that can not reduce again with subsequent conductive connector is in electrical contact; ensure that the resistivity of conductive plunger, improve the electrical property of semiconductor device.
As shown in Figure 9, the first interlayer dielectric layer 113 and protective layer 116 form the second interlayer dielectric layer 118.
In the present embodiment, the material of described second interlayer dielectric layer 118 is silica or silicon oxynitride or tetraethoxysilane etc.The method forming described second interlayer dielectric layer 118 is chemical vapour deposition technique.
In the present embodiment; in the process of formation second interlayer dielectric layer 118; characteristic due to the second interlayer dielectric layer 118 determines and needs to use oxygen in formation process; adopt TiN or Ti or Ta or TaN to protect metal gates 115 surface not oxidized as protective layer 116, ensure that the electrical property of metal gates.
As shown in Figure 10, form the first conductive plunger 120a running through its thickness in the second interlayer dielectric layer 118, described first conductive plunger 120a is electrically connected by protective layer 116 and metal gates 115; In the first interlayer dielectric layer 113 and the second interlayer dielectric layer 118, form the second conductive plunger 120b running through its thickness, described second conductive plunger 120b and source/drain 108 are electrically connected.
Based on the semiconductor device that above-described embodiment is formed, comprising: Semiconductor substrate 100; Isolated area 112, is positioned at Semiconductor substrate 100, for the isolation between active area; Gate dielectric layer 114, is positioned in Semiconductor substrate 100, and described gate dielectric layer 114 is high K dielectric; Metal gates 115, is positioned on gate dielectric layer 114; Protective layer 116, is positioned on metal gates 115, is oxidized metal gates 115 surface for avoiding oxygen in the process of follow-up formation second interlayer dielectric layer; Side wall 106, is positioned at gate dielectric layer 114, metal gates 115 and protective layer 116 both sides; First interlayer dielectric layer 113, to be positioned in Semiconductor substrate 100 and to flush with protective layer 116 surface; Second interlayer dielectric layer 118 is positioned on the first interlayer dielectric layer 113 and protective layer 116; First conductive plunger 120a, runs through the thickness of the second interlayer dielectric layer 118 and contacts with protective layer 116, and by protective layer 116 and metal gates 115 electrical communication; Second conductive plunger 120b, run through the second interlayer dielectric layer 118 and the first interlayer dielectric layer 113 thickness and with source/drain 108 electrical communication.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (7)
1. a formation method for semiconductor device, is characterized in that, comprising:
There is provided substrate, form replacement gate structure at described substrate surface, replacement gate structure both sides are formed with side wall, described substrate are also formed with the first interlayer dielectric layer flushed with replacement gate structural top;
With the first interlayer dielectric layer for mask, remove replacement gate structure, form groove;
After channel bottom forms gate dielectric layer, on the first interlayer dielectric layer, form metal level, and described metal level fills full groove;
Grinding metal layer, to after exposing the first interlayer dielectric layer, crosses grinding metal layer, forms metal gates, and the height of described metal gates upper surface is lower than the surface 0 ~ 20nm of the first interlayer dielectric layer;
Protective layer is formed on the first interlayer dielectric layer and metal gates;
Grinding protection layer is to exposing the first interlayer dielectric layer, and after grinding, the described protective layer thickness be positioned on metal gates is 1 ~ 15nm;
After first interlayer dielectric layer and protective layer are formed the second interlayer dielectric layer, in described second interlayer dielectric layer, form the conductive plunger running through its thickness, described conductive plunger is communicated with protective layer.
2. formation method according to claim 1, is characterized in that, the material of described protective layer is TiN or Ti or Ta or TaN.
3. formation method according to claim 1, is characterized in that, the method forming described protective layer is physical vaporous deposition or chemical vapour deposition technique.
4. formation method according to claim 1, is characterized in that, the material of described metal level is aluminium.
5. formation method according to claim 4, is characterized in that, the method forming described metal level is chemical vapour deposition technique.
6. formation method according to claim 1, is characterized in that, the method that grinding metal layer, protective layer adopt is chemical mechanical milling method.
7. formation method according to claim 1, is characterized in that, after grinding protection layer, also comprises step: cross grinding protection layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110145354.1A CN102810477B (en) | 2011-05-31 | 2011-05-31 | Semiconductor device and method for forming same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110145354.1A CN102810477B (en) | 2011-05-31 | 2011-05-31 | Semiconductor device and method for forming same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102810477A CN102810477A (en) | 2012-12-05 |
| CN102810477B true CN102810477B (en) | 2015-04-01 |
Family
ID=47234157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110145354.1A Active CN102810477B (en) | 2011-05-31 | 2011-05-31 | Semiconductor device and method for forming same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102810477B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582277A (en) * | 2020-12-08 | 2021-03-30 | 武汉新芯集成电路制造有限公司 | Semiconductor device processing method and semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1450600A (en) * | 2002-04-10 | 2003-10-22 | 台湾积体电路制造股份有限公司 | Method for mfg of double grid structure |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6933227B2 (en) * | 2003-10-23 | 2005-08-23 | Freescale Semiconductor, Inc. | Semiconductor device and method of forming the same |
| US7338888B2 (en) * | 2004-03-26 | 2008-03-04 | Texas Instruments Incorporated | Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same |
| US8053849B2 (en) * | 2005-11-09 | 2011-11-08 | Advanced Micro Devices, Inc. | Replacement metal gate transistors with reduced gate oxide leakage |
| US8120114B2 (en) * | 2006-12-27 | 2012-02-21 | Intel Corporation | Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate |
-
2011
- 2011-05-31 CN CN201110145354.1A patent/CN102810477B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1450600A (en) * | 2002-04-10 | 2003-10-22 | 台湾积体电路制造股份有限公司 | Method for mfg of double grid structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102810477A (en) | 2012-12-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI578446B (en) | Non-volatile memory array with concurrently formed low and high voltage logic devices | |
| US9281368B1 (en) | Split-gate trench power MOSFET with protected shield oxide | |
| US7838946B2 (en) | Method for fabricating semiconductor structure and structure of static random access memory | |
| US9024389B2 (en) | Borderless contact for ultra-thin body devices | |
| US8836031B2 (en) | Electrical isolation structures for ultra-thin semiconductor-on-insulator devices | |
| US8673755B2 (en) | Semiconductor device having metal gate and manufacturing method thereof | |
| CN103545183B (en) | Cmos device and preparation method thereof | |
| US9583640B1 (en) | Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure | |
| CN102769017A (en) | Semiconductor device and method of manufacturing the same | |
| CN102487010B (en) | Method for forming metal grid and MOS (Metal Oxide Semiconductor) transistor | |
| US20160211250A1 (en) | Semiconductor substrate arrangement, a semiconductor device, and a method for processing a semiconductor substrate | |
| JP4320405B2 (en) | Semiconductor device and manufacturing method thereof | |
| TWI647844B (en) | Semiconductor device and method of manufacturing the same | |
| CN107403721B (en) | Method for manufacturing power metal oxide semiconductor field effect transistor | |
| KR20030023718A (en) | Manufacture of trench-gate semiconductor devices | |
| TW201714284A (en) | Semiconductor structure and manufacturing method thereof | |
| CN101924110B (en) | SOI (Silicon On Insulator) transistor structure of body contact and preparation method thereof | |
| TW201725612A (en) | Semiconductor device and method of forming the same | |
| KR100809338B1 (en) | Semiconductor device and method of fabricating the same | |
| CN104681490A (en) | Forming method of CMOS (complementary metal-oxide-semiconductor) transistor | |
| CN102810477B (en) | Semiconductor device and method for forming same | |
| KR100791331B1 (en) | Nonvolatile memory device and method for fabricating the same | |
| CN103390583B (en) | Semiconductor integrated device and preparation method thereof | |
| CN102856178B (en) | The formation method of metal gates and MOS transistor | |
| CN102800577B (en) | Methods for forming metal gate and metal oxide semiconductor (MOS) transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |