CN103390583B - Semiconductor integrated device and preparation method thereof - Google Patents
Semiconductor integrated device and preparation method thereof Download PDFInfo
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- CN103390583B CN103390583B CN201210141118.7A CN201210141118A CN103390583B CN 103390583 B CN103390583 B CN 103390583B CN 201210141118 A CN201210141118 A CN 201210141118A CN 103390583 B CN103390583 B CN 103390583B
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Abstract
The embodiment of the invention discloses a kind of semiconductor integrated device and preparation method thereof, the method comprises: provide substrate, and this substrate includes source region and isolated area, resistance form layer and sacrifice layer; Remove part sacrificial layer material and resistance and form layer material, at the pseudo-grid of formation and resistance, pseudo-grid comprise partial ohmic and form layer material and sacrificial layer material, and resistance only comprises partial ohmic and forms layer material, and the apparent height of resistance is lower than the apparent height of pseudo-grid; Form first medium layer; Planarization first medium layer, only exposes pseudo-grid surface; Form metal gate opening; Fill metal gate opening, obtain metal gates.The embodiment of the present invention arranges sacrifice layer on the surface by forming layer at resistance, remove the sacrifice layer above resistance afterwards, and retain the sacrifice layer of pseudo-gate region, make the height of height higher than resistive surface on pseudo-grid surface, avoid being damaged to resistive surface in subsequent planarization process, the resistance of resistance is met design requirement, improves the yield of semiconductor integrated device.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of semiconductor integrated device and preparation method thereof.
Background technology
Along with improving constantly of semiconductor device integrated level, often need polytype device to integrate to make, as polysilicon resistance and MOS device are made in same technical process, and, along with the reduction of semiconductor process techniques node, tradition adopts material to be the gate dielectric layer of silicon dioxide and material to be the MOS device of the gate electrode layer of polysilicon to occur, and electrical leakage quantity increases and the problem such as gate electrode layer loss, for solving this problem, propose in prior art and adopt hafnium to replace silicon dioxide to make gate dielectric layer, adopt metal material for polysilicon to make gate electrode layer and (be called for short high-K metal gate, HKMG), following appearance the integrated device manufacture craft that polysilicon resistance and the MOS device adopting HKMG technique to make integrate is also become the present focus studied.
In US Patent No. 6406956, provide semiconductor device of a kind of integrated polysilicon resistance and high-K metal gate and preparation method thereof, the method flow chart as shown in Figure 1, comprising:
Step S101: substrate is provided, described substrate includes source region and isolated area, the pseudo-grid be positioned in described surfaces of active regions, the polysilicon resistance be positioned on described isolated area surface, and described polysilicon resistance and pseudo-grid are formed simultaneously; Step S102: form first medium layer on described substrate surface, described first medium layer is dielectric layer (ILD0) between level 0, and planarization ILD0, expose pseudo-grid and polysilicon resistance surface;
Step S103: form protective layer on the surface at polysilicon resistance;
Step S104: with described protective layer for mask, removes described pseudo-grid, forms groove;
Step S105: remove the protective layer on described polysilicon resistance surface;
Step S106: form high-K dielectric layer at described channel bottom, the high-K dielectric layer in groove fills metal material until metal material fills up described groove, to form metal gate layers, now metal gate layers covers the surface of polysilicon resistance simultaneously;
Step S107: adopt cmp (CMP) technique grinding and polishing metal gate layers surface, expose ILD0 material, namely define metal gates and polysilicon resistance simultaneously.
Find in actual production process, the semiconductor integrated device yield adopting said method to produce is often undesirable, and especially the resistance of polysilicon resistance is often lower than design load.
Summary of the invention
For solving the problems of the technologies described above, embodiments provide a kind of semiconductor integrated device and preparation method thereof, by polysilicon resistance and high-K metal gate integrated, and the resistance of polysilicon resistance meets designing requirement, improves the yield of semiconductor integrated device.
For solving the problem, embodiments provide following technical scheme:
A kind of semiconductor integrated device manufacture method, comprising:
Substrate is provided, described substrate includes source region and isolated area, the resistance on the described active area of covering and isolated area surface forms layer and cover the sacrifice layer that described resistance forms layer surface;
Remove part sacrificial layer material and resistance formation layer material, to form pseudo-grid in described surfaces of active regions, resistance is formed on the surface in described isolated area, wherein, described pseudo-grid comprise the sacrificial layer material that partial ohmic forms layer material and is positioned on its surface, described resistance only comprises partial ohmic and forms layer material, and the apparent height of described resistance is lower than the apparent height of described pseudo-grid;
Form first medium layer on the surface of the substrate;
First medium layer described in planarization, only exposes described pseudo-grid surface;
With described first medium layer for mask, the resistance removing pseudo-gate region forms layer material and sacrificial layer material, in described first medium layer surface, form metal gate opening;
Fill described metal gate opening, obtain metal gates.
Preferably, the thickness of described metal gates is 1.1 times-2 times of described resistance thickness.
Preferably, the material of described sacrifice layer is the material of etching selection ratio higher than 10:1 described resistance being formed to layer material.
Preferably, described resistance forms the polysilicon that layer material is polysilicon or doping, and the cambial thickness of described resistance is
Preferably, described sacrificial layer material is the SiGe of SiGe or doping.
Preferably, the thickness of described sacrifice layer is
Preferably, the described process forming first medium layer is on the surface of the substrate specially:
Form barrier layer on the surface of the substrate, described barrier layer covers described pseudo-grid surface and resistive surface;
Described barrier layer surface is formed described first medium layer.
Preferably, the material on described barrier layer is silicon nitride, and the thickness on described barrier layer is
Preferably, described substrate also comprises the cushion oxide layer be positioned in described surfaces of active regions, and described liner oxidation layer material is silica.
Preferably, describedly in described surfaces of active regions, form pseudo-grid, the process forming resistance in described isolated area is on the surface specially:
Adopt photoetching process in described sacrificial layer surface, form first photosensitive layer with isolated area figure, there is the first photosensitive layer of isolated area figure for mask, remove the whole sacrificial layer material on described isolated area surface, the resistance exposed on described isolated area surface forms layer material;
Remove described first photosensitive layer;
Adopt photoetching process to form layer with described resistance in sacrificial layer surface and form second photosensitive layer with pseudo-gate figure and resistance pattern on the surface, there is the second photosensitive layer of pseudo-gate figure and resistance pattern for mask, remove the sacrificial layer material and resistance formation layer material that are not covered by described second photosensitive layer, expose described liner oxidation layer material, form described pseudo-grid and resistance.
Preferably, the technique of described removal part sacrificial layer material is: plasma etching industrial or chemical reagent etching technics.
Preferably, the gas adopted in described plasma etching industrial is hot HCl gas.
Preferably, the described metal gate opening of described filling, the process obtaining metal gates is:
Gate dielectric layer is formed in the bottom of described metal gate opening and sidewall;
In metal gate opening, fill grid metal, until fill up described metal gate opening, form grid metal level;
Remove the grid metal layer material on described first medium layer surface, described first medium layer surface is flushed, obtains described metal gates.
Preferably, described gate dielectric layer material is hafnium.
Preferably, described gate dielectric layer material is at least one in hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum and lead niobate zinc.
Preferably, described grid metal level is single coating or multilayer lamination structure.
Preferably, when described grid metal level is single coating, described grid metal layer material is aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, tungsten silicide, tungsten titanium, titanium nitride, nitrogenize thallium, carbonization thallium, nickel platinum or nitrogen silication thallium.
Preferably, when described grid metal level is multilayer lamination structure, described grid metal level comprises:
Be positioned at the work-function layer on described gate dielectric layer surface;
Be positioned at the second gate metal level on described work-function layer surface, described second gate metal layer material can be aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, tungsten silicide, tungsten titanium, titanium nitride, nitrogenize thallium, carbonization thallium, nickel platinum or nitrogen silication thallium.
Preferably, described work-function layer material is titanium, titanium nitride, thallium, titanium aluminium or nitrogenize thallium.
Preferably, before the described first medium of formation on the surface of the substrate layer, also comprise:
Source and leakage is formed in the surfaces of active regions of described pseudo-grid both sides.
Preferably, after forming described metal gates, also comprise:
Second dielectric layer is formed on the surface at described first medium layer;
Form the multiple through holes running through described second dielectric layer and first medium layer, expose source and drain material, metal gate material and resistance two ends;
In described through hole, fill connecting line metal, form connector, to be electrically connected described semiconductor integrated device.
The embodiment of the invention also discloses a kind of semiconductor integrated device, this device comprises:
Isolated area and active area;
Be positioned at the resistance on described isolated area surface;
Be positioned at the metal gates in described surfaces of active regions;
Wherein, the apparent height of described resistance is lower than the apparent height of described metal gates, and described resistance and described active area are electrically insulated.
Preferably, described metal gates comprises:
Be positioned at the gate dielectric layer in described surfaces of active regions;
Be positioned at the grid metal level on described gate dielectric layer surface, described grid metal level is single coating or multilayer lamination structure.
Preferably, described active area comprises source and leakage, and this semiconductor integrated device also comprises:
Cover described resistive surface, source and drain surface and the barrier layer of metal gates sidewall;
Only cover the first medium layer of described barrier layer surface;
Cover the second dielectric layer of described first medium layer surface and described metal gates upper surface;
Run through multiple connectors of described second dielectric layer and first medium layer, described multiple connector is electrically connected with source and drain, metal gates and resistance two ends respectively.
Compared with prior art, technique scheme has the following advantages:
The technical scheme that the embodiment of the present invention provides, by forming layer at resistance, sacrifice layer is set on the surface, remove the sacrifice layer above resistance afterwards, and retain the sacrifice layer of pseudo-gate region, thus make the height of height higher than resistive surface on pseudo-grid surface, thus avoid be damaged to resistive surface in the planarization of follow-up first medium layer and Metal gate layer planarization process, the resistance of resistance is met design requirement, improves the yield of semiconductor integrated device.
Further, the resistance in the embodiment of the present invention and pseudo-grid are formed in same photoetching and etching process, thus enable resistance manufacturing process integrated with the manufacturing process of high-K metal gate.
Further, sacrificial layer material in the present embodiment is the material high to the etching selection ratio of described resistance formation layer material, thus reduce the injury when removing sacrificial layer material, resistance being formed to layer surface, and then ensure that resistive surface has good smoothness and evenness.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the manufacturing method of semiconductor device schematic flow sheet of integrated polysilicon resistance and high-K metal gate in prior art;
The flow chart of the semiconductor integrated device manufacture method that Fig. 2 provides for the embodiment of the present invention;
The profile of each step of semiconductor integrated device manufacture method that Fig. 3-12 provides for the embodiment of the present invention.
Embodiment
Just as described in the background section, the yield of the integrated-semiconductor device adopting method of the prior art to produce often can not meet the demands, the resistance of especially integrated with high-K metal gate polysilicon resistance is often lower than design load, inventor studies discovery, occur that the basic reason of this problem is, the apparent height of polysilicon resistance structure of the prior art is identical with the apparent height of pseudo-grid structure, metal gate layers is being carried out in the process of cmp, due to first medium layer material will be exposed, namely polysilicon resistance surface to be exposed, thus cause in the CMP process of gate electrode layer, inevitably damage polysilicon resistance surface, namely part polysilicon resistor material can be removed, thus cause the resistance of polysilicon resistance to be less than design load.
On basis based on above-mentioned research, embodiments provide a kind of semiconductor foundation device and preparation method thereof, the method comprises the following steps:
Substrate is provided, described substrate includes source region and isolated area, the resistance on the described active area of covering and isolated area surface forms layer and cover the sacrifice layer that described resistance forms layer surface;
Remove part sacrificial layer material and resistance formation layer material, to form pseudo-grid in described surfaces of active regions, resistance is formed on the surface in described isolated area, wherein, described pseudo-grid comprise the sacrificial layer material that partial ohmic forms layer material and is positioned on its surface, described resistance only comprises partial ohmic and forms layer material, and the apparent height of described resistance is lower than the apparent height of described pseudo-grid;
Form first medium layer on the surface of the substrate, this first medium layer covers described pseudo-grid surface, resistive surface and the active area except described pseudo-grid and resistance and isolated area surface;
First medium layer described in planarization, only exposes described pseudo-grid surface;
With described first medium layer for mask, the resistance removing pseudo-gate region forms layer material and sacrificial layer material, in described first medium layer surface, form metal gate opening;
Fill described metal gate opening, obtain metal gates.
The technical scheme that the embodiment of the present invention provides, by forming layer at resistance, sacrifice layer is set on the surface, remove the sacrifice layer above resistance afterwards, and retain the sacrifice layer of pseudo-gate region, thus make the height of height higher than resistive surface on pseudo-grid surface, avoid the injury of subsequent planarization process to resistance, the resistance of resistance is met design requirement, improves the yield of semiconductor integrated device.
It is more than the core concept of the application, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Embodiments provide a kind of semiconductor integrated device manufacture method, as shown in Figure 2, the profile of each step is as shown in Fig. 3-Figure 12, and the method comprises the following steps for its flow chart:
Step S201: as shown in Figure 3, provides substrate, and described substrate includes source region 101, isolated area 102, covers the resistance formation layer 104 on described active area 101 and isolated area 102 surface and cover the sacrifice layer 105 on described resistance formation layer 104 surface;
Preferably, isolated area 102 in the present embodiment can be shallow-trench isolation (STI) district, concrete, described substrate can also comprise, semi-conductive substrate, be generally silicon substrate (not shown), be positioned at the epitaxial loayer (not shown) in described surface of silicon, be positioned at N-type and the P type trap zone of described epi-layer surface, described isolated area 102 is between N-type well region and P type trap zone, or in the surface of N-type and P type trap zone, to isolate different devices.Active area 101 in the present embodiment is and is isolated district 102 and keeps apart region for making active device, and certainly, also can have doping particle in this active area 101, namely this active area 101 can be N-type or P type trap zone.
Can adopt chemical vapor deposition (being called for short CVD) technique disposable growth N-type or P type epitaxial loayer on a silicon substrate in the present embodiment, the thickness of epitaxial loayer can require to determine according to the embody rule of device.Afterwards, adopt ion implantation technology to form N trap and P trap, before carrying out ion implantation, injection oxide layer can be formed on the surface at epitaxial loayer, to protect epitaxial loayer from staining, stoping the damage of ion implantation process to substrate, control the ion implantation degree of depth etc.
After formation N trap and P trap, first can form an isolating oxide layer on the surface at epitaxial loayer, layer of isolation oxide forms one first barrier layer (being generally silicon nitride layer), in epi-layer surface, forms STI shallow trench by photoetching process and etching technics afterwards.
It should be noted that, described " in epi-layer surface " refers to that this region does not belong to epitaxial loayer itself by epi-layer surface region upwards; Described " in epi-layer surface " refers to that this region belongs to a part for epitaxial loayer by the region of epi-layer surface to the certain depth of downward-extension, and all the other describe roughly the same.
Before carrying out sti oxide filling, also bottom STI shallow trench, trench liner oxide skin(coating) should be formed, to improve the interfacial characteristics between silicon substrate and trench fill oxide with sidewall.CVD technique can be adopted afterwards to carry out the filling of trench oxide; described trench liner oxide skin(coating) and trench oxide are generally silica; trench oxide unnecessary outside STI shallow trench is removed by chemico-mechanical polishing CMP after completing the filling of trench oxide; described substrate surface is flushed; obtain multiple shallow-trench isolation (STI) district; remove described first barrier layer afterwards again, described isolating oxide layer can protect active area to stain from chemistry in the process removing the first barrier layer.
After forming shallow trench isolation region, just there is not isolation oxidation layer material and the first barrier material on the surface in shallow trench isolation region, namely described isolating oxide layer only covers surface, active area 101.The concrete technology step forming shallow trench isolation region can refer to prior art, repeats no more here.
Substrate described in the present embodiment also can comprise the cushion oxide layer 103 between described active area 101 and resistance formation layer, described cushion oxide layer 103 material is silica, according to above description, described cushion oxide layer 103 is above-mentioned isolating oxide layer, certainly, described cushion oxide layer 103 can be also other oxide layer formed before follow-up formation resistance forms layer, as gate oxide, in order to reduce production process in the present embodiment, be preferably above-mentioned isolating oxide layer.
After forming described shallow trench isolation region (i.e. isolated area 102), CVD technique can be adopted to form resistance on the surface in described isolated area 102 and active area 101 and to form layer 104, form layer 104 at resistance and form sacrifice layer on the surface.
Resistance in the present embodiment forms the polysilicon that layer 104 material can be polysilicon or doping, and resistance forms the thickness of layer 104 for being preferably
within, be more preferably
along with the requirement of device miniaturization, the thickness of resistance also can be more and more less, as
within, and the method in the present embodiment also can meet the making requirement of device miniaturization, below will be described in detail this.
It should be noted that, substrate in the present embodiment can comprise semiconductor element, the silicon of such as monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe), also the semiconductor structure of mixing can be comprised, such as carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination; Also can be silicon-on-insulator (SOI).In addition, semiconductor base can also comprise other material, the sandwich construction of such as epitaxial loayer or oxygen buried layer.Although the foregoing describe several examples of the material that can form substrate, all the spirit and scope of the present invention can be fallen into as any material of semiconductor base.
Step S202: remove part sacrificial layer material and resistance formation layer material, to form pseudo-grid 106 in described surfaces of active regions, resistance 107 is formed on the surface in described isolated area 102, wherein, described pseudo-grid 106 comprise the sacrificial layer material that partial ohmic forms layer material and is positioned on its surface, described resistance 107 only comprises partial ohmic and forms layer material, and the apparent height of described resistance is lower than the apparent height of described pseudo-grid;
In other words, in this step, the resistance only retaining resistance region and pseudo-gate region forms layer material, and only retains the sacrificial layer material of pseudo-gate region, to make the apparent height of described resistance lower than the apparent height of described pseudo-grid.
This process is concrete as shown in Figure 4 and Figure 5, first, see Fig. 4, photoetching process can be adopted at described sacrifice layer 105 to form the first photosensitive layer (not shown) with isolated area figure on the surface, described first photosensitive layer is generally photoresist layer, as adopted the techniques such as e-beam direct write lithography, shown first photosensitive layer can be electron beam glue-line.
This process can be, first in sacrifice layer 105 surperficial spin coating photoresist layer (not shown), in order to ensure exposure accuracy, also can form anti-reflecting layer (not shown) between photoresist layer and sacrifice layer 105, to reduce unnecessary reflection, the mask plate with isolated area figure is adopted to expose photoresist layer afterwards, isolated area pattern is formed on the surface at described photoresist layer, there is the photoresist layer (i.e. the first photosensitive layer) of isolated area figure for mask after development, adopt the technique such as reactive ion etching (i.e. plasma etching or dry etching) or chemical reagent etching (wet etching), remove the whole sacrificial layer material on described isolated area 102 surface, the resistance exposed on described isolated area surface forms layer material (polysilicon), the methods such as chemical cleaning are adopted to remove photoresist layer (i.e. the first photosensitive layer) and anti-reflecting layer afterwards.
Afterwards, as shown in Figure 5, adopt photoetching process to form layer 104 with described resistance on the surface at described sacrifice layer 105 again and form the second photosensitive layer (not shown) with pseudo-gate figure and resistance pattern on the surface, there is the second photosensitive layer of pseudo-gate figure and resistance pattern for mask, adopt reactive ion etching or chemical reagent etching to remove and do not formed layer material by the sacrificial layer material of described second photosensitive layer covering and resistance, expose described cushion oxide layer 103 material, the methods such as chemical cleaning are adopted to remove the second photosensitive layer afterwards, form described pseudo-grid 106 and resistance 107.
Wherein, due to in longitudinal etching process of pseudo-grid, inevitably there will be lateral etching effect, namely in etching process, can damage pseudo-grid sidewall, therefore, the size of pseudo-gate figure described in the present embodiment can be a bit larger tham the size of the final pseudo-grid formed, to offset the injury of lateral etching to pseudo-grid sidewall, make the size of the pseudo-grid 106 finally obtained more accurate.
In addition, the sacrificial layer material above isolated area 102 is first removed in the present embodiment, retain the sacrificial layer material of active region, and non-immediate removes most sacrificial layer material, only retain the sacrificial layer material of pseudo-grid required size, make to be formed in pseudo-grid process in subsequent etching, the pseudo-gate figure that size is greater than actual pseudo-grid size can be formed, thus avoid lateral etching to the injury of pseudo-grid sidewall.
It should be noted that, in order to reach above-mentioned effect, in removal sacrificial layer material process, the width of the sacrificial layer material retained is greater than the actual size of pseudo-grid, the width limiting the sacrificial layer material retained is not needed to be specially how many, namely in the present embodiment remove sacrificial layer material time, being used for the dimension of picture done on the first photosensitive layer of mask only need be greater than the actual size of pseudo-grid, do not need to do strict restriction, only first remove sacrificial layer material above isolated area 102 for example to be described in the present embodiment, can not as the restriction to the present embodiment protection range.
In the present embodiment, the thickness of resistance 107 is as shown in label h in Fig. 5, width is as shown in label a in Fig. 5, the resistance of resistance is by the cambial doping content of resistance, doping type, and the size of resistance determines, the size of described resistance comprises at least one parameter in resistance thickness, width and area.
Wherein, removing sacrificial layer material in the present embodiment can be identical with the method for resistance formation layer material, also can be different, as removed sacrificial layer material chemical reagent etching technics, remove resistance and form layer material reactive ion etching, concrete mode can form layer material according to sacrificial layer material and resistance and determine.
It should be noted that, damage to form layer surface to resistance when reducing to remove the sacrificial layer material above isolated area in the present embodiment, to ensure that resistive surface has good smoothness and evenness, select during sacrificial layer material, to select the material high to the etching selection ratio of described resistance formation layer material, generally, sacrificial layer material forms the etching selection ratio of layer material higher than 10:1 to resistance, resistance in the present embodiment forms the polysilicon that layer 104 material is polysilicon or doping, accordingly, described sacrifice layer 105 material can be the SiGe of SiGe or doping, whether need to adulterate and doping type and concentration etc. can be determined according to the requirement of the cambial doping content of resistance and etching selection ratio.
In addition, based on above-mentioned material, preferably adopt plasma etching industrial to remove sacrificial layer material in the present embodiment, in plasma etching process, adopt the HCl gas of heating to remove sige material.Wherein, the selection of sacrificial layer thickness is determined primarily of the height of the thickness of metal gate dielectric layer needed for this semiconductor integrated device, the height of metal gate and resistance, namely the thickness of described sacrifice layer is the total height of metal gate dielectric layer and metal gate and the difference of resistance height, and in the present embodiment, the thickness of sacrifice layer is preferably
After forming pseudo-grid 106 and resistance 107, also comprise, formed in the surfaces of active regions of described pseudo-grid both sides, as shown in Figure 5.
The process forming source and drain can be, adopt photoetching process and ion implantation technology in surfaces of active regions, form lightly doped drain and (be called for short LDD, not shown), adopt CVD technique in surfaces of active regions, form side wall medium layer afterwards and (be generally silica, not shown), side wall medium layer is anti-carved, side wall is formed in pseudo-grid both sides, adopt photoetching process in described surfaces of active regions, form the photoresist layer with source and drain figure afterwards, and with the photoresist layer with source and drain figure for mask, ion implantation technology and annealing process is adopted in the surfaces of active regions of described pseudo-grid 107 both sides, to form source 109a and leak 109b.
In addition, it should be noted that, the injection process of described source and drain can be carried out (as mentioned above) after the pseudo-grid of formation, also can carrying out before the described resistance of formation forms layer, in order to reduce processing step, being preferably the former in the present embodiment.
Step S203: form first medium layer 110 on the surface of the substrate, in the present embodiment, first medium layer 110 can be dielectric layer between level 0, be called for short ILD0 layer, first medium layer 110 covers described pseudo-grid 106 surface, resistance 107 surface and the active area except described pseudo-grid 106 and resistance 107 and isolated area surface; In order to better ensure in ILD0 layer CMP process in the embodiment of the present invention, reduce the injury to resistive surface, simultaneously also in order to avoid the pseudo-grid surface of excessive damage, as shown in Figure 6, before the described first medium layer 110 of formation, also can form barrier layer 108 on the surface of the substrate, this barrier layer covers described pseudo-grid 106 surface, resistance 107 surface and the active area except described pseudo-grid 106 and resistance 107 and isolated area surface.This barrier layer 108 material is preferably silicon nitride, and thickness is preferably
the material of first medium layer 110 is silica, the silica of B doping or P doping or simultaneously mix the silica of B element and P element.
Concrete, the technique forming barrier layer 108 can for adopting PVD, CVD technique, and described CVD technique comprises PECVD(plasma chemical vapor deposition), LPTEOS or HDP(high-density plasma chemical vapor deposition) etc. method.
After forming barrier layer 108, the techniques such as CVD can be adopted to form described first medium layer 110 on the surface on barrier layer 108, as shown in Figure 7.
It should be noted that, in theory, in order to avoid damaging resistive surface in ILD0 layer CMP process in the present embodiment, as long as ensure that pseudo-grid surface and resistive surface have difference in height, because the pseudo-grid surface formed in above step is inevitable higher than resistive surface, therefore, in other embodiments of the present invention, also barrier layer 108 can not be set, in this case, after ILD0 layer CMP process terminates, at least to retain the part ILD0 layer material on resistive surface, and, generally, in order to expose pseudo-grid surface completely, crossing of suitable degree can be carried out with slower grinding and polishing speed in the CMP later stage of ILD0 layer to throw.
Step S204: as shown in Figure 8, first medium layer 110 described in planarization, i.e. ILD0 layer, only expose described pseudo-grid 106 surface, because resistance 107 surface formed in step S202 is lower than pseudo-grid 106 surface, therefore, in this planarization process, resistance 107 surface can not be exposed;
Concrete, CMP grinding and polishing ILD0 layer surface can be adopted, remove the barrier material on unnecessary ILD0 layer material and pseudo-grid surface, to expose the surface of pseudo-grid 106, if do not arrange barrier layer 108, can according to the time of CMP, carry out the grinding and polishing speed of control CMP, namely at CMP in earlier stage, speed can carry out the grinding and polishing of ILD0 layer material faster, when the CMP time more than a Preset Time time, start to reduce CMP grinding and polishing speed, namely the ILD0 layer material of pseudo-grid surface residual is removed with slower grinding and polishing speed, for ensureing to expose pseudo-grid surface completely, also can carry out throwing to the ILD0 layer on pseudo-grid surface, because CMP speed is now very slow, therefore throwing is crossed very little to the damage on pseudo-grid surface, and, because pseudo-grid surface is higher than resistive surface, therefore, can not need strictly to control the grinding and polishing time in mistake throwing process, as long as retain part first medium layer 110 material on resistance 107 surface, the injury to resistive surface can be avoided.
If be provided with barrier layer 108, then in the CMP process of ILD0 layer, first can carry out grinding and polishing with speed faster to ILD0 layer material, when grinding and polishing is to barrier layer surface, reduce the speed of CMP, namely with slower speed grinding and polishing barrier layer surface, until expose the surface of pseudo-grid 106.In like manner, for ensureing to expose pseudo-grid surface completely, also throwing can be carried out to the barrier layer on pseudo-grid surface, because CMP speed is now very slow, therefore throwing is crossed very little to the damage on pseudo-grid surface, further, because resistive surface is lower than pseudo-grid surface, and the stop on barrier layer 108 is had, and the material on pseudo-grid surface is different with barrier material, therefore substantially not needing to limit spending the throwing time, stopping to during barrier material as long as be set in the grinding and polishing of throwing process, and can not damage resistive surface yet.
In the present embodiment, material due to first medium layer 110 is silica, barrier layer 108 material is silicon nitride, select the lapping liquid of CMP to the technological parameter that silica and the Selection radio of silicon nitride are greater than 1 can ensure higher than pseudo-grid silicon nitride barrier and silica ILD0 layer can together be removed.
Concrete, the lapping liquid adopted in the process of barrier layer 108, CMP if having can with silica or cerium oxide for main component, and the planarization rate Selection radio of described lapping liquid to silica and silicon nitride is greater than 1.Wherein, the particle size of described silica abrasive liquid is 1 ~ 100nm, and the advantage of employing silica abrasive liquid is: active, the rear cleaning process of abrasive grains good dispersion, chemical property is easy to advantage; The particle size of described cerium oxide abrasive liquid is 10 ~ 20nm, adopts the advantage of cerium oxide abrasive liquid to be: have that polishing speed is high, material remove rate is high, the advantage less to the damage on polished surface.
Step S205: as shown in Figure 9, with described first medium layer 110 for mask, adopt dry etching or wet corrosion technique, the resistance removing described pseudo-grid 106 region forms layer material and sacrificial layer material, in described first medium layer surface, form metal gate opening 111;
When described resistance formation layer surface is provided with cushion oxide layer 103, in this step, also with first medium layer 110 for mask, dry etching or wet corrosion technique to be adopted, remove the liner oxidation layer material 103 in described pseudo-grid 106 region simultaneously.
In this step, described dry etching is plasma etching industrial, and when removing sacrificial layer material (i.e. SiGe), the gas of employing is hot HCl gas, when removing resistance formation layer material (i.e. polysilicon), the mixture of chlorine, helium, hydrogen bromide or helium and oxygen can be selected.The advantage of dry etching is adopted to be that anisotropy, selectivity are good and etching efficiency is high.
According to wet corrosion technique, tetramethyl ammonium hydroxide solution can be selected to remove resistance and form layer material, mass percent concentration is 2 ~ 4%, and temperature is 50 DEG C ~ 90 DEG C, corrosion rate is 100 ~ 3000 A/min of clocks, and the speed ratio of corrosion polysilicon and silica is greater than 100:1; Adopt the advantage of wet etching be easy and simple to handle, low for equipment requirements, be easy to produce in enormous quantities.
Step S206: fill described metal gate opening 111, obtain metal gates 114.
This process is specially, and as shown in Figure 10, the first medium layer that the techniques such as PVD or CVD have metal gate opening 111 can be adopted to form gate dielectric layer 112 on the surface, and described gate dielectric layer 112 covers bottom and the sidewall of described metal gate opening 111;
The techniques such as PVD or CVD can be adopted to be attached with in the metal gate opening of gate dielectric layer 112 in bottom and sidewall and to fill grid metal, until fill up described metal gate opening, form grid metal level 113;
As shown in figure 11, CMP can be adopted to remove gate dielectric layer material on described first medium layer surface and grid metal layer material, described first medium layer surface is flushed, obtains described metal gates 114.
Metal gates 114 described here comprises gate dielectric layer 112 after CMP and grid metal level 113, namely the thickness of metal gates 114 is the thickness sum of gate dielectric layer 112 after CMP and grid metal level 113, in theory, the thickness of metal gates 114 is the degree of depth of metal gate opening 111, but in actual production, owing to can cross throwing in CMP process, the thickness of metal gates 114 is generally slightly smaller than the degree of depth of metal gate opening 111.
The thickness of the described metal gates 114 in the present embodiment is 1.1 times-2 times of described resistance thickness, to avoid carrying out gate dielectric layer 112 and grid metal level 113 damaging resistance 107 surface in CMP process.
The material of gate dielectric layer 112 described in the present embodiment is hafnium, and described hafnium comprises at least one in hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum and lead niobate zinc.
Described grid metal level 113 in the present embodiment is single coating or multilayer lamination structure.
When described grid metal level 113 is single coating, described grid metal layer material is aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, tungsten silicide, tungsten titanium, titanium nitride, nitrogenize thallium, carbonization thallium, nickel platinum or nitrogen silication thallium.
When described grid metal level is multilayer lamination structure, described grid metal level 113 comprises:
Be positioned at the work-function layer (not shown) on described gate dielectric layer 112 surface, described work-function layer material can be titanium, titanium nitride, thallium, titanium aluminium or nitrogenize thallium;
Be positioned at the second gate metal level (not shown) on described work-function layer surface, described second gate metal layer material can be aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, tungsten silicide, tungsten titanium, titanium nitride, nitrogenize thallium, carbonization thallium, nickel platinum or nitrogen silication thallium.
In another embodiment of the present invention, after the described metal gates of formation, also need this semiconductor integrated device to be electrically connected with external devices, see Figure 12, this process is specially:
Second dielectric layer 115 is formed on the surface at described first medium layer 110, in the present embodiment, this second dielectric layer is the first interlayer dielectric layer, be called for short ILD1 layer, CVD technique specifically can be adopted to form second dielectric layer 115, also can carry out cmp to second dielectric layer 115 afterwards, remove unnecessary second medium layer material, second dielectric layer 115 surface is flushed;
Form the multiple through holes running through described second dielectric layer 115 and first medium layer 110, expose source and drain material, metal gate material and resistance two ends, photoetching process and etching technics specifically can be adopted to form described multiple through hole, and detailed process similarly to the prior art, repeats no more here;
Connecting line metal is filled in described through hole, form connector 116, to be electrically connected described semiconductor integrated device, drawn two lead ends of source electrode, drain electrode, metal gates and resistance by connector 116, the technique of filling connecting line metal in through hole also can with reference to prior art.
The material of second dielectric layer 115 described in the present embodiment is identical with first medium layer 110 material, can think the silica of silica, B doping or P doping or the silica of simultaneously adulterate B element and P element.
The embodiment of the present invention arranges sacrifice layer on the surface by forming layer at resistance, remove the sacrifice layer above resistance afterwards, and retain the sacrifice layer of pseudo-gate region, thus make the height of height higher than resistive surface on pseudo-grid surface, thus avoid be damaged to resistive surface in the planarization of follow-up first medium layer and Metal gate layer planarization process, the resistance of resistance is met design requirement, improves the yield of semiconductor integrated device.
Further, the resistance in the embodiment of the present invention and pseudo-grid are formed in same photoetching and etching process, thus enable resistance manufacturing process integrated with the manufacturing process of high-K metal gate.
Corresponding with said method, another embodiment of the present invention discloses the semiconductor integrated device adopting said method to produce, the MOS device adopting HKMG technique to produce and resistance are integrated, and the resistance of the resistance produced can meet design requirement, improve the yield of overall device.
The structure chart of this semiconductor integrated device can refer to Figure 12, comprising:
Active area 101, isolated area 102, the source 109a being positioned at surface, active area 101 and leakage 109b, in the present embodiment, isolated area 102 is shallow-trench isolation (STI) district;
Be positioned at the resistance 107 on described isolated area 102 surface, in the present embodiment, resistance 107 is preferably polysilicon resistance;
Be positioned at the metal gates 114 on surface, described active area 101;
Wherein, the apparent height of described resistance 107 is lower than the apparent height of described metal gates 114, and described resistance 107 is electrically insulated with described active area 109.
The semiconductor integrated device of the present embodiment is by making the height of height higher than resistive surface on pseudo-grid surface, the apparent height of the metal gates 114 namely in the present embodiment is higher than the apparent height of resistance 107, thus avoid be damaged to resistive surface in the planarization of follow-up first medium layer and Metal gate layer planarization process, the resistance of resistance is met design requirement, improves the yield of semiconductor integrated device.
Described metal gates 114 in the present embodiment comprises:
Be positioned at the gate dielectric layer 112 in described surfaces of active regions, described gate dielectric layer 112 material is hafnium;
Be positioned at the grid metal level 113 on described gate dielectric layer surface, described grid metal level 113 can be single coating or multilayer lamination structure, and the concrete structure of described grid metal level 113 and material, as described in embodiment of the method, repeat no more here.
In addition to the foregoing structure, this semiconductor integrated device also comprises:
Cover described resistance 107 surface, source 109a and leak 109b surface and the barrier layer 108 of metal gates 114 sidewall, namely do not covered by barrier layer 108 on the surface at metal gates 114, described barrier material is silicon nitride;
Only cover the first medium layer 110 of described barrier layer surface, the surface of i.e. described metal gates 114 is not covered by first medium layer, it should be noted that, barrier layer on resistance 107 surface can be coated with first medium layer material, also first medium layer material can not be covered, depend primarily on resistance 107 and the difference in height of metal gates 114 and the thickness on barrier layer, the present embodiment does not limit this;
Cover the second dielectric layer 115 of described first medium layer 110 surface and described metal gates 114 upper surface;
Run through multiple connectors 116 of described second dielectric layer 110 and first medium layer 115, to be electrically connected semiconductor device, described multiple connector is respectively with source 109a with leak 109b, metal gates 114 and resistance 107 two ends and be electrically connected, and connector described in the present embodiment is preferably tungsten plug.
In this specification, various piece adopts the mode of going forward one by one to describe, and what each some importance illustrated is the difference with other parts, between various piece identical similar portion mutually see.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to embodiment illustrated herein, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (21)
1. a semiconductor integrated device manufacture method, is characterized in that, comprising:
Substrate is provided, described substrate includes source region and isolated area, the resistance on the described active area of covering and isolated area surface forms layer and cover the sacrifice layer that described resistance forms layer surface;
Remove part sacrificial layer material and resistance formation layer material, to form pseudo-grid in described surfaces of active regions, resistance is formed on the surface in described isolated area, wherein, described pseudo-grid comprise the sacrificial layer material that partial ohmic forms layer material and is positioned on its surface, described resistance only comprises partial ohmic and forms layer material, and the upper level of described resistance is lower than the upper level of described pseudo-grid, and the lower surface of described resistance flushes with the lower surface of described pseudo-grid;
Form first medium layer on the surface of the substrate;
First medium layer described in planarization, only exposes described pseudo-grid surface;
With described first medium layer for mask, the resistance removing pseudo-gate region forms layer material and sacrificial layer material, in described first medium layer surface, form metal gate opening;
Fill described metal gate opening, obtain metal gates.
2. semiconductor integrated device manufacture method according to claim 1, is characterized in that, the thickness of described metal gates is 1.1 times-2 times of described resistance thickness.
3. semiconductor integrated device manufacture method according to claim 1, is characterized in that, the material of described sacrifice layer is the material of etching selection ratio higher than 10:1 described resistance being formed to layer material.
4. semiconductor integrated device manufacture method according to claim 3, is characterized in that, it is polysilicon that described resistance forms layer material, and the cambial thickness of described resistance is
5. semiconductor integrated device manufacture method according to claim 4, is characterized in that, described sacrificial layer material is SiGe.
6. semiconductor integrated device manufacture method according to claim 5, is characterized in that, the thickness of described sacrifice layer is
7. semiconductor integrated device manufacture method according to claim 1, is characterized in that, the described process forming first medium layer is on the surface of the substrate specially:
Form barrier layer on the surface of the substrate, described barrier layer covers described pseudo-grid surface and resistive surface;
Described barrier layer surface is formed described first medium layer.
8. semiconductor integrated device manufacture method according to claim 7, is characterized in that, the material on described barrier layer is silicon nitride, and the thickness on described barrier layer is
9. semiconductor integrated device manufacture method according to claim 1, is characterized in that, described substrate also comprises the cushion oxide layer be positioned in described surfaces of active regions, and described liner oxidation layer material is silica.
10. semiconductor integrated device manufacture method according to claim 9, is characterized in that, describedly in described surfaces of active regions, forms pseudo-grid, and the process forming resistance in described isolated area is on the surface specially:
Adopt photoetching process in described sacrificial layer surface, form first photosensitive layer with isolated area figure, there is the first photosensitive layer of isolated area figure for mask, remove the whole sacrificial layer material on described isolated area surface, the resistance exposed on described isolated area surface forms layer material;
Remove described first photosensitive layer;
Adopt photoetching process to form layer with described resistance in sacrificial layer surface and form second photosensitive layer with pseudo-gate figure and resistance pattern on the surface, there is the second photosensitive layer of pseudo-gate figure and resistance pattern for mask, remove the sacrificial layer material and resistance formation layer material that are not covered by described second photosensitive layer, expose described liner oxidation layer material, form described pseudo-grid and resistance.
The 11. semiconductor integrated device manufacture methods stated according to claim 5, is characterized in that, the technique of described removal part sacrificial layer material is: plasma etching industrial or chemical reagent etching technics.
12. semiconductor integrated device manufacture methods according to claim 11, is characterized in that, the gas adopted in described plasma etching industrial is hot HCl gas.
13. semiconductor integrated device manufacture methods according to claim 1, is characterized in that, the described metal gate opening of described filling, and the process obtaining metal gates is:
Gate dielectric layer is formed in the bottom of described metal gate opening and sidewall;
In metal gate opening, fill grid metal, until fill up described metal gate opening, form grid metal level;
Remove the grid metal layer material on described first medium layer surface, described first medium layer surface is flushed, obtains described metal gates.
14. semiconductor integrated device manufacture methods according to claim 13, is characterized in that, described gate dielectric layer material is hafnium.
15. semiconductor integrated device manufacture methods according to claim 14, it is characterized in that, described gate dielectric layer material is at least one in hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum and lead niobate zinc.
16. semiconductor integrated device manufacture methods according to claim 13, is characterized in that, described grid metal level is single coating or multilayer lamination structure.
17. semiconductor integrated device manufacture methods according to claim 16, it is characterized in that, when described grid metal level is single coating, described grid metal layer material is aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, tungsten silicide, tungsten titanium, titanium nitride, nitrogenize thallium, carbonization thallium, nickel platinum or nitrogen silication thallium.
18. semiconductor integrated device manufacture methods according to claim 16, is characterized in that, when described grid metal level is multilayer lamination structure, described grid metal level comprises:
Be positioned at the work-function layer on described gate dielectric layer surface;
Be positioned at the second gate metal level on described work-function layer surface, described second gate metal layer material can be aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, tungsten silicide, tungsten titanium, titanium nitride, nitrogenize thallium, carbonization thallium, nickel platinum or nitrogen silication thallium.
19. semiconductor integrated device manufacture methods according to claim 18, is characterized in that, described work-function layer material is titanium, titanium nitride, thallium, titanium aluminium or nitrogenize thallium.
20. semiconductor integrated device manufacture methods according to any one of claim 1-19, is characterized in that, described form first medium layer on the surface of the substrate before, also comprise:
Source and leakage is formed in the surfaces of active regions of described pseudo-grid both sides.
21. semiconductor integrated device manufacture methods according to claim 20, is characterized in that, after forming described metal gates, also comprise:
Second dielectric layer is formed on the surface at described first medium layer;
Form the multiple through holes running through described second dielectric layer and first medium layer, expose source and drain material, metal gate material and resistance two ends;
In described through hole, fill connecting line metal, form connector, to be electrically connected described semiconductor integrated device.
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