CN102044476B - Forming method of metal pattern - Google Patents
Forming method of metal pattern Download PDFInfo
- Publication number
- CN102044476B CN102044476B CN 200910197092 CN200910197092A CN102044476B CN 102044476 B CN102044476 B CN 102044476B CN 200910197092 CN200910197092 CN 200910197092 CN 200910197092 A CN200910197092 A CN 200910197092A CN 102044476 B CN102044476 B CN 102044476B
- Authority
- CN
- China
- Prior art keywords
- metal pattern
- formation method
- curing
- metal
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The invention provides a forming method of a metal pattern, comprising the following steps of supplying a semiconductor substrate; forming the metal pattern on the surface of the semiconductor substrate; baking the metal pattern; and cleaning the baked metal pattern. The invention improves the quality of the formed metal pattern.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method of metal pattern.
Background technology
In semiconductor fabrication process, usually need to form metal pattern, for example plain conductor and metal gasket in semiconductor device.Wherein plain conductor is used for being electrically connected to the device of same layer or different layers, and metal gasket is used for realizing the electrical connection of semiconductor device and external circuit.
The method that forms above-mentioned metal pattern comprises step: form metal level on semiconductor base, for example metal A l; Then under the mask layer protection, metal level is carried out etching, for example dry etching, remove unwanted metal level, and reservation will form the metal level of metal pattern; Then carry out cleaning step, the solution of etch residue and etching residue is washed.Be for example to disclose a kind of method that forms metal pattern in semiconductor device in the Chinese patent literature of " 20071000243.5 " in the patent No..
Along with dwindling of device size, it is more and more thinner that plain conductor becomes, and it is more and more less that the size of metal gasket also becomes, therefore the quality requirement of metal pattern is also more and more higher, if the edge of metal pattern by overetch, can make some places meticulous, will easily open circuit.
But utilize the phenomenon of the marginal existence overetch of the metal pattern that above-mentioned prior art forms, thereby make the edge quality of metal pattern bad.
Summary of the invention
The technical problem that the present invention solves is to provide a kind of formation method of metal pattern, thereby the quality of metal pattern is provided.
In order to address the above problem, the invention provides a kind of metal pattern, comprise step:
Semiconductor base is provided;
Form metal pattern at described semiconductor-based basal surface;
Described metal pattern is cured;
Metal pattern after described curing is cleaned.
Compared with prior art, the present invention mainly has the following advantages:
The present invention had increased baking step by improving the formation step of metal pattern before cleaning step, thereby reduced the over etching phenomenon of metal pattern, made the quality of metal pattern be improved.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other purpose of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Deliberately do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on illustrating purport of the present invention.
Fig. 1 is the flow chart of the formation method of metal pattern of the present invention;
Fig. 2 to Fig. 4 is the schematic diagram of formation method one embodiment of metal pattern of the present invention;
Fig. 5 is take light transmittance, Q-time and cures the time started as the three-dimension curved surface schematic diagram of coordinate.
Embodiment
By background technology as can be known, the prior art method that forms metal pattern in semiconductor device comprises the following steps: to form metal level, for example metal Al layer on semiconductor base; Then under the mask layer protection, metal level is carried out etching, for example dry etching, remove unwanted metal level, and reservation will form the metal level of metal pattern; Then carry out cleaning step, the solution of etch residue and etching residue is washed.
Along with dwindling of device size, it is more and more thinner that plain conductor becomes, and it is more and more less that the size of metal gasket also becomes, therefore the quality requirement of metal pattern is also more and more higher, if the edge of metal pattern by overetch, can make some places meticulous, will easily open circuit.But utilize marginal existence overetch existing of the metal pattern that above-mentioned prior art forms, thereby make the edge quality of metal pattern bad.
The present inventor thinks through after a large amount of experimental studies, the problems referred to above are because etch step and the semiconductor base that will have a metal level are taken away between the step of cleaning between meeting (Q-time) at regular intervals, the cleaning of namely can the interval certain hour after etch step again semiconductor base being taken away.Having the etching thing after etch step is attached on metal level, because etching gas generally includes the gas of acid ion, be attached to the acid group on metal level, for example chloride ion and airborne moisture content are in conjunction with generating acid solution, in addition the residue that generates of etching for example aluminium chloride and airborne moisture content in conjunction with generating acid solution, thereby after described etching, be attached to the further corroding metal layer of layer on surface of metal.
For example following reaction:
AlCL
x+ H
2O → Al (OH)
3+ HCL, wherein x is natural number.
Because be coated with mask layer on the upper surface of metal level in etch step, so acid solution can be attached on the sidewall of metal pattern, thereby makes sidewall be further corroded into irregular figure, therefore makes the second-rate of metal pattern.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the present invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that should comprise in addition, length, width and the degree of depth in actual fabrication.
Fig. 1 is the flow chart of the formation method of metal pattern of the present invention, and Fig. 2 to Fig. 4 is the formation method schematic diagram of metal pattern of the present invention.Below in conjunction with Fig. 1 to Fig. 4, metal pattern formation method of the present invention is described, metal pattern formation method of the present invention comprises the following steps:
S10: described semiconductor base is provided.
With reference to figure 2, semiconductor base 100 can be silicon or the SiGe (SiGe) of monocrystalline, polycrystalline or non crystalline structure, can be also silicon-on-insulator (SOI), can also comprise other material, for example indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.Can also be substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate, epitaxial silicon substrate, section processes or the substrate that is not patterned in addition.
S20: at described semiconductor base 100 surface formation metal patterns.
With reference to figure 3, concrete, can utilize method well known to those skilled in the art, for example utilize in the present embodiment physical vapour deposition (PVD) metal level 110.Described formation concrete technology condition comprises: physical vapor deposition target material material is aluminium, reaction temperature is 250 degrees centigrade to 500 degrees centigrade, chamber pressure is 10 millitorr to 18 millitorrs, direct current power is 10000 watts to 40000 watts, argon flow amount is that 2 standard cubic centimeters per minute are to 20 standard cubic centimeters per minute, until form the metal level of desired thickness, for example 0.2um.
In other embodiments, the material of described formation metal level 110 can be selected from silver, chromium, molybdenum, nickel, palladium, platinum, titanium or tantalum, perhaps is selected from the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium or tantalum.
Then, with reference to figure 4, can first can utilize spin coating (spin on) technique coating photomask layer on semiconductor base, shown in photomask layer can comprise: photoresist layer, the thickness of photoresist layer can for
Then carry out etching, concrete dry etching can be plasma etch process, selects inductively coupled plasma type etching apparatus, utilizes Cl
2, BCL
2And CHF
3Mist, carry out etching.
For step S20, in another embodiment, for example the metal pattern of copper material makes, can also for: first form insulating barrier on semiconductor base 100, then the etching insulating barrier, form groove in insulating barrier, then depositing metal layers is until groove is completely filled.Then, adopt chemico-mechanical polishing or etching technics, remove unnecessary metal level, form metal pattern.For example the design parameter of concrete described chemico-mechanical polishing is: select SiO
2Polishing fluid, the pH value of polishing fluid is 10 to 11.5, the flow of polishing fluid be 120 milliliters per minute to 170 milliliters per minute, in glossing, the rotating speed of grinding pad is 65 rpms to 80 rpms, the rotating speed of grinding head is 55 rpms to 70 rpms, and the pressure of glossing is 200 handkerchief to 350 handkerchiefs.
S30: described metal pattern 120 is cured.
Concrete, can utilize method well known to those skilled in the art, for example can adopt convection furnace, online and manual heat dish etc., stoving temperature is 150 ℃-200 ℃ in the present embodiment.Described light transmittance is the Area Ratio of the semiconductor base at the area of opening of mask pattern and its place, because the position of the larger etching of light transmittance is larger, therefore the situation of etching post-etching is also more serious, because the situation to front time (Q-time) the longer etching post-etching of cleaning step after etch step is also more serious, and the etching thing that the inventor finds to be attached on the metal pattern sidewall through overtesting is not to corrode once suction, but through just beginning after a while.The time started of therefore curing can be determined according to light transmittance and Q-time.For example can be in advance carry out experiment test according to light transmittance, Q-time and time started of curing, obtain take light transmittance, Q-time and cure the time started as the three-dimension curved surface of coordinate, for example as shown in Figure 5, wherein S1, S2, S3, S4 represent the value of light transmittance.Thereby when carrying out baking step, the time started that obtains curing according to light transmittance, Q-time and the three-dimension curved surface that obtains in advance, then utilize this time started of curing to cure, the concrete time started of curing also can be relevant with stoving temperature, for example concrete stoving temperature is 150 ℃-200 ℃, curing the time started is 120s after etch step is completed, and light transmittance is that 80%, Q-time is 4 hours.The concrete time of curing can decide according to the degree of surperficial water evaporates, and its result is cured the moisture content of metal pattern surface totally.
S40: the metal pattern after described curing is cleaned.
Concrete, described cleaning utilizes deionized water.
Usually do not cure after etching in the prior art, but directly clean, but because technique is limit, must (O-time) just can clean through after a while after etching, therefore increased in the present invention by a step baking step between cleaning, cure and to evaporate the etching solvent, thereby make the phenomenon that can not exist residual solvent that metal pattern is further corroded, therefore just reduced like this overetch to metal pattern, make the etching edge better effects if of metal pattern, metal pattern is more near Ideal graph, and quality is higher.
The above is only preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (8)
1. the formation method of a metal pattern, is characterized in that, comprises step:
Semiconductor base is provided;
Form metal pattern at described semiconductor-based basal surface;
Described metal pattern is cured, so that the evaporation of the moisture on metal pattern is clean, described temperature of curing is 150 ℃-200 ℃, the definite method that begins to carry out the time of described baking step is: test according to time and the time started of curing before the cleaning step after light transmittance, etch step in advance, obtaining after light transmittance, the etch step time before cleaning step and the time started of curing is the three-dimension curved surface of coordinate, according to time and the described three-dimension curved surface before the cleaning step after light transmittance and etch step, determine the described time started of curing;
Metal pattern after described curing is cleaned.
2. the formation method of metal pattern according to claim 1, is characterized in that, the material of described metal pattern is metallic aluminium.
3. the formation method of metal pattern according to claim 1, it is characterized in that, at first the step of described formation metal pattern comprises utilizes the described metal level of dry etching at the semiconductor base forming metal layer on surface, form metal pattern, described dry etching is plasma etching.
4. the formation method of metal pattern according to claim 3, is characterized in that, the gas source of plasma etching comprises CL
2, BCL
3And CHF
3
5. the formation method of metal pattern according to claim 1, is characterized in that, described light transmittance is 80%, and the time after described etch step before the cleaning step is 4 hours, and the described time started of curing is 120s after etch step is completed.
6. the formation method of metal pattern according to claim 1, is characterized in that, described cleaning utilizes deionized water.
7. the formation method of metal pattern according to claim 1, is characterized in that, described metal pattern is plain conductor.
8. the formation method of metal pattern according to claim 1, is characterized in that, described metal pattern is metal gasket.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910197092 CN102044476B (en) | 2009-10-13 | 2009-10-13 | Forming method of metal pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910197092 CN102044476B (en) | 2009-10-13 | 2009-10-13 | Forming method of metal pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102044476A CN102044476A (en) | 2011-05-04 |
| CN102044476B true CN102044476B (en) | 2013-06-19 |
Family
ID=43910488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910197092 Expired - Fee Related CN102044476B (en) | 2009-10-13 | 2009-10-13 | Forming method of metal pattern |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102044476B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1170777A (en) * | 1996-05-30 | 1998-01-21 | 三星电子株式会社 | Apparatus and method of preventing residual reaction gas from dry etcher |
| CN1681086A (en) * | 2004-04-06 | 2005-10-12 | 三菱电机株式会社 | Resist pattern formation method, patterned substrate manufacturing method, and display device making method |
| KR100744005B1 (en) * | 2006-06-29 | 2007-07-30 | 주식회사 하이닉스반도체 | Method for forming of metal pattern in semiconductor device |
| CN101126894A (en) * | 2006-08-16 | 2008-02-20 | 三星电子株式会社 | Systems and methods for manufacturing wire grid polarizers |
-
2009
- 2009-10-13 CN CN 200910197092 patent/CN102044476B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1170777A (en) * | 1996-05-30 | 1998-01-21 | 三星电子株式会社 | Apparatus and method of preventing residual reaction gas from dry etcher |
| CN1681086A (en) * | 2004-04-06 | 2005-10-12 | 三菱电机株式会社 | Resist pattern formation method, patterned substrate manufacturing method, and display device making method |
| KR100744005B1 (en) * | 2006-06-29 | 2007-07-30 | 주식회사 하이닉스반도체 | Method for forming of metal pattern in semiconductor device |
| CN101097866A (en) * | 2006-06-29 | 2008-01-02 | 海力士半导体有限公司 | Method for forming metal pattern in semiconductor device |
| CN101126894A (en) * | 2006-08-16 | 2008-02-20 | 三星电子株式会社 | Systems and methods for manufacturing wire grid polarizers |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102044476A (en) | 2011-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI419349B (en) | Method for producing a silicon solar cell with a back-etched emitter as well as a corresponding solar cell | |
| TWI466232B (en) | Method for processing semiconductor structure and device based on the same | |
| CN103337475B (en) | The synchronous etching technics of double structure contact hole | |
| US10204933B2 (en) | Thin film transistor and method for manufacturing the same, and display panel | |
| CN110416076B (en) | Method and device for improving metal line fracture | |
| CN106058003B (en) | A method of promoting LED chip brightness | |
| CN107768490B (en) | Preparation method for optimizing performance of GaN-based L ED chip | |
| CN106129063B (en) | Thin-film transistor array base-plate and its manufacturing method | |
| CN103050438B (en) | The lithographic method of contact hole | |
| CN106571295A (en) | Method for manufacturing a patterned sapphire substrate | |
| TW201420812A (en) | Etchant composition and method of forming metal pattern and method of manufacturing an array substrate | |
| CN106684031A (en) | Manufacturing method of semiconductor structure | |
| CN108389952B (en) | It is a kind of without electric leakage MESA Cutting Road 3D through-hole superstructure LED chip and preparation method thereof | |
| CN101728317B (en) | Forming methods of conducting structure and pad | |
| CN102044476B (en) | Forming method of metal pattern | |
| CN110148654A (en) | A kind of light-emitting diode chip for backlight unit and its manufacturing method | |
| CN100461476C (en) | Production method for type N ohm contact electrode of GaN based power type LED | |
| CN102800587B (en) | Process for producing schottky diode | |
| KR100220933B1 (en) | Forming method for metal wiring of semiconductor device | |
| TWI427378B (en) | Laminated structure and the use of its electrical circuit electrode | |
| CN107507869A (en) | Low-temperature polysilicon film transistor and preparation method thereof and array base palte | |
| CN107527802A (en) | Groove type double-layer grid MOS film build methods | |
| CN102446814A (en) | Forming method for dual mosaic structure | |
| CN109103140A (en) | A kind of production method of array substrate | |
| CN102290349A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121113 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20121113 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130619 Termination date: 20191013 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |