CN102034855B - Silicon-germanium heterojunction bipolar transistor and manufacturing method thereof - Google Patents
Silicon-germanium heterojunction bipolar transistor and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a silicon-germanium HBT (heterojunction bipolar transistor) which comprises a T-shaped emitter, an inner base region and an outer base region, wherein the maximum value of the vertical distance between the upper surface of the T-shaped emitter and the upper surface of the inner base region is a, and the minimum value is b, the difference between a and b is c, and c is less than or equal to 5% of b or is less than or equal to 500; the outer base region comprises a silicon-germanium alloy layer and a polycrystalline silicon layer above the silicon-germanium alloy layer; and the inner base region comprises a silicon-germanium alloy layer. The invention also discloses a manufacturing method of the silicon-germanium HBT. In the silicon-germanium HBT and the manufacturing method thereof, the T-shaped emitter has extremely smooth upper surface; and the emitter can be made of polycrystalline silicon or high k metal materials, and is compatible with the CMOS (complementary metal oxide semiconductor) metal gate process. Besides, the invention reduces the diffusion of outer-base region impurities to the substrate, thereby reducing the parasitic capacitance and being beneficial to improving the overall working frequency of the device.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly relate to a kind of silicon-silicon-germanium heterojunction bipolar transistor.
Background technology
Heterojunction bipolar transistor (HBT) is by the emitter region of broad stopband, the base that heavy doping, band gap are less and the collector region material of broad stopband are formed, as the emitter region by silicon constitute, the base is by sige alloy (being abbreviated as silicon-germanium usually) constitutes, collector region is made of silicon silicon-germanium HBT.The base band gap of silicon-germanium HBT is littler than the emitter region, and compatible fully with silicon integrated circuit technology, be fit to make high integration, high-speed, with the semiconductor device of Si semiconductor manufacturing process highly compatible, be widely used in the high-frequency high-speed communications field.
See also Fig. 1, this is the structural representation of a kind of existing silicon-germanium HBT.Dark separator 2, shallow separator 3 and 4, two dark separators 2 of buried regions are arranged in buried regions 4 both sides in the silicon substrate 1.Collector region 5 and collector electrode draw-out area 6 are arranged in the silicon substrate 1 on the buried regions 4.Interior base 7b is arranged on the collector region 5, on partial silicon substrate 1, the dark separator 2 of part and the shallow separator 3 of part outer base area 7a is arranged, two outer base area 7a are in 7b both sides, interior base.Medium 16 and T shape emitter 12 are arranged on the interior base 7b, and there is side wall (medium) 11 both sides of medium 16 and T shape emitter 12.On outer base area 7a, T shape emitter 12 and the collector electrode draw-out area 6 metal silicide 13 and contact hole 14 are arranged, inter-level dielectric 15 is arranged on all the other zones.
In existing silicon-germanium HBT device, interior base 7b and outer base area 7a are sige alloys, and according to the mol ratio of silicon, germanium, chemical formulation is Si
xGe
1-xPerhaps Ge
1-xSi
xEmitter 12 adopts polysilicon usually; Collector region 5 adopts the silicon (monocrystalline silicon) that doping is arranged usually.For the demand that increases amplification coefficient and rising cut-off frequency as far as possible, general emitter 12 all is T shape structure, its medium 16 by T shape structure two shoulder positions belows and interior base 7b and outer base area 7a are isolated, and link to each other with interior base 7b by a very little emitter-window (being the bottom of T shape structure).
Existing silicon-germanium HBT, the manufacture method of its T shape emitter 12 is such: earlier at ready silicon chip surface deposit one deck dielectric; Etch emitter-window at dielectric; At silicon chip surface deposit emitter material (as polysilicon), the part of emitter material in emitter-window is exactly narrower part below the T shape emitter; Etching emitter material and insulating material form complete T shape emitter 12 and insulating barrier 16.Form outer base area 7a and interior base 7b with ion implantation technology then.Described ready silicon chip refers to form in the silicon substrate 1 dark separator 2, shallow separator 3, buried regions 4, collector region 5 and collector electrode draw-out area 6, and silicon substrate 1 top is deposit base material (as sige alloy).
Above-mentioned silicon-germanium HBT structure and manufacture method thereof have following deficiency:
The first, etch emitter-window owing to first at insulating barrier, again the deposit polysilicon; Be subjected to the restriction of technological ability, the upper surface of the polysilicon at emitter-window place (being the upper surface of T shape emitter) can't be accomplished complete planarization, and has a significant depressions, and this depression does not constantly change along with the shape of the uniformity difference of depositing technics, emitter-window does not coexist, and causes emitter very big to effective emitter varied in thickness of base.Emitter thickness difference can have influence on follow-up base again when injecting, and the interior base 7b of diverse location and the silicon of outer base area 7a and/or the CONCENTRATION DISTRIBUTION of germanium have slight change.The two variation is very big for the amplification coefficient of final silicon-germanium HBT and cut-off frequency influence, causes the whole yields of silicon-germanium HBT that final actual production goes out to be difficult to promote, and can only in a disguised form reach higher yields by reducing technical indicator sometimes.
Second, in order to improve the yields of silicon-germanium HBT, fidelity to emitter-window requires very high, because the upper surface of the polysilicon at emitter-window place has significant depressions, the shape and size control that must keep unusual high request, could guarantee because the variation of the emitter effective thickness that the difference that caves in causes in allowable range.For 0.35 μ m, amplification coefficient 100, the HBT technology of cut-off frequency 10～40GHZ, only 3% critical size difference or 0.5% emitter-window rectangular aspect ratio change and just can cause that cut-off frequency, operating voltage, amplification coefficient etc. exceed standard, cause rate of finished products to reduce significantly, and general production gone up the technology controlling and process ability all about 5%～10%.So traditional HBT manufacturing process, the emitter-window technology difficulty is very big, often needs to use more high-end photoetching technique to satisfy the demand of low side technology.For example the silicon of 0.35 μ m-emitter-window of germanium HBT need be used the photoetching process of 0.18 μ m, and the emitter-window of the silicon of 0.13 μ m-germanium HBT need be used the photoetching process of 0.09 μ m or 0.065 μ m, this makes silicon-germanium HBT will lag behind CMOS technology more than 2 generations, has limited the development in integrated artistic generation simultaneously.
The 3rd, silicon-germanium HBT is applied to high speed device, along with present CMOS technology begins generally to adopt high k (dielectric constant) metal material as grid, for example is alloy material or the oxide that contains hafnium (Hf).In order to keep the highly compatible with CMOS technology, the emitter of silicon-germanium HBT also adopts high k metal material certainly will become development in future trend.Yet because high k metal material thermal endurance is very poor, must after all main ion implantation technologies, form again, therefore can't be with traditional first deposit, etching, the formation of reflooded method again.The etching technics difficulty height of high k metal material and etching apparatus and gas are more special simultaneously, and cost is very high.
The 4th, the maximum operation frequency of silicon-germanium HBT and the electric capacity of outer base area 7a and resistance relation are very big.The work period of silicon-germanium HBT was made up of the following time period: the lag time of base 7b in electric current flow to by outer base area 7a, emitter 12 under vertical voltage, produce electronics be transmitted in lag time of base 7b, the free carrier that produces under the 7b transverse electric field effect of interior base produces vertical amplified current under the emission electronic action of the lengthwise movement that emitter 12 produces time, the longitudinal current that interior base 7b produces is collected the time of back output by collector region 5.Therefore the operating frequency of silicon-germanium HBT is determined by above these time periods basically.
For reduce electric current flow to by outer base area 7a in lag time of base 7b, the RC hysteresis effect of this part circuit of inevitable requirement is as far as possible little, this just requires the electric capacity of outer base area 7a and resistance low; In order to improve the amplification efficient of emitter input current, it is big as far as possible laterally to inject electric current under identical operating voltage simultaneously, therefore also requires the resistance of outer base area 7a low.Thereby common HBT technology all can use the doped silicon of the low electric capacity of low resistance or silicon-germanium alloy as outer base area, outer base area 7a injected mix and annealing activates the resistance that further reduces outer base area 7a simultaneously.
But in existing silicon-germanium HBT technology, outer base area all adopts the epitaxy technique growth usually.And epitaxy technique has high requirements for backing material, therefore direct growth outer base area 7a on silicon substrate usually, this just means that existing silicon-germanium HBT structure and technology must cause outer base area 7a to link to each other with silicon substrate 1, silicon-germanium HBT is the audion of NPN or PNP simultaneously, the doping type of outer base area 7a is inevitable opposite with substrate, therefore the impurity of outer base area 7a can produce to vertical direction and diffuse to form parasitic PN junction behind implantation annealing, makes extra parasitic capacitance C1, C2 and the dead resistance (as shown in Figure 1) of generation between outer base area 7a and the silicon substrate 1.And the existence of parasitic capacitance C1, C2 can reduce electric current flow to by outer base area 7a in lag time of base 7b, thereby limited the lifting of silicon-germanium HBT maximum operation frequency.
Summary of the invention
Technical problem to be solved by this invention provides a kind of silicon-germanium HBT, and the upper surface of its T shape emitter is comparatively smooth, has lower parasitic capacitance between its outer base area and the silicon substrate.For this reason, the present invention also will provide the manufacture method of described silicon-germanium HBT, and this method adopts common process can make T shape emitter, and CMOS technique compatible makes emitter can adopt high k metal material simultaneously.
For solving the problems of the technologies described above, silicon-silicon-germanium heterojunction bipolar transistor of the present invention comprises T shape emitter, interior base and outer base area, and the bottom of described T shape emitter contacts with interior base; The maximum of the vertical range of the upper surface of described T shape emitter and interior base upper surface is a, and minimum value is b, and the difference of a and b is c, and c is less than or equal to 5% of b, and perhaps c is less than or equal to
Described outer base area comprises that the polysilicon of sige alloy and top thereof is two-layer altogether; The base is sige alloy one deck in described; Have inside wall to isolate between the bottom of described outer base area and T shape emitter, described inside wall is also as the isolation between the top of interior base and T shape emitter.
The manufacture method of above-mentioned silicon-silicon-germanium heterojunction bipolar transistor comprises the steps:
The 1st step, adopt photoetching and etching technics base protective layer ready silicon chip etches in, described interior base protective layer comprise silica 9 and on first silicon nitride layer 10;
Described ready silicon chip is to have formed dark separator 2, shallow separator 3, buried regions 4, collector region 5 and collector electrode draw-out area 6 in silicon substrate 1, at silicon chip surface deposit silicon germanium alloy 7 successively, silica 9 and first silicon nitride layer 10;
The 2nd step is at silicon chip surface deposit one deck polysilicon layer 8 successively and the second silicon nitride layer 10a;
The 3rd step, adopt photoetching and etching technics to etch a rectangular window A at silicon chip, stop etching when etching into first silicon nitride layer 10;
The 4th step is at silicon chip surface deposit one deck first dielectric layer 11;
The 5th step, adopt dual damascene process to etch T shape emitter-window B at silicon chip surface, described T shape emitter-window B lower width is less than base protective layer width in described, stop etching when etching into silicon oxide layer 9, the interior residual emitter material 12 of T shape emitter-window B this moment has constituted T shape emitter;
In the 6th step, the employing wet corrosion technique is removed the silica under the T shape emitter-window;
The 7th step is at silicon chip surface deposit one deck emitter material 12;
The 8th step, adopt chemical mechanical milling tech that silicon chip surface is carried out planarization, when being ground to first dielectric layer, 11 upper surfaces, stop;
The 9th step, adopt photoetching and etching technics to etch external wall at silicon chip, stop etching when etching into polysilicon layer 8;
The 10th step, adopt photoetching and etching technics to etch the outer boundaries of outer base area at silicon chip, stop etching when etching into silicon substrate 1;
The 11st step formed metal silicide 13 on the polysilicon layer 8 of outer base area, T shape emitter and collector draw-out area 6, at silicon chip surface deposit one deck second dielectric layer 15, form contact hole 14 in second dielectric layer 15 on metal silicide 13.
Silicon of the present invention-germanium HBT and manufacture method thereof, T shape emitter adopts common process (dual damascene process etching T shape window, deposit and cmp) manufacturing, has very smooth upper surface.Behind the deposit emitter material, do not have the ion implantation step, so emitter can adopt polysilicon or high k metal material, and compatible mutually with the metal gate process of CMOS.Outer base area comprises that polysilicon and sige alloy are two-layer, and the sige alloy layer that contacts with silicon substrate is light dope, thereby has reduced the diffusion of outer base area impurity to substrate, thereby has reduced parasitic capacitance, is conducive to improve the overall work frequency of device.
Description of drawings
Fig. 1 is the structural representation of a kind of existing silicon-germanium HBT;
Fig. 2 is the structural representation of the embodiment of silicon of the present invention-germanium HBT;
Fig. 3 a～Fig. 3 k is each step schematic diagram of the manufacture method of silicon of the present invention-germanium HBT;
Fig. 4, Fig. 5 are the structural representations of two embodiment in addition of silicon of the present invention-germanium HBT.
Description of reference numerals among the figure:
1 is silicon substrate; 2 is dark separator; 3 is shallow separator; 4 is buried regions; 5 is collector region; 6 is the collector electrode draw-out area; 7 is sige alloy; 7a is base in the sige alloy; 7b is the sige alloy outer base area; 8 is polysilicon; 9 is silica; 10,10a is silicon nitride; 11,11a is medium; 12 is emitter; 13 is metal silicide; 14 is contact hole; 15 is inter-level dielectric; 16 is medium; A is rectangular window; B is T shape window.
Embodiment
See also Fig. 2, this is the embodiment of silicon of the present invention-germanium HBT.Dark separator 2, shallow separator 3, buried regions 4, collector region 5 and collector electrode draw-out area 6 are arranged in the silicon substrate 1.
Wherein silicon substrate 1 also can be two parts, is silicon substrate below buried regions 4, is epitaxial loayer above buried regions 4, this to the present invention without any influence.
The manufacture method of separator 2 and shallow separator 3 normally deeply: offer isolation channel at silicon chip earlier, use insulating material (as silica, silicon nitride, silicon oxynitride etc.) as side wall protective layer then, carrying out trench fill again (is generally polysilicon or above-mentioned insulating material, also may adopts special process to form the air gap; As adopt the air gap then also to need polysilicon or above-mentioned insulating material to the ditch slot seal).
Shallow separator 3 only also can change on silicon substrate 1, and adopt deposit and etching technics to form this moment.
Buried regions 4, collector region 5 and collector electrode draw-out area 6 normally adopt ion implantation technology to form.
Usually silicon-germanium HBT is the NPN type, and for the silicon-germanium HBT of NPN type, details are as follows for the material of each several part and doping type:
If silicon substrate 1 changes the silicon substrate of buried regions 4 belows and epitaxial loayer two parts of buried regions 4 tops into, then the silicon substrate of buried regions 4 belows is doped with p-type impurity, for example boron etc.; The epitaxial loayer of buried regions 4 tops is doped with n type impurity.
Buried regions 4 normally has the heavily doped monocrystalline silicon of n type impurity, is used for the cabling between collector region 5 and the collector electrode draw-out area 6.The doping content of buried regions 4 is than the doping content height of silicon substrate 1, thus the lower resistance of acquisition.
Collector electrode draw-out area 6 is the n type heavily doped regions that form by ion implantation technology on silicon substrate 1, and its doping content with collector region 5 is different, therefore needs Twi-lithography+ion implantation technology to realize usually.
Sige alloy, according to the mol ratio of silicon, germanium, chemical formulation is Si
xGe
1-xPerhaps Ge
1-xSi
xBase 7b is identical with doping content with the doping type of sige alloy outer base area 7a in the sige alloy, all is doped with p-type impurity; In order to reduce defective, to improve performance and also can add a certain amount of carbon.
It is p-type that polysilicon 8 has identical doping type with sige alloy outer base area 7a, and is p-type heavy doping.
Medium 11 can be unadulterated silica, silicon nitride; Perhaps be doped with silica, the silicon nitride of boron, phosphorus; Perhaps other low k dielectric materials for example are silica, the silicon nitrides that is doped with fluorine.Different doping types and doping content can change the electrology characteristic of medium 11, as dielectric constant etc.
T shape emitter material 12 can be polysilicon or other high k metal materials, and it mixes for the n type.
Compare with existing silicon-germanium HBT (shown in Figure 1), the embodiment of silicon of the present invention-germanium HBT shown in Figure 2 has following characteristics:
1, the upper surface of T shape emitter 12 keeps smooth.If the maximum of the vertical range between the upper surface of base 7b in the upper surface of T shape emitter 12 and the sige alloy is made as a, minimum value is made as b, a-b=c, then c≤0.05b or
Ideally, the upper surface of T shape emitter 12 is horizontal.
Among existing silicon-germanium HBT, T shape emitter is to adopt deposit and two steps of etching, emitter material during deposit is exactly the thickness of the final T shape emitter that forms, because the irregular situation of T shape emitter upper surface can appear in the existence of T shape emitter-window inevitably.The present invention then adopts deposit and two steps of chemico-mechanical polishing (CMP) to form T shape emitter.Can deposit when deposit than the thicker emitter material of thickness of T shape emitter, carry out the planarization of T shape emitter upper surface afterwards by chemico-mechanical polishing, therefore can form the smooth T shape emitter of upper surface.
2, outer base area comprises two-layer: the sige alloy layer 7a and the polysilicon layer 8 that is positioned at the top that are positioned at the below.In fact, the interior base 7b of sige alloy outer base area 7a and sige alloy is identical one deck sige alloy among the present invention, base 7b among the present invention silica 9 and the sige alloy below T shape emitter 12 bottoms being called is called outer base area 7a with the sige alloy of remainder.
Among silicon of the present invention-germanium HBT, because that outer base area comprises sige alloy layer and polysilicon is two-layer, so outer base area thickness is inevitable greater than interior base thickness.In the outer base area, polysilicon layer thickness is preferably
Among existing silicon-germanium HBT, outer base area only is sige alloy, and it requires the sige alloy outer base area to carry out extra ion injection, in order to have the p-type impurity than base higher concentration in the sige alloy.When the sige alloy outer base area is carried out annealing process, because the sige alloy outer base area is opposite with silicon substrate contact and doping type, therefore the impurity in the sige alloy outer base area can diffuse to form parasitic PN junction to silicon substrate in the vertical direction after annealing, thereby has had parasitic capacitance and dead resistance.Whole one deck sige alloy has the p-type doping of low concentration among the present invention, and polysilicon outer base area 8 is p-type heavy doping.Though between sige alloy outer base area 7a after the annealing and silicon substrate 1, also have parasitic capacitance and dead resistance like this, because the doping content of whole layer sige alloy is lower, therefore parasitic capacitance and dead resistance are less, and the sige alloy layer 7a of outer base area and the parasitic capacitance between the silicon substrate 1 are less than 1pF usually.Lower parasitic capacitance can shorten the lag time that electric current flows from the inside base of outer base area, thereby shortens the overall work time, is conducive to improve the overall work frequency of silicon-germanium HBT.
The manufacture method of silicon of the present invention-germanium HBT shown in Figure 2 comprises the steps:
The 1st step saw also Fig. 3 b, adopted photoetching and etching technics base protective layer ready silicon chip etches in, described interior base protective layer comprise silica 9 and on silicon nitride 10.The sige alloy 7 of protective layer below, interior base is exactly base 7b in the sige alloy.
Described ready silicon chip sees also Fig. 3 a, is to have formed dark separator 2, shallow separator 3, buried regions 4, collector region 5 and collector electrode draw-out area 6 in silicon substrate 1, at the silicon chip of silicon chip surface deposit silicon germanium alloy 7, silica 9 and silicon nitride 10.
In the 2nd step, see also Fig. 3 c, at silicon chip surface deposit one deck polysilicon 8 successively and silicon nitride 10a.
The 3rd step saw also Fig. 3 d, adopted photoetching and etching technics to etch a rectangular window A at silicon chip, stopped etching when etching into silicon nitride layer 10.
The 4th step saw also Fig. 3 e, and at silicon chip surface deposit one deck medium 11, medium 11 can be silica, silicon nitride, silicon oxynitride etc.
The 5th step saw also Fig. 3 f, adopted dual damascene process to etch T shape emitter-window B at silicon chip surface, stopped etching when etching into silicon oxide layer 9.T shape window B bottom (being the vertical line part of T shape) width is less than the width of silicon nitride 10.Dual damascene process is a kind of very ripe semiconductor fabrication process, " semiconductor fabrication " that the Electronic Industry Press published in 2004 (U.S. Michael Quirk, Julian Serda work) 301-303 page or leaf has been introduced the typical process flow of dual damascene process, can be used as a kind of reference.
The 6th step saw also Fig. 3 g, and the employing wet corrosion technique is removed the silica under the T shape emitter-window B.
The 7th step saw also Fig. 3 h, and at silicon chip surface deposit one deck emitter material 12, emitter material 12 can be polysilicon or high k metal.
The 8th step saw also Fig. 3 i, adopted chemical mechanical milling tech that silicon chip surface is carried out planarization, stopped when being ground to dielectric layer 11 upper surfaces.The interior residual emitter material of T shape window B this moment has constituted T shape emitter 12.Chemical mechanical milling tech can guarantee that the upper surface of T shape emitter 12 is smooth, and need not other technologies of higher level, smaller szie.
The 9th step saw also Fig. 3 j, adopted photoetching and etching technics to etch external wall at silicon chip, stopped etching when etching into polysilicon layer 8.External wall herein comprises silicon nitride 10a and medium 11.
The 10th step saw also Fig. 3 k, adopted photoetching and etching technics to etch the outer boundaries of outer base area at silicon chip, stopped etching when etching into silicon substrate 1.The sige alloy of the remainder in will removing this moment beyond the base 7b is called sige alloy outer base area 7a, and sige alloy outer base area 7a and remaining polysilicon 8 have constituted the outer base area of silicon-germanium HBT jointly.
The 11st step, see also Fig. 2, on the polysilicon layer 8 of outer base area, on the T shape emitter 12 and form metal silicide 13 respectively on the collector electrode draw-out area 6, at silicon chip surface deposit one deck medium 15, form contact hole 14 in the medium 15 on metal silicide 13.The formation of metal silicide 13 normally is deposited on refractory metal on the silicon chip, carries out The high temperature anneal then to form metal silicide.Medium 15 can be silica, silicon nitride, silicon oxynitride etc.
Said method is in the 1st step, and the width (being the width of silica 9 or silicon nitride 10) of base protective layer is x in establishing; Said method is in the 3rd step, and the width of establishing rectangular window A is y; Said method is in the 5th step, and top (being the horizontal line part of the T shape) width of establishing T shape window B is z.Then when x 〉=y, the bottom of medium 11 is on silicon nitride 10; When x＜y, the bottom of medium 11 is on sige alloy outer base area 7a.When z 〉=y, medium 11 is divided into two parts 11 and 11a, and its medium 11 is parts of external wall, and medium 11a is the part of inside wall; When z＜y, medium 11 keeps an integral body, is the part of external wall, also is the part of inside wall.
Fig. 4, Fig. 5 have provided two other embodiment of silicon of the present invention-germanium HBT.Wherein Fig. 4 is corresponding to the situation of x＜y and z＜y, and Fig. 5 is corresponding to the situation of x 〉=y and z＜y, and Fig. 2 is then corresponding to the situation of x 〉=y and z 〉=y.
Said method is in the 5th step, and owing to the width of restriction T shape window B lower width less than silicon nitride 10, so the both sides of T shape emitter 12 bottoms are always silica 9, silicon nitride 10 and medium 11 or 11a.In other words, the inside wall of silicon of the present invention-germanium HBT always is made up of silica 9, silicon nitride 10 and medium 11 or 11a.When medium 11 was as a whole, inside wall comprised medium 11.When medium 11 was decomposed into two parts, the both sides on T shape emitter 12 tops were medium 11, and inside wall comprises medium 11a.
The both sides on T shape emitter 12 tops are medium 11 always.
(being external wall) or medium 11 between the polysilicon layer 8 of T shape emitter 12 tops and outer base area, or medium 11 and silicon nitride 10a.
The various embodiments described above disclose silicon of the present invention-germanium HBT and manufacture method thereof, it should be noted that above-mentioned each structure, each processing step and concrete numerical value etc. are the usefulness of signal.Under the prerequisite of not violating the principle of the invention, thought and spirit, to any change, modification and the variation that the various embodiments described above are done, all should regard as within protection scope of the present invention.
Claims (3)
1. the manufacture method of a silicon-silicon-germanium heterojunction bipolar transistor, it is characterized in that, described silicon one silicon-germanium heterojunction bipolar transistor comprises T shape emitter, interior base and outer base area, the maximum of the vertical range of the upper surface of described T shape emitter and interior base upper surface is a, minimum value is b, the difference of a and b is c, and c is less than or equal to 5% of b, and perhaps c is less than or equal to
Described outer base area comprises that the polysilicon of sige alloy and top thereof is two-layer altogether; The base is sige alloy one deck in described; The manufacture method of described silicon-silicon-germanium heterojunction bipolar transistor comprises the steps:
The 1st step, adopt photoetching and etching technics base protective layer ready silicon chip etches in, described interior base protective layer comprise silica (9) and on first silicon nitride layer (10);
Described ready silicon chip is to have formed dark separator (2), shallow separator (3), buried regions (4), collector region (5) and collector electrode draw-out area (6) in silicon substrate (1), at silicon chip surface deposit silicon germanium alloy (7), silica (9) and first silicon nitride layer (10);
The 2nd step is at silicon chip surface deposit one deck polysilicon layer successively (8) and second silicon nitride layer (10a);
The 3rd step, adopt photoetching and etching technics to etch a rectangular window (A) at silicon chip, stop etching when etching into first silicon nitride layer (10);
The 4th step is at silicon chip surface deposit one deck first dielectric layer (11);
The 5th step, adopt dual damascene process to etch T shape emitter-window (B) at silicon chip surface, described T shape emitter-window (B) lower width stops etching less than base protective layer width in described when etching into silicon oxide layer (9);
In the 6th step, the employing wet corrosion technique is removed the silica under the T shape emitter-window;
The 7th step is at silicon chip surface deposit one deck emitter material (12);
The 8th step, adopt chemical mechanical milling tech that silicon chip surface is carried out planarization, when being ground to first dielectric layer (11) upper surface, stop, residual emitter material (12) has constituted T shape emitter in T shape emitter-window this moment (B);
The 9th step, adopt photoetching and etching technics to etch external wall at silicon chip, stop etching when etching into polysilicon layer (8);
The 10th step, adopt photoetching and etching technics to etch the outer boundaries of outer base area at silicon chip, stop etching when etching into silicon substrate (1);
The 11st step, on the polysilicon layer (8) of outer base area, T shape emitter and collector draw-out area (6), form metal silicide (13), at silicon chip surface deposit one deck second dielectric layer (15), form contact hole (14) o in second dielectric layer (15) on metal silicide (13)
2. the manufacture method of silicon one silicon-germanium heterojunction bipolar transistor according to claim 1 is characterized in that, described method l is in the step, and the width of base protective layer is x in establishing; Described method is in the 3rd step, and the width of establishing rectangular window (A) is y; Described method is in the 5th step, and the upper width of establishing T shape emitter-window (B) is z;
Then when x 〉=y, the bottom of first dielectric layer (11) is on first silicon nitride layer (10);
When x＜y, the bottom of first dielectric layer (11) is on sige alloy outer base area (7a);
When z 〉=y, first dielectric layer (11) is divided into two parts, and wherein a part is the part of external wall, and another part is the part of inside wall;
When z＜y, first dielectric layer (11) keeps an integral body, is the part of external wall, also is the part of inside wall.
3. according to the manufacture method of the described silicon-silicon-germanium heterojunction bipolar transistor of claim l, it is characterized in that, during described method the 9th goes on foot, described external wall or first dielectric layer (11), or first dielectric layer (11) and second silicon nitride layer (10a); The inside wall of described silicon-silicon-germanium heterojunction bipolar transistor always is made up of silica (9), first silicon nitride layer (10) and first dielectric layer (11); The both sides on described T shape emitter top are first dielectric layer (11) always.
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|---|---|---|---|---|
| CN102412272B (en) * | 2011-07-28 | 2013-09-11 | 上海华虹Nec电子有限公司 | Vertical parasitic type PNP device in BiCMOS technology |
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| CN109148291A (en) * | 2018-08-15 | 2019-01-04 | 深圳市诚朗科技有限公司 | A kind of transistor and preparation method thereof |
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