CN114388496A - Device integration scheme using bulk semiconductor substrate having <111> crystal orientation - Google Patents

Device integration scheme using bulk semiconductor substrate having <111> crystal orientation Download PDF

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Publication number
CN114388496A
CN114388496A CN202111085565.0A CN202111085565A CN114388496A CN 114388496 A CN114388496 A CN 114388496A CN 202111085565 A CN202111085565 A CN 202111085565A CN 114388496 A CN114388496 A CN 114388496A
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Prior art keywords
semiconductor substrate
bulk semiconductor
transistor
device region
layer stack
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CN202111085565.0A
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Chinese (zh)
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M·莱维
黄正铉
西瓦·P·阿度苏米利
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GlobalFoundries US Inc
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GlobalFoundries US Inc
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

Structures including devices such as transistors integrated on a bulk semiconductor substrate and methods of forming structures including devices such as transistors integrated on a bulk semiconductor substrate are disclosed. The bulk semiconductor substrate contains a single crystal semiconductor material having a diamond lattice structure and a <111> crystal orientation. The first transistor is formed in a first device region of the bulk semiconductor substrate, and the second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer composed of a III-V compound semiconductor material.

Description

Device integration scheme using bulk semiconductor substrate having <111> crystal orientation
Technical Field
The present invention relates to semiconductor device fabrication and integrated circuits, and more particularly, to structures including devices (e.g., transistors) integrated on a bulk semiconductor substrate and methods of forming structures including devices (e.g., transistors) integrated on a bulk semiconductor substrate.
Background
High voltage power electronic devices, such as high electron mobility transistors, may be fabricated using group III-V compound semiconductors to take advantage of their material properties, such as carrier mobility, which is greater than that of silicon. The group III-V compound semiconductor includes group III elements (aluminum, gallium, indium) and group V elements (nitrogen, phosphorus, arsenic, antimony). High electron mobility transistors may include heterojunctions between crystalline III-V compound semiconductor materials having different band gaps, such as a heterojunction between binary gallium nitride and ternary aluminum gallium nitride. During operation, a two-dimensional electron gas is formed near the interface at the heterojunction and defines a channel of the high electron mobility transistor.
The integration of high electron mobility transistors with field effect transistors or heterojunction bipolar transistors formed on the same chip by Complementary Metal Oxide Semiconductor (CMOS) processing has proven to be a complex process. Integration may be achieved by wafer bonding or by using engineered or hybrid substrates, the nature of which makes the process of integrating high electron mobility transistors with these other types of transistors very complex.
What is needed are structures including devices (e.g., transistors) integrated on a bulk semiconductor substrate and methods of forming structures including devices (e.g., transistors) integrated on a bulk semiconductor substrate.
Disclosure of Invention
In one embodiment of the present invention, a structure includes a bulk semiconductor substrate composed of a single crystal semiconductor material having a diamond (diamond) crystal lattice structure and a <111> crystal orientation. The bulk semiconductor substrate has a first device region and a second device region. The structure includes a first transistor located in the first device region of the bulk semiconductor substrate and a second transistor located in the second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer composed of a III-V compound semiconductor material.
In one embodiment of the invention, a method includes providing a bulk semiconductor substrate comprised of a single crystal semiconductor material having a diamond crystal lattice structure and a <111> crystal orientation. The method also includes forming a first transistor in a first device region of the bulk semiconductor substrate, forming a layer stack including layers composed of III-V compound semiconductor materials in a second device region of the bulk semiconductor substrate, and forming a second transistor using the layer stack.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above, and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like numerals refer to like features throughout the various views.
Fig. 1-6 are cross-sectional views of structures at successive stages of manufacture of a processing method according to an embodiment of the invention.
FIG. 3A is an enlarged cross-sectional view of a portion of FIG. 3 according to an embodiment of the present invention.
Fig. 7 is a cross-sectional view of a structure according to an alternative embodiment of the present invention.
Fig. 8 and 9 are cross-sectional views of structures at successive stages of manufacture of a processing method according to an alternative embodiment of the invention.
Fig. 10 is a cross-sectional view of a structure according to an alternative embodiment of the present invention.
Description of the main Components
10 semiconductor substrate
12 top surface
14 shallow trench isolation region
16 device area
18 device region
20 device area
22 gate conductor layer, layer
24 gate dielectric layer
26 hard mask
29 sidewalls, trench sidewalls
30 grooves
31 side wall, trench side wall
32 surface of
34 sidewall spacer
35 top surface of
36 layer Stack
37 side wall
40 source/drain region
42 field effect transistor, transistor
44 bipolar junction transistor, transistor
46 collector electrode
48 emitter
50 base layer
52 gate electrode
54 transistor
56 source region
58 drain region
60 interconnect structure
62 dielectric layer
64 contact
66 metal wire
68 opening
76 buffer layer, layer
78 channel layer, layer
80 spacer layer, layer
82 barrier layer, layer.
Detailed Description
Referring to fig. 1, a semiconductor substrate 10 comprising a single crystal semiconductor material (e.g., monocrystalline silicon) is provided, in accordance with an embodiment of the present invention. The semiconductor substrate 10 has a top surface 12, which may be planar. The semiconductor substrate 10 is a bulk substrate comprising a single crystal semiconductor material (e.g., monocrystalline silicon). In one embodiment, the single crystal semiconductor material of the semiconductor substrate 10 may have a diamond crystal lattice structure with a <111> crystal orientation as specified by the Miller index. In one embodiment, the semiconductor substrate 10 may comprise single crystal silicon having a diamond lattice structure with a <111> crystal orientation. For a semiconductor substrate 10 having a <111> crystal orientation, a (111) crystallographic plane is parallel to the top surface 12 of the semiconductor substrate 10, and a [111] crystallographic direction is perpendicular to the (111) plane. (100) The crystallographic axis (crystallographic axe) does not lie in the plane of the top surface 12. The semiconductor substrate 10 may be characterized as a non-silicon-on-insulator substrate (i.e., a non-SOI substrate) that lacks the buried oxide layer characteristic of a silicon-on-insulator (SOI) substrate. In one embodiment, the semiconductor substrate 10 may be entirely composed of a semiconductor material having a <111> crystal orientation.
Shallow trench isolation regions 14 are formed extending from the top surface 12 of the semiconductor substrate 10 to the semiconductor substrate 10. The shallow trench isolation regions 14 may comprise dielectric material deposited by chemical vapor deposition into trenches etched in the semiconductor substrate 10, polished, and stripped. The dielectric material included in the shallow trench isolation regions 14 may comprise silicon dioxide, silicon nitride, silicon carbide, silicon-rich silicon dioxide, or a combination of two or more of these materials. The shallow trench isolation region 14 may extend to a depth d1 relative to the top surface 12 into the semiconductor substrate 10. The shallow trench isolation region 14 surrounds and defines a plurality of device regions 16, 18, 20. In one embodiment, top surface 12 in device region 18 may be coplanar with top surface 12 in device region 16, or coplanar with top surface 12 in device region 20.
A gate conductor layer 22 comprised of doped polysilicon (i.e., doped polysilicon) and a gate dielectric layer 24 comprised of an electrical insulator (e.g., silicon dioxide) are formed on the semiconductor substrate 10. These layers 22, 24 are formed on the top surface 12 of all device regions 16, 18, 20.
A hard mask 26 may be formed over the layers 22, 24 on the semiconductor substrate 10 and patterned to include an opening generally over the device region 18. Hard mask 26 may be comprised of a dielectric material, such as silicon nitride, and may be patterned by photolithography and etching processes. The sections of the gate conductor layer 22 and the gate dielectric layer 24 exposed by the openings in the hard mask 26 may be removed by etching through an etching process, such as a reactive ion etching process, that exposes the top surface 12 of the semiconductor substrate 10 in the device region 18.
Subsequently, a trench 30 in the semiconductor substrate 10 is formed at the position of the opening in the hard mask 26 by etching using another etching process (e.g., a reactive ion etching process). The trench 30 may extend to the bottom of the trench at the surface 32 of the semiconductor substrate 10 and may have sides or sidewalls 29, 31. The trench 30 may be surrounded by shallow trench isolation regions 14 that define the device region 18. The surface 32 may be located at a depth d2 relative to the top surface 12 in the semiconductor substrate 10, the depth d2 being greater than the depth d1 of the shallow trench isolation region 14. The hard mask 26 protects the device region 16 and the segments of the gate conductor layer 22 and the gate dielectric layer 24 in the device region 20 during the etching process. In one embodiment, the surface 32 may be planar and free of topography. In one embodiment, the top surface 12 may be planar, the surface 32 may be planar, and the planes of the top surface 12 and the surface 32 may be parallel.
Referring to fig. 2, wherein like reference numerals refer to like features in fig. 1, at a subsequent fabrication stage of the processing method, sidewall spacers 34 are formed adjacent to the sidewalls 29, 31 of the trenches 30. Sidewall spacers 34 may extend from the top surface 12 of the semiconductor substrate 10 to the surface 32 at the bottom of the trench 30. The sidewall spacers 34 may be formed by depositing a liner layer composed of a dielectric material (e.g., silicon nitride) and etching the deposited liner layer using an anisotropic etch process (e.g., a reactive ion etch process).
Referring to fig. 3, 3A, wherein like reference numerals refer to like features in fig. 2, at a subsequent manufacturing stage of the processing method, a layer stack 36 comprising one or more compound semiconductor layers is formed on the surface 32 of the semiconductor substrate 10 within the trench 30. In an embodiment, the layer stack 36 may include at least one crystalline layer composed of a III-V compound semiconductor material. In an embodiment, the layer stack 36 may include at least one crystalline layer composed of a binary III-V compound semiconductor material. In an embodiment, the layer stack 36 may include at least one crystalline layer composed of a ternary III-V compound semiconductor material. In one embodiment, the layer stack 36 may comprise polycrystalline layers composed of different III-V compound semiconductor materials. In an embodiment, the layer stack 36 may include at least one crystal layer composed of a binary III-V compound semiconductor material and at least one crystal layer composed of a ternary III-V compound semiconductor material. In an embodiment, the layer stack 36 may include one or more crystal layers comprising gallium nitride or a ternary III-V compound semiconductor material based on gallium nitride (e.g., aluminum gallium nitride). In an embodiment, the layer stack 36 may include one or more crystalline layers containing gallium and nitrogen.
The layer stack 36 may be formed by an epitaxial growth process. Each layer of the layer stack 36 may have a monocrystalline crystalline structure or, alternatively, a substantially monocrystalline crystalline structure with varying degrees of crystalline defectivity. The <111> crystal orientation of the semiconductor material (e.g., single crystal silicon) of the semiconductor substrate 10 may facilitate epitaxial growth of III-V compound semiconductor material (e.g., gallium nitride) of the layer stack 36 having a low rate of crystal defects by a closer lattice match than a substrate having a <100> crystal orientation. Specifically, atoms having a <111> crystal orientation in the surface plane of the semiconductor substrate 10 are arranged in a hexagon, which may be reasonably lattice matched to the crystal structure of the one or more compound semiconductor materials in the layer stack 36 (e.g., wurtzite crystal structure of gallium nitride (based on a binary hexagonal close-packed crystal system).
In an embodiment, layer stack 36 may be formed by a selective epitaxial growth process, wherein semiconductor material is not formed on dielectric surfaces, such as hard mask 26 and sidewall spacers 34. In an embodiment, the layer stack 36 may be formed by a non-selective epitaxial growth process, wherein the semiconductor material is deposited and patterned by a photolithography and etching process. In an embodiment, the sidewalls 37 of the layer stack 36 may be located adjacent to and spaced apart from the trench sidewalls 29, 31, in which case the trench 30 may be substantially filled by the layer stack 36. In the representative embodiment, the layer stack 36 has sidewalls 37 that slope inward away from the trench sidewalls 29, 31 to define, for example, a trapezoidal shape and to space the sidewalls 37 from the trench sidewalls 29, 31. In an embodiment, the sidewalls 37 may converge at the top surface 35 of the layer stack 36, and the top surface 35 may be coplanar or substantially coplanar with the top surface 12 of the semiconductor substrate 10. Isolation regions (not shown) may be formed at the top surface 35 of the layer stack 36 by mask implantation of, for example, nitrogen or argon.
In an embodiment, as shown in fig. 3A, the layer stack 36 may include a buffer layer 76, a channel layer 78, a spacer layer 80, and a barrier layer 82. The layers 76, 78, 80, 82 may be formed sequentially using an epitaxial growth process (e.g., metal organic chemical vapor deposition). Each of the layers 76, 78, 80, 82 may have a single crystal structure or, alternatively, a substantially single crystal structure with varying degrees of crystal defectivity. One or more of the layers 76, 78, 80, 82 may include multiple sub-layers having different compositions or dopings. The buffer layer 76 may comprise a III-V compound semiconductor material, such as gallium nitride, that is tailored according to material composition, doping, and/or layer thickness to accommodate the lattice mismatch between the material of the semiconductor substrate 10 and the material of the channel layer 78. The channel layer 78 disposed above the buffer layer 76 may comprise a III-V compound semiconductor material, such as gallium nitride. A spacer layer 80 and a barrier layer 82 are disposed over the channel layer 78, the spacer layer 80 being located between the channel layer 78 and the barrier layer 82. The spacer layer 80 may be thin and may comprise a III-V compound semiconductor, such as aluminum nitride. The barrier layer 82 may comprise a III-V compound semiconductor, such as aluminum gallium nitride, aluminum nitride, or indium aluminum nitride, having a heterointerface with the channel layer 78 of different composition. The material properties of the spacer layer 80 and the barrier layer 82 and the channel layer 78 facilitate the generation of a two-dimensional electron gas at a heterogeneous interface filled with highly mobile and rich electrons during device operation.
Referring to fig. 4, wherein like reference numerals refer to like features in fig. 3, at a subsequent fabrication stage of the processing method, a dielectric layer 38 may be deposited and patterned by photolithography and etching processes so as to cover the layer stack 36 in the device region 18. After deposition and patterning of dielectric layer 38, hardmask 26 is removed from device region 16 and device region 20 by an etching process to expose gate conductor layer 22 and gate dielectric layer 24.
The gate conductor layer 22 and the gate dielectric layer 24 may then be patterned by photolithography and etching processes to define the gate structure of the field effect transistor 42 in the device region 16. During patterning, the gate conductor layer 22 and the gate dielectric layer 24 are removed from the device region 20. Additional elements of the field effect transistor 42 may be fabricated by Complementary Metal Oxide (CMOS) processing to form device structures in the device region 16 of the semiconductor substrate 10. Field effect transistor 42 may also include source/drain regions 40 and a channel region under the gate structure. The channel region and source/drain regions 40 of field effect transistor 42 comprise respective portions of the single crystal semiconductor material of semiconductor substrate 10. Source/drain regions 40 are at least partially below top surface 12, and a channel region is generally below top surface 12 between source/drain regions 40. The patterned gate conductor layer 22 and gate dielectric layer 24 included in the gate structure of the field effect transistor 42 may be positioned as device layers on and over the top surface 12 of the semiconductor substrate 10. In one embodiment, the patterned gate dielectric layer 24 included in the gate structure of the field effect transistor 42 may be positioned as a device layer directly on the top surface 12 of the semiconductor substrate 10.
The bipolar junction transistor 44 may be fabricated in the device region 20 of the semiconductor substrate 10 as a device structure. The bipolar junction transistor 44 may include a plurality of terminals in the form of a collector 46, an emitter 48, and a base layer 50 disposed between the collector 46 and the emitter 48 defined in the semiconductor substrate 10. In an alternative embodiment, an on-collector (collector-up) bipolar junction transistor may be formed, wherein the emitter is provided as a terminal in the semiconductor substrate 10. The emitter 48 and base layer 50 may be positioned as device layers on and above the top surface 12 of the semiconductor substrate 10. In one embodiment, the base layer 50 may be positioned directly on the top surface 12 of the semiconductor substrate 10 as a device layer. The collector 46 comprises a portion of the semiconductor material of the semiconductor substrate 10, which may be at least partially and preferably completely located in the semiconductor substrate 10 below the top surface 12. The base layer 50 may comprise a single crystal semiconductor material (e.g., silicon germanium) epitaxially grown on the top surface 12 of the semiconductor substrate 10. In one embodiment, the collector 46 and emitter 48 may comprise n-type semiconductor material and the base layer 50 may comprise p-type semiconductor material to define an NPN transistor. The bipolar junction transistor 44 may be formed from a bipolar complementary metal oxide (BiCMOS) process, which is a variation of a CMOS process.
The field effect transistor 42 and the bipolar junction transistor 44 constitute different types or classes of transistor structures. The difference between the field effect transistor 42 and the bipolar junction transistor 44 is that only the majority of the charge carriers flow in the field effect transistor 42, however, both the majority and minority of the charge carriers can flow in the bipolar junction transistor 44. The field effect transistor 42 and the bipolar junction transistor 44 do not include any silicon carbide layer in their respective structures and therefore do not contain silicon carbide. Both the field effect transistor 42 and the bipolar junction transistor 44 are formed on a semiconductor material having the same <111> crystal orientation as the semiconductor material used to form the layer stack 36.
Referring to fig. 5, wherein like reference numerals refer to like features in fig. 4, at a subsequent fabrication stage of the processing method, transistor 54 is formed into a device structure using layer stack 36. To this end, dielectric layer 38 is patterned in device region 18 by photolithography and etching processes to define openings that form gate electrodes 52 of transistors 54. The gate electrode 52 may be comprised of a metal (e.g., a metal nitride) that is deposited and patterned by a photolithography and etching process to define a given shape. Source region 56 and drain region 58 of transistor 54 may be formed by patterning openings in dielectric layer 38 using a photolithography and etching process, and then forming a metal (e.g., a metal nitride) in the patterned openings. Metal atoms from the source region 56 and the drain region 58 may diffuse into the layer stack 36.
Transistor 54 is not formed by a CMOS process and therefore can be considered a non-CMOS transistor. In one embodiment, the transistor 54 may be a High Electron Mobility Transistor (HEMT). In one embodiment, the transistor 54 may be a Metal Insulator Semiconductor High Electron Mobility Transistor (MISHEMT). In one embodiment, transistor 54 may be a Metal Oxide Semiconductor High Electron Mobility Transistor (MOSHEMT).
Although the <111> crystal orientation of the semiconductor material (e.g., monocrystalline silicon) of semiconductor substrate 10 enables epitaxial growth of the III-V compound semiconductor material of layer stack 36 having a low crystal defect rate, field effect transistor 42 and/or bipolar junction transistor 44 may exhibit non-optimized electrical performance due to the <111> crystal orientation as compared to comparable transistors formed on semiconductor substrates of other crystal orientations. Many structural and electronic properties of single crystal semiconductor substrates are highly anisotropic and depend on the orientation of the crystal. Nonetheless, implementation of a semiconductor substrate 10 having a <111> crystal orientation allows the transistor 54 to be integrated with the field effect transistor 42 and/or the bipolar junction transistor 44 on the same semiconductor substrate 10 without requiring complex manufacturing processes, such as wafer bonding, or the use of engineered or hybrid substrates (e.g., SOI substrates having one or more crystal orientations for the device layer), which may be considered an acceptable tradeoff for poor electrical performance.
Referring to fig. 6, wherein like reference numerals refer to like features in fig. 5, at a subsequent manufacturing stage of the processing method, a mid-stage process and subsequent back-stage processes include forming contacts, vias and wiring for an interconnect structure 60 located over the semiconductor substrate 10 and over the transistors 42, 44, 54. Various metallization levels of interconnect structure 60, such as a first metallization (M1) level, may be formed, which are coupled with field effect transistor 42, bipolar junction transistor 44, and transistor 54 through contact levels. In this regard, interconnect structure 60 may include one or more dielectric layers 62, metallization levels with metal lines 66, and contact levels with contacts 64 coupling metal lines 66 to field effect transistors 42, bipolar junction transistors 44, and transistors 54.
Referring to fig. 7 and in accordance with an alternative embodiment, the sidewalls 37 of the layer stack 36 may be coextensive with the trench sidewalls 29, 31, in which case the trench 30 may be completely filled by the layer stack 36. The growth conditions may be selected to impart a given shape to the layer stack 36. Processing may continue as described in connection with fig. 4-6.
Referring to fig. 8 and in accordance with an alternative embodiment, after completion of the formation of field effect transistor 42 and bipolar junction transistor 44, channel 30, layer stack 36, and transistor 54 may be completely formed. In this regard, one or more dielectric layers 62 may be formed and patterned to provide an opening 68 defining a path to the top surface 12 of the semiconductor substrate 10 in the device region 18. In the exemplary embodiment, opening 68 is formed prior to forming contact 64 and metal line 66. In one embodiment, the opening 68 may be formed after forming the contact 64 coupled to the contact level of the field effect transistor 42 and the bipolar junction transistor 44. In one embodiment, the openings 68 may be formed after forming the metal lines 66 of the first metallization level and the contacts 64 coupling the metal lines 66 to the contact levels of the field effect transistors 42 and the bipolar junction transistors 44.
Referring to fig. 9, wherein like reference numerals refer to like features in fig. 8, at a subsequent manufacturing stage of the processing method, trenches 30 are subsequently formed in the semiconductor substrate 10 at the location of the openings 68 in the one or more dielectric layers 62. Sidewall spacers 34, layer stack 36, and transistor 54 are then formed using channel 30 in semiconductor substrate 10. After forming transistor 54, opening 68 may be refilled with a dielectric material and interconnect structure 60 may be completed by forming contact 64 and metal line 66 coupled to transistor 54.
Referring to fig. 10 and in accordance with an alternative embodiment, the layer stack 36 may be formed on the top surface 12 of the semiconductor substrate 10 without the need to pre-form the trench 30. By forgoing trench formation, the layer stack 36 and the transistor 54 formed using the layer stack 36 may be located in the same plane as the field effect transistor 42 and the bipolar junction transistor 44. More specifically, the layer stack 36, the gate structure of the field effect transistor 42, and the emitter 48 and the base layer 50 of the bipolar junction transistor 44 may be located on the top surface 12, which may be considered to provide a common plane for the transistors 42, 44, 54.
The above method is used to manufacture integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as bare chips, or in packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier with leads secured to a motherboard or other higher level carrier) or in a multi-chip package (e.g., a ceramic carrier with one or both of surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of an intermediate or end product.
Terms modified by approximating language, such as "about," "about," and "substantially," as referred to herein, are not limited to the precise values specified. The approximating language may correspond to the precision of an instrument for measuring the value, and may represent +/-10% of the specified value, unless otherwise dependent on the precision of the instrument.
References herein to terms such as "vertical", "horizontal", and the like, are by way of example and not by way of limitation, to establish a frame of reference. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of a semiconductor substrate regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal, as just defined. The term "lateral" refers to a direction in the horizontal plane.
A feature being "connected" or "coupled" to another feature may be directly connected or coupled to the other feature or one or more intervening features may be present. One feature may be "directly connected" or "directly coupled" to or with another feature if there are no intervening features present. A feature may be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. One feature may be directly on or in direct contact with another feature or vice versa, or one or more intervening features may be present. If no intervening feature is present, one feature may be directly on or directly in contact with another feature. If there is at least one intervening feature, one feature may be indirectly on or in contact with another feature.
The description of the various embodiments of the invention has been presented for purposes of illustration but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, the practical application or technical improvements over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (20)

1. A structure, comprising:
a bulk semiconductor substrate comprising a single crystal semiconductor material having a diamond crystal lattice structure and a <111> crystal orientation, and having a first device region and a second device region;
a first transistor located in the first device region of the bulk semiconductor substrate; and
a second transistor located in the second device region of the bulk semiconductor substrate, the second transistor comprising a layer stack located on the bulk semiconductor substrate, and the layer stack comprising a layer composed of a III-V compound semiconductor material.
2. The structure of claim 1 wherein the single crystal semiconductor material is single crystal silicon.
3. The structure of claim 1, wherein the III-V compound semiconductor material comprises gallium nitride.
4. The structure of claim 1, wherein the III-V compound semiconductor material of the layer stack has a substantially single crystalline crystal structure.
5. The structure of claim 1, wherein the bulk semiconductor substrate has a top surface and the first transistor is a field effect transistor comprising a source/drain region in the bulk semiconductor substrate and at least partially below the top surface.
6. The structure of claim 5, wherein the bulk semiconductor substrate has a third device region, and further comprising:
a bipolar junction transistor located in the third device region of the bulk semiconductor substrate, the bipolar junction transistor including a terminal located in the bulk semiconductor substrate and at least partially below the top surface.
7. The structure of claim 1, wherein the bulk semiconductor substrate has a top surface, and the first transistor is a bipolar junction transistor including a terminal located in the bulk semiconductor substrate and at least partially below the top surface.
8. The structure of claim 1, wherein the bulk semiconductor substrate has a third device region, and further comprising:
a third transistor in the third device region of the bulk semiconductor substrate;
wherein the first transistor and the third transistor are of different transistor types.
9. The structure of claim 1, wherein the bulk semiconductor substrate has a top surface, and the layer stack is located on the top surface of the bulk semiconductor substrate.
10. The structure of claim 9, wherein the top surface of the bulk semiconductor substrate is planar in the first and second device regions, and the first transistor comprises a device layer on the top surface of the bulk semiconductor substrate.
11. The structure of claim 1, wherein the bulk semiconductor substrate has a first surface and a trench extending into the bulk semiconductor substrate from the first surface, and the layer stack is located on the bulk semiconductor substrate within the trench.
12. The structure of claim 11, wherein the bulk semiconductor substrate has a second surface located at the bottom of the trench, and the layer stack is located on the second surface.
13. The structure of claim 11, further comprising:
a shallow trench isolation region in the bulk semiconductor substrate, the shallow trench isolation region being laterally between the first device region and the second device region;
wherein the trench extends to a depth deeper into the bulk semiconductor substrate relative to the first surface than the shallow trench isolation region.
14. The structure of claim 11, wherein the trench includes a plurality of sidewalls, and further comprising:
a spacer on each of the plurality of sidewalls, the spacer comprised of a dielectric material.
15. The structure of claim 1, further comprising:
an interconnect structure over the bulk semiconductor substrate, the interconnect structure including a plurality of first contacts coupled to the first transistors and a plurality of second contacts coupled to the second transistors.
16. The structure of claim 1, further comprising:
a shallow trench isolation region in the bulk semiconductor substrate, the shallow trench isolation region being laterally between the first device region and the second device region.
17. A method, comprising:
providing a bulk semiconductor substrate comprised of a single crystal semiconductor material having a diamond crystal lattice structure and a <111> crystal orientation;
forming a first transistor in a first device region of the bulk semiconductor substrate;
forming a layer stack comprising layers consisting of III-V compound semiconductor materials in a second device region of the bulk semiconductor substrate; and
a second transistor is formed using the layer stack.
18. The method of claim 17, wherein the single-crystal semiconductor material is single-crystal silicon and the III-V compound semiconductor material is gallium nitride.
19. The method of claim 17, further comprising:
forming a trench extending into the bulk semiconductor substrate from a first surface to a second surface at a bottom of the trench;
wherein the layer stack is located on the second surface of the bulk semiconductor substrate within the trench.
20. The method of claim 17, further comprising:
forming a shallow trench isolation region in the bulk semiconductor substrate;
wherein the shallow trench isolation region is laterally located between the first device region and the second device region.
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