CN102034766A - 电子装置 - Google Patents
电子装置 Download PDFInfo
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- CN102034766A CN102034766A CN2010105015240A CN201010501524A CN102034766A CN 102034766 A CN102034766 A CN 102034766A CN 2010105015240 A CN2010105015240 A CN 2010105015240A CN 201010501524 A CN201010501524 A CN 201010501524A CN 102034766 A CN102034766 A CN 102034766A
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Abstract
本发明提供一种电子装置。电子装置包括:半导体器件;和安装基板,该安装基板安装有半导体器件并且与预定的电压相连接。半导体器件包括滤波器电路部件,该滤波器电路部件被构造为将除了想要的频率分量之外的输入信号的谐波分量输出到安装基板并且将想要的频率分量输出到滤波器电路部件的输出节点。滤波器电路部件包括电感器,该电感器大于安装基板中的寄生电感分量。
Description
技术领域
本发明涉及半导体器件、用于安装半导体器件的安装基板、以及包括半导体器件和安装基板的电子装置,并且更加具体地涉及包括滤波器电路的半导体器件、用于安装半导体器件的安装基板、以及包括半导体器件和安装基板的电子装置。
背景技术
在微波射频系统中,阻止到除了所使用的频率之外的频带的功率泄漏。为此,通常插入各种类型的滤波器以基本上衰减从系统中的各种类型的电源和信号处理电路产生的低频率噪声、从发送和接收部件的放大器产生的谐波信号等等。这些滤波器电路通常包括是无源元件的电容器和电感器。
最近,随着用于安装在移动设备上的滤波器模块的小型化的发展,在半导体芯片上构图的电容器和螺旋电感器被用于进一步小型化以前从离散部件的组合构造的滤波器模块。而且,它们被安装在同一半导体芯片上作为有源元件用于MMIC(单片微波集成电路)中的放大。
同时,在减少尺寸和面积方面,构图在半导体芯片上的螺旋电感器是有效的,但是在特性方面是不利的,并且很难在螺旋电感器中获得高Q值。因此,采用通过将一部分电感元件替换为具有高Q值的键合线的方案。
图1A至图1C是示出具有滤波器电路的传统的半导体器件和用于安装半导体器件的传统的安装基板的图。图1A是示出在包括封装的半导体芯片上的滤波器电路的附近的传统的半导体器件的内部结构的平面图。图1B是示出用于安装传统的半导体器件的封装的安装基板的构造的平面图。当图1C是从A方向看封装时的图1A中的半导体器件的横截面图。
半导体器件包括半导体芯片1、引线框架(LF)安装区域2、多个引线框架插脚端子3、模树脂4、以及多条键合线10a至10c。半导体芯片1包括滤波器电路部件、滤波器电路输入部件7、以及滤波器电路输出部件8。滤波器电路部件包括多个焊盘9a至9c、多个螺旋电感器图案5a至5e、以及多个电容器图案6a至6c。
安装基板包括安装基板组件15、安装基板前表面镀图案11、12a、和12b、以及安装基板后表面镀图案13。安装基板前表面镀图案11、12a、和12b包括封装中心部分区域11,被连接至封装中心部分区域11的插脚部分区域12a、以及没有被连接至封装中心部分区域的插脚部分区域12b。安装基板组件15包括通孔14。
安装基板被安装在外壳16上。包括引线框架安装区域2、引线框架插脚端子3、以及模树脂4的封装被安装在安装基板上。在这样的情况下,LF安装区域2被连接至安装基板前表面镀图案的封装中心部分区域11,并且引线框架插脚端子3被连接至安装基板前表面镀图案的插脚部分区域12a和12b。
半导体芯片1被安装在引线框架安装区域2上。通过模树脂4在其上固定其上安装半导体芯片1的引线框架安装区域2和多个引线框架插脚端子3。
多条键合线10a和10c中的每一条的一端被连接至引线架安装区域2。另外,多条键合线10a至10c的另一端分别被连接至多个焊盘9a至9c。在半导体芯片1的滤波器电路部件中,多个焊盘9a至9c分别被连接至多个螺旋电感器图案5a至5c的一端。多个螺旋电感器图案5a至5c的另一端分别被连接至多个电容器图案6a至6c的一端。电容器图案6a的另一端被连接至滤波器电路输入部件7。电容器图案6b的另一端被连接至多个螺旋电感器图案5d和5e的一端。电容器图案6c的另一端被连接至滤波器电路输出部件8。螺旋电感器图案5d的另一端被连接至滤波器电路输入部件7。螺旋电感器图案5e的另一端被连接至滤波器电路输出部件8。
安装基板上的封装中心部分区域11被连接至通孔14a的一端。通孔14a的另一端被连接至安装基板背面镀图案13。
螺旋电感器5a至5c分别被连接至电容器6a至6c,以形成三个谐振电路。这三个谐振电路经由焊盘9a至9c和键合线10a至10c分别被连接至引线框架安装区域2。这三个谐振电路使要被衰减的谐振信号的频率分量流至被连接至GND的引线框架安装区域2。结果,滤波器电路部件从滤波器电路输出部件8输出具有从滤波器电路输入部件7输入的信号的谐波分量的衰减信号。
假定滤波器电路部件分成三个部分,a、b、以及c。部分a包括螺旋电感器图案5a、电容器图案6a、焊盘9a、以及键合线10a。部分b包括螺旋电感器图案5b、电容器图案6b、焊盘9b、以及键合线10b。部分c包括螺旋电感器图案5c、电容器图案6c、焊盘9c、以及键合线10c。
在这样的情况下,关于输入信号的基频(f0),分别地,滤波器电路的部分a和部分b具有与二次谐波频率(2f0)相对应的谐振电路,并且部分3类似地具有与三次谐波频率(3f0)相对应的谐振电路。
图2是示出考虑图1A至图1C中的传统的半导体器件的滤波器电路中的寄生分量的等效电路的电路图。等效电路包括滤波器电路输入部件7、第一部分电路a、第二部分电路b、第三部分电路c、两个电感5d和5e、两条路径18a和18b、接地电压GND、以及滤波器电路输出部件8。第一部分电路a包括电容图案6a、螺旋电感图案5a、键合线10a、以及第一路径17a。第二部分电路b包括电容图案6b、螺旋电感图案5b、键合线10b、以及第二路径17b。第三部分电路c包括电容图案6c、螺旋电感图案5c、键合线10c、以及第三路径17c。
作为键合线10a至10c的连接目标的引线框架安装区域2不是理想的接地端子。实际上,键合线10a至10c和接地端子之间的连接经由安装基板表面镀图案的封装中心部分区域11和通孔14d。因此,与这些路线相对应的第一至第三路径17a、17b、以及17c中的每一条具有寄生电感分量。
另一方面,从键合线10a经由引线框架安装区域2被连接至键合线10b的路径18a和从键合线10b经由引线架安装区域2被连接至键合线10c的路径18b分别具有寄生电感分量。
同时,在传统的示例中,由于满足关系(路径17a至17c的长度>>路径18a和18b的长度),并且路径17a至17c以及路径18a和18b的寄生电感分量与长度近似地成比例,因此,满足关系(路径17a至17c的寄生电感分量>>路径18a和18b的寄生电感分量)。应注意的是,因为路径17a至17c的寄生电感充分地小于滤波器电路中的电感5a至5e,所以路径17a至17c的寄生电感分量能够被视为等效值L_GND。以相同的方式,路径18a和18b的寄生电感分量能够被视为等效值L_GND_ISO。
滤波器电路输入部件7被连接至第四螺旋电感图案5d的一端和电容图案6a的一端。电容图案6a的另一端被连接至螺旋电感图案5a的一端。螺旋电感图案5a的另一端被连接至键合线10a的一端。键合线10a的另一端被连接至第四路径18a的一端和第一路径17a的一端。第一路径17a的另一端被连接至接地电压GND。
第四螺旋电感图案5d的另一端被连接至第五螺旋电感图案5e的一端和电容图案6b的一端。电容图案6b的另一端被连接至螺旋电感图案5b的一端。螺旋电感图案5b的另一端被连接至键合线10b的一端。键合线10b的另一端被连接至第四路径18a的另一端,第五路径18b的一端,以及第二路径17b的一端。第二路径17b的另一端被连接至接地电压GND。
第五螺旋电感图案5e的另一端被连接至滤波器电路输出部件8以及电容图案6c的一端。电容图案6c的另一端被连接至螺旋电感图案5c的一端。螺旋电感图案5c的另一端被连接至键合线10c的一端。键合线10c的另一端被连接至第五路径18b的另一端以及第三路径17c的一端。第三路径17c的另一端被连接至接地电压GND。
结合上述描述,专利文献1(JP-A-Heisei 2-34014)公布一种复合半导体器件,该复合半导体器件包括具有高输入阻抗的晶体管以及电容和电感的内部匹配电路以获得最佳输入阻抗。
另外,专利文献2(JP-A-Heisei 8-274263)公布一种噪声滤波器,其通过将螺旋状的第一金属布线经由第一绝缘膜布置在半导体基板上来形成。通过经由第一金属布线上的第二绝缘膜将螺旋状的第二金属布线布置为彼此相对来形成噪声滤波器。在噪声滤波器中,第一金属布线用作信号线,并且通过键合线连接第二金属布线的引线电极和其上通过导电胶粘附半导体基板的引线框架从而第二金属布线和半导体基板处于相同的电压(接地)。
此外,专利文献3(JP 2002-93845A)公布一种集成信号滤波器,其包括信号滤波器、具有多个焊盘的集成电路、安装有集成电路并且具有多个焊盘的集成电路载体基板、以及被连接在焊盘中的两个之间的键合线,并且滤波器用作寄生到信号滤波器的电感元件。
此外,专利文献4(WO2003/094232)公布一种半导体器件,其包括密封基板、多条引线、接头、半导体芯片、多条第一导线、以及多条第二导线。在这里,密封基板包括绝缘树脂。沿着密封基板的外周从密封基板的内部到外部提供多条引线。接头具有主表面和背表面。半导体芯片具有主表面和背表面。半导体芯片包括主表面上的多个电极端子;和每个包括多个半导体元件的多个电路部件。多条第一导线将多个电极端子连接至引线。多条第二导线将多个电极端子连接至接头的主表面以将第一电压提供给多个电极端子。半导体芯片的背表面被固定在接头的主表面上。多个电路部件包括第一电路部件和第二电路部件。多个电极端子包括用于将外部信号输入到第一电路部件的第一电极端子、用于将第一电压提供给第一电路部件的第二电极端子、被连接至第二电路部件的第三电极端子、以及用于将第一电压提供给第二电路部件的第四电极端子。多条引线包括第一引线、第二引线、以及被布置在第一引线和第二引线之间的第三引线。第一电极端子经由导线被连接至第一引线。第二电极端子经由导线被连接至第三引线。第三电极端子经由导线被连接至第二引线。第四电极端子经由导线被连接至接头。第三引线和接头被相互隔开。
引用列表:
[专利文献1]:JP-A-Heisei 2-34014
[专利文献2]:JP-A-Heisei 8-274263
[专利文献3]:JP 2002-93845A
[专利文献4]:WO2003/094232
发明内容
图5是示出传统的半导体滤波器电路中其中忽略寄生分量的理想的信号传输特性的模拟结果的图。图5示出下述图,其中输入信号的基频(f0)是2.45GHz,并且滤波器电路的信号传输特性(S21)被示出为滤除4.9GHz的二次谐波频率(2f0)和7.35GHz的三次谐波(3f0)的通过。在附图中,水平轴表示到滤波器电路的输入信号的频率,并且竖直轴表示滤波器的信号通过特性。
在图中,第一线S(2,1)表示其中忽略寄生分量的理想的接地条件下的滤波器电路的信号传输特性,并且通过第一线S(2,1)上的标记(1)示出2f0的信号的滤除量作为传输信号与输入信号的比率。以相同的方式,第二线S(4,3)表示在其中存在寄生分量的情况下的传统的滤波器电路特性,并且通过第二线S(4,3)上的标记(2)示出2f0的信号的滤除量。在此图中,第一线示出第一条件下的滤波器电路特性。第二线示出第二条件下的滤波器电路特性。第三线“Ref”示出标准条件下的滤波器电路特性。
图3是示出在图1A至1C中的传统的滤波器电路中忽略寄生分量的情况下的理想的等效电路的电路图。图3中所示的电路图与其中从图2中的电路图中移除两条路径18a和18b以及三条路径17a至17c的电路图相同。因此,将会省略进一步详细的解释。
在图1A至图1C中所示的结构被采用作为实际组装的规格同时通过使用图3中所示的滤波器电路的理想的等效电路在计算模拟中执行电路设计的情况下,由于被包括在图2的等效电路中的两条路径18a和18b以及三条路径17a至17c中的寄生电感分量导致出现影响。即,满足关系(三条路径17a至17c中的寄生电感分量(L_GND)>>两条路径18a和18b中的寄生电感分量(L_GND_ISO))。
结果,通过构造2f0的谐振电路的滤波器电路b和滤波器电路a,假定频率分量(在本示例中2f0)通过将2f0的频率分量连接至接地电压GND而被滤除。然而,实际上,经由滤波器电路a、对应的路径18a、以及滤波器电路b在滤波器电路输出部件8上出现2f0的频率分量。为此,在传统示例中,滤除量小于理想情况下的滤除量。
另外,由于路径17a至17c导致的寄生电感分量不是取决于封装中的半导体器件而是取决于形成在安装基板15中的通孔14的直径或长度而变化。因此,当安装基板的图案变化时,滤波器电路的滤除量也因此改变。
本发明的主题是提供一种电子装置,其中谐波分量的滤除量增加。
在本发明的方面中,电子装置包括:半导体器件;和安装基板,该安装基板安装有半导体器件并且与预定的电压相连接。半导体器件包括滤波器电路部件,该滤波器电路部件被构造为将除了想要的频率分量之外的输入信号的谐波分量输出到安装基板并且将想要的频率分量输出到滤波器电路部件的输出节点。滤波器电路部件包括电感器,该电感器大于安装基板中的寄生电感分量。
根据本发明的电子装置,在半导体器件的滤波器电路中,通过抑制由寄生电感引起的谐波分量的滤除量的减少能够获得等于在其中不包括寄生电感的理想情况下的滤除量,并且因此谐波分量的滤除量增加。
附图说明
结合附图,根据某些实施例的以下描述,本发明的以上和其它目的、优点和特征将更加明显,其中:
图1A是示出滤波器电路的附近的传统的半导体器件的内部结构的平面图;
图1B是示出用于安装传统的半导体器件的封装的安装基板的构造的平面图;
图1C是图1A中的传统的半导体器件的横截面图;
图2是示出考虑寄生分量的滤波器电路的等效电路的电路图;
图3是示出在忽略寄生分量的情况下的理想的等效电路的电路图;
图4A是示出在半导体芯片上具有滤波器电路的根据本发明的实施例的半导体器件的内部结构的平面图;
图4B是示出安装有半导体器件的封装的安装基板的图案的平面图;
图4C是沿着虚线的在安装基板上安装有半导体器件的电子装置的横截面图;
图5示出信号传输特性的模拟结果的图;
图6是示出根据本发明的电子装置的滤波器电路的特性的模拟结果的图;
图7是根据本发明的第二实施例的电子装置的横截面图;以及
图8是示出根据本发明的电子装置的滤波器电路的信号通过特性中的二次谐波频率(2f0)滤除量的模拟计算结果的表。
具体实施方式
在下文中,将会参考附图详细地描述根据本发明的安装在安装基板上的半导体器件。
[第一实施例]
图4A至图4C是示出根据本发明的第一实施例的电子装置的构造的图。图4A是示出具有在半导体芯片上具有滤波器电路的本实施例中的半导体器件的封装部分的内部结构的平面图。图4B是示出根据本实施例的安装有半导体器件的封装的安装基板的图案的平面图。图4C是当从A方向中看时沿着虚线的在图4B中的安装基板上安装有图4A中的半导体器件的电子装置的横截面图。
根据本实施例的电子装置包括半导体芯片1、LF(引线框架)安装区域2、多个引线框架插脚端子3、模树脂4、以及多条键合线10a至10c。半导体芯片1包括滤波器电路部件、滤波器电路输入部件7、以及滤波器电路输出部件8。滤波器电路部件包括多个焊盘9a至9c、多个螺旋电感图案5a至5e、以及多个电容图案6a至6c。
根据本实施例的安装基板包括安装基板组件15、安装基板前表面镀图案11、12a、和12b、以及安装基板后表面镀图案13。安装基板前表面镀图案11、12a、和12b包括封装中心部分区域11、和没有被连接至封装中心区域的插脚部分区域12a和12b。安装基板组件15包括通孔14a和14b。
根据实施例的安装基板被安装在外壳16上。包括引线框架安装区域2、引线框架插脚端子3、以及模树脂4的封装被安装在安装基板上。在这样的情况下,引线框架安装区域2被连接至安装基板前表面镀图案的封装中心部分区域11,并且引线框架插脚端子3被连接至安装基板前表面镀图案的插脚部分区域12a和12b。
半导体集成电路的半导体芯片1被安装在引线框架安装区域2上。通过模树脂4固定安装有半导体芯片1的引线框架安装区域2和多个引线框架插脚端子3。
多条键合线10a和10c中的每一条的一端被连接至引线架安装区域2,并且键合线10b的一端被连接至引线框架插脚端子3。另外,多条键合线10a至10c中的每一条的另一端分别被连接至多个焊盘9a至9c。在半导体芯片1的滤波器电路部件中,多个焊盘9a至9c分别被连接至多个螺旋电感图案5a至5c的一端。多个螺旋电感图案5a至5c的另一端分别被连接至多个电容图案6a至6c的一端。电容图案6a的另一端被连接至滤波器电路输入部件7。电容图案6b的另一端分别被连接至多个螺旋电感图案5d和5e的一端。电容图案6c的另一端被连接至滤波器电路输出部件8。螺旋电感图案5d的另一端被连接至滤波器电路输入部件7。螺旋电感图案5e的另一端被连接至滤波器电路输出部件8。
安装基板表面上的封装中心部分区域11被连接至通孔14a的一端。通孔14a的另一端被连接至安装基板背表面镀图案13。
螺旋电感5a至5c分别被连接至电容6a至6c,以形成三个谐振电路。这三个谐振电路经由焊盘9a至9c和键合线10a至10c分别被连接至引线框架安装区域2。这三个谐振电路将要被衰减的谐振信号的频率分量连接至被连接至GND的引线框架安装区域2。结果,滤波器电路部件执行用于通过从滤波器电路输出部件8输出用于通过衰减与从滤波器电路输入部件7输入的信号有关的谐波分量获得的信号的操作。
将通过将此滤波器电路部件分成三部分,a、b、以及c来考虑该滤波器电路部件。部分a包括螺旋电感图案5a、电容图案6a、焊盘9a、以及键合线10a。部分b包括螺旋电感图案5b、电容图案6b、焊盘9b、以及键合线10b。部分c包括螺旋电感图案5c、电容图案6c、焊盘9c、以及键合线10c。
在这样的情况下,关于输入信号的基频(f0),分别地,滤波器电路部件的部分a和部分b具有与二次谐波频率(2f0)相对应的谐振电路,并且部分c类似地具有与三次谐波频率(3f0)相对应的谐振电路。
图2是示出考虑寄生分量的图4A至图4C中的根据本实施例的电子装置的滤波器电路的等效电路的电路图。等效电路包括滤波器电路输入部件7、第一部分电路a、第二部分电路b、第三部分电路c、两个电感5d和5e、两条路径18a和18b、接地电压GND、以及滤波器电路输出部件8。第一部分电路a包括电容图案6a、螺旋电感图案5a、键合线10a、以及第一路径17a。第二部分电路b包括电容图案6b、螺旋电感图案5b、键合线10b、以及第二路径17b。第三部件电路c包括电容图案6c、螺旋电感图案5c、键合线10c、以及第三路径17c。
作为各键合线10a至10c的连接目标的引线框架安装区域2不具有理想的接地电压GND。实际上,键合线10a至10c中的每一条和接地电压GND之间的连接经由安装基板前表面镀图案的封装中心部分区域11和通孔14d。因此,与这些路线相对应的第一至第三路径17a、17b、以及17c中的每一条具有寄生电感分量。同时,忽略寄生分量的理想的等效电路是与图3中所示的相同的电路。
另一方面,从键合线10a经由引线框架安装区域2连接至键合线10b的路径18a和从键合线10b经由引线架安装区域2连接至键合线10c的路径18b分别还具有寄生电感分量。
在本实施例中应注意的是,满足关系(路径18的长度>路径17的长度)并且路径17a至17c以及路径18a和18b的寄生电感分量与各自的长度近似地成比例。因此,满足关系(路径17a至17c的寄生电感分量<路径18a和18b的寄生电感分量)。在这里,路径17a至17c的寄生电感基本上小于滤波器电路中的电感5a至5e,并且因此路径17a至17c的寄生电感分量能够分别被视为等效值L_GND。以相同的方式,路径18a和18b的寄生电感分量能够被视为等效值L_GND_ISO。
图8中的表1示出根据本发明的电子装置的滤波器电路的信号通过特性中的二次谐波频率(2f0)滤除量的模拟计算结果。表1示出根据从键合线10a至10c(GND线)被连接至的引线框架安装区域2、经由路径17a至17c以及路径18a和18b、到用作接地电压GND的外壳16的寄生电感分量的变化的信号通过特性的变化。
图5是示出根据本发明的电子装置的滤波器电路的信号通过特性的模拟计算结果的图。该图示出滤波器电路的信号通过特性(S21),当输入信号的基频(f0)是2.45GHz时该滤波器电路阻止(滤除)4.9GHz的二次谐波频率(2f0)和7.35GHz的三次谐波(3f0)。在图中,水平轴表示到滤波器电路的输入信号的频率并且竖直轴表示信号通过特性。图5中绘制的四个图分别对应于表1的项目“图5中的表示”中的S(2,1)至S(8,7),并且在标记(1)至(4)将2f0的滤除量表示为通过信号与输入信号的比率,当值较小时其示出滤除量较大。
图6是示出根据本发明的电子装置的滤波器电路的特性的模拟结果的图。在该图中,水平轴表示L_GND_ISO/L_GND的比率,并且竖直轴表示滤波器电路中2f0的滤除量。
路径17a至17c中的寄生电感L_GND取决于通孔等等的条件而变化。作为表1中的寄生电感L_GND,使用当基板厚度是0.2mm,通孔的半径是0.2mm,并且镀敷厚度是17μm时的电磁场模拟中的结果。在电磁场模拟的结果中,每孔电感是0.6nH。所以,在表1中,寄生电感L_GND是0.06nH,并且通过与L_GND的比率来表示路径18a和18b中的寄生电感L_GND_ISO。
作为模拟的结果,在(L_GND_ISO/L_GND<0.5)的情况下,当采用两个谐振电路时的滤除量是-32.8dB,并且因此能够看到滤除量小于当采用一个谐振电路时的滤除量-36.7dB。另外,能够看到,在(L_GND_ISO/L_GND=0.5)的情况下,一个谐振电路的情况下的滤除量和两个谐振电路的情况下的滤除量变为等于-36.7dB。在(L_GND_ISO/L_GND>0.5)的情况下,通过将谐振电路的数目增加到2来使滤除量变大。
在本实施例中,由于能够获得与(L_GND_ISO/L_GND≥1)相对应的寄生电感比率,所以滤除量变成-40.5dB,其示出与传统的示例相比较滤除量增加了7.7dB。
[第二实施例]
图7是根据本发明的第二实施例的电子装置的横截面图。以与第一实施例相同的方式,根据本实施例的电子装置还包括半导体器件,和用于安装半导体器件的安装基板。同时,在滤波器电路部件的附近的包括封装的电子装置的内部结构的顶视图与图4A的相同,并且因此描述被省略。另外,示出用于在半导体芯片上安装具有滤波器电路部件的根据本实施例的半导体器件的基板的图案与图4B的相同,并且因此描述被省略。换言之,图7是当在A方向中看时沿着虚线的图4B中的安装基板上的图4A中的半导体器件的横截面图。
根据本实施例的电子装置与根据本发明的第一实施例的电子装置之间的区别是安装基板背表面镀图案13。即,在根据本发明的第一实施例的电子装置中,两个谐振电路a和b共享安装基板背表面镀图案13。然而,在根据本实施例的电子装置中,在两个谐振电路a和b之间分隔安装基板背表面镀图案13。
根据本实施例的电子装置的其它构造与本发明的第一实施例的相同,并且因此详细的描述将会被省略。
在本实施例的条件下的模拟结果对应于表1的行中的“第二实施例”和图5的图中的S(8,7)和2f0标记(4)、以及图6的图中的水平轴中对应于值“8”的点。根据这些结果能够理解,根据本实施例,获得基本上等于理想的电路中的滤除量。
将会描述原因。根据本实施例,能够在同一谐振电路中实现关系(L_GND_ISO/L_GND>>1),即,(L_GND_ISO>>L_GND)。结果,基本上能够抑制下述现象,即本质上要通过下降到GND来滤除的频率分量经由谐振电路a、对应的路径18、以及谐振电路b返回而再次出现在滤波器电路输出部件8中。同时,在本实施例中要滤除的频率分量是具有2f0的频率的谐波信号。
如上所述,根据本发明,能够获得下述效果。即,通过抑制由寄生电感引起的谐波分量的滤除量的减少,能够在具有接地线并且形成在半导体芯片上的滤波器电路中获得等于其中没有包括寄生电感的理想情况中滤除量的滤除量。因此,谐波分量的滤除量增加。
尽管结合数个实施例已经描述了本发明,但是对本领域的技术人员来说显然的是,提供这些实施例仅用于示出本发明,并且不应基于其来在限制的意义上解决随附的权利要求。
Claims (6)
1.一种电子装置,包括:
半导体器件;和
安装基板,所述安装基板安装有所述半导体器件并且与预定的电压相连接,
其中所述半导体器件包括滤波器电路部件,所述滤波器电路部件被构造为将输入信号的除了想要的频率分量之外的谐波分量输出到所述安装基板并且将所述想要的频率分量输出到所述滤波器电路部件的输出节点,并且
其中所述滤波器电路部件包括电感器,所述电感器大于所述安装基板中的寄生电感分量。
2.根据权利要求1所述的电子装置,其中所述滤波器电路部件包括为所述谐波分量的频带提供的谐振电路部件。
3.根据权利要求2所述的电子装置,其中所述谐振电路部件包括:
所述电感器;和
电容器,所述电容器与所述电感器串联地连接,
其中所述电感器和所述电容器的组合对应于所述谐波分量的所述频带。
4.根据权利要求3所述的电子装置,其中除了所述谐振电路部件之外,所述滤波器电路部件进一步包括另一谐振电路部件,并且
其中为所述谐波分量的不同于所述频带的另一频带提供所述另一谐振电路部件。
5.根据权利要求4所述的电子装置,其中所述滤波器电路部件包括:
输入部件,所述输入部件被构造为输入所述输入信号;
输出部件,所述输出部件被构造为从所述输出节点输出所述输入信号的所述想要的频率分量;以及
部件间电感器,所述部件间电感器被连接在所述输入部件和所述输出部件之间,
其中所述谐振电路部件和所述另一谐振电路部件的一端分别与所述部件间电感器的末端相连接,并且
其中所述谐振电路部件和所述另一谐振电路部件的另一端与所述安装基板中的所述寄生电感分量的末端相连接。
6.根据权利要求5所述的电子装置,其中所述安装基板包括:
第一背表面接地图案,所述第一背表面接地图案与所述寄生电感分量的末端中的一个相连接;和
第二背表面接地图案,所述第二背表面接地图案与所述寄生电感分量的另一端相连接,并且
其中所述第一和第二背表面接地图案相互绝缘。
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