CN102030303B - Microstructure manufacturing method - Google Patents
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- CN102030303B CN102030303B CN 200910174511 CN200910174511A CN102030303B CN 102030303 B CN102030303 B CN 102030303B CN 200910174511 CN200910174511 CN 200910174511 CN 200910174511 A CN200910174511 A CN 200910174511A CN 102030303 B CN102030303 B CN 102030303B
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Abstract
The invention relates to a microstructure manufacturing method applied to a semiconductor manufacturing process. The microstructure manufacturing method comprises the following steps of: forming an insulating layer containing a microstructure, a plurality of metal circuits and a metal connecting layer on a silicon substrate, wherein the microstructure and the metal circuits are parallelly arranged in the insulating layer, and the metal connecting layer is electrically connected with the metal circuits and is exposed out of the surface of the insulating layer; and depositing a protective layer on the metal connecting layer and the surface of the insulating layer, and etching to suspend the microstructure. Therefore, the microstructure and the metal connecting layer are prevented from being corroded and damaged by etching liquid.
Description
Technical field
The invention relates to a kind of arrangement of semiconductors and manufacture method, and particularly relevant for a kind of miniature suspension structure and manufacture method thereof.
Background technology
MEMS (Micro-Electro-Mechanical Systems, MEMS) comprises various micro-structural now.For example, Immobile probe, runner, opening structure, or the structure such as some movable springs, connecting rod, gear.Above-mentioned different micro-structural and relevant semiconductor circuit are integrated mutually, can be consisted of various semiconductor application.Semiconductor circuit is complementary metal oxide layer semiconductor (Complementary Metal-Oxide Semiconductor, CMOS) for example.And promote the various function of micro-structural by manufacture method and structural design, and be the crucial pointer of following semiconductor micro electromechanical system, the severe challenge when being also following further research chip.Therefore, if can research and develop the known technology of improving, following expansionary reality can't be estimated.
At present the sensor in microelectromechanicdevices devices and actuator all are independent of outside semiconductor subassembly and make, and must utilize the micro electronmechanical operation of the special use such as wet etching, dry ecthing and sacrifice layer (sacrificial-layer) removal to produce floated structure on silicon base.Wherein, wet etching is a kind of etching mode fast and effectively, mainly utilize the chemical reaction of etchant and storeroom to reach etched effect, and the etchant that uses only can react with certain material usually, therefore has quite high " selectively " (selectivity) for different materials.Yet, because chemical reaction can't have any preference to specific direction, so wet etching belongs in essence a kind of " isotropic etching " (isotropic etching).Isotropic etching means that wet etching not only can vertically carrying out etching, also have horizontal etch effect.Horizontal etch effect can cause what is called " lateral erosion " phenomenon (undercut) to occur.
And dry ecthing, plasma etching for example, be utilize partial solution from gas carry out, great advantage is namely that dry ecthing is " anisotropic etching " (anisotropic etching).Yet, be mainly the shock removing materials that utilizes ion due to dry ecthing, belong to a kind of physical action, so dry ecthing it is selectively low than wet etching for different materials.
In micro-structural commonly used, its metallic circuit is for being embedded in insulating barrier, and need utilize metal connecting layer with metallic circuit and the electric connection of other external conductor structure, makes metal connecting layer for directly being exposed to outside insulating barrier.In addition, usually can be when forming micro-structural, in micro-structural week side laying metal stack structure, recycling subsequent etch metal stack structure reaches micro-structural and suspends.Thus, in the metal etch process of carrying out the micro-structural suspension, metal connecting layer just easily weathers simultaneously and wrecks.
Moreover in etching process, etching solution also easily directly corrodes not shielded micro-structural, and structure is damaged.In addition, micro-electromechanical technology can be protected not etched zone with light shield usually, but along with the design of micro-electromechanical technology is more and more meticulousr, also causes the manufacturing of photomask more and more to be not easy.Therefore, how to allow metal connecting layer and micro-structural be protected in etching process, and how to adopt substituting photomask can carry out the emphasis place that fine etching is present utmost point wish solution.
Summary of the invention
Therefore, but a purpose of the present invention is to provide a kind of micro-electromechanical pretreatment manufacturing method for manufacturing of integrating semiconductor processing, avoiding for the metal connecting layer that is electrically connected with external conductor by improper etching, and is damaged.
According to above-mentioned purpose of the present invention, a kind of method for manufacturing microstructure that is applied to manufacture of semiconductor is proposed.This method for manufacturing microstructure comprises the following steps.At first form and contain the insulating barrier of micro-structural, a plurality of metallic circuit and metal connecting layer on silicon base.Wherein micro-structural is parallel with metallic circuit side by side in insulating barrier, and metal connecting layer and metallic circuit are electrically connected, and metal connecting layer exposes to surface of insulating layer.Afterwards, at metal connecting layer and surface of insulating layer deposition protective layer, and make micro-structural reach suspension with etching.
But another object of the present invention is to provide a kind of micro-electromechanical pretreatment manufacturing method for manufacturing of integrating semiconductor processing, no matter utilize from top to bottom etching, or from bottom to top etching, all can avoid micro-structural to be avoided being damaged by improper etching.And utilize protective layer to replace photomask and carry out etching, simplify and use the required cost of accurate light shield in general processing procedure.
According to above-mentioned purpose of the present invention, a kind of method for manufacturing microstructure that is applied to manufacture of semiconductor is proposed.This method for manufacturing microstructure comprises the following steps.At first form and contain the insulating barrier of micro-structural, a plurality of metallic circuit, a plurality of metal stack and metal connecting layer on silicon base.Wherein micro-structural is parallel with metallic circuit side by side in insulating barrier, and metal stack is positioned at all sides of micro-structural, and metal connecting layer and metallic circuit are electrically connected, and metal connecting layer exposes to surface of insulating layer.Then, at metal connecting layer and surface of insulating layer deposition protective layer, then etching removes the corresponding protective layer that is positioned on metal stack and micro-structural.Metal stack is removed in etching, connects the etching space of insulating barrier with formation, then by the substrate of etching space etching silicon, makes etching space extend to silicon base.Then, after on protective layer, over cap being set, by silicon base bottom surface etching silicon substrate, so that the substrate of etching space through-silicon makes micro-structural suspend.At last, remove the corresponding over cap that is positioned on metal connecting layer, then remove with etching the protective layer that is positioned on metal connecting layer, so that metal connecting layer exposes to surface of insulating layer, and utilize routing to be electrically connected metal connecting layer and external conductor.
According to above-mentioned purpose of the present invention, a kind of method for manufacturing microstructure that is applied to manufacture of semiconductor.This method for manufacturing microstructure comprises the following steps.At first form and contain the insulating barrier of micro-structural, a plurality of metallic circuit, a plurality of metal stack and metal connecting layer on silicon base.Wherein micro-structural is parallel with metallic circuit side by side in insulating barrier, and metal stack is positioned at all sides of micro-structural, and metal connecting layer and metallic circuit are electrically connected, and metal connecting layer exposes to surface of insulating layer.Then, at metal connecting layer and surface of insulating layer deposition protective layer, then remove the corresponding protective layer that is positioned on metal stack and micro-structural with etching.Then, metal stack is removed in etching, connects the etching space of insulating barrier with formation, then by the substrate of etching space etching silicon, so that micro-structural suspends.Next, over cap is set on protective layer, and removes the corresponding over cap that is positioned on metal connecting layer, then the protective layer that is positioned on metal connecting layer is removed in etching, so that metal connecting layer exposes to surface of insulating layer.At last, utilize routing to be electrically connected metal connecting layer and external conductor.
Use method for manufacturing microstructure utilization deposition protective layer of the present invention and effectively avoid micro-structural and metal connecting layer to suffer that in etching process etching destroys, and replace the use of precise light mask in the past with protective layer, can reduce the processing procedure cost.
Description of drawings
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, appended the description of the drawings is as follows:
Fig. 1 is the section of structure that illustrates according to a kind of each step of method for manufacturing microstructure of an embodiment of the present invention;
Fig. 2 is the section of structure that illustrates when in Fig. 1, step 110 is carried out;
Fig. 3 is the section of structure that illustrates when in Fig. 1, step 120 is carried out;
Fig. 4 is the detailed step flow chart that illustrates step 130 in Fig. 1;
Fig. 5 to Figure 11 is the section of structure that illustrates when in Fig. 4, step 131a～137a carries out;
Figure 12 to Figure 15 is the section of structure that illustrates when in Fig. 4, step 131b～136b carries out.
[primary clustering symbol description]
100: method 110: step
120: step 130: step
131a～137a: step 131b～136b: step
200: silicon base 201: etching space
300: insulating barrier 301: etching space
310: micro-structural 320: metallic circuit
330: metal stack 340: metal connecting layer
350: 400: the first protective layer of complementary metal oxide semiconductor circuit layer
700: adhesion layer
The specific embodiment
Fig. 1 is the section of structure that illustrates according to a kind of each step of method for manufacturing microstructure of an embodiment of the present invention.Method for manufacturing microstructure 100 is contained in and forms the three large steps such as insulating barrier (step 110), deposition protective layer (step 120) and etching microactuator suspension structure (step 130) that contain micro-structural, metallic circuit and metal connecting layer on silicon base.The method for manufacturing microstructure of present embodiment can be applicable in manufacture of semiconductor, and manufacture of semiconductor is complementary metal oxide layer semiconductor (Complementary Metal-OxideSemiconductor, CMOS) processing procedure for example.The manufacturing of micro-structural and manufacture of semiconductor are integrated in same processing procedure to carry out.
Then, please refer to Fig. 2 and Fig. 3, it is for illustrating respectively the section of structure of step 110 and step 120 in Fig. 1, so as to the detailed content of explanation micro-structural processing method.At first, please refer to Fig. 2.Form insulating barrier 300 (step 110) on silicon base 200.Have micro-structural 310, a plurality of metallic circuit 320, a plurality of metal stack 330, metal connecting layer 340 and at least one complementary metal oxide semiconductor circuit layer 350 in insulating barrier 300.Micro-structural 310, metallic circuit 320 and complementary metal oxide semiconductor circuit layer 350 are parallel side by side in insulating barrier 300, and all are subject to the coating of insulating barrier 300.
After aforementioned structure formed, last at the standard semiconductor processing procedure was at the first protective layer 400 of insulating barrier 300 surface deposition passivation materials.The depositional mode of the first protective layer 400 is for adopting plasma-assisted chemical vapour deposition (Plasma-Enhanced Chemical Vapor Deposition; PECVD), aumospheric pressure cvd (Atmospheric pressure Chemical Vapor Deposition; APCVD) or low-pressure chemical vapor deposition (Low-pressure Chemical Vapor Deposition, LPCVD).Then, utilize the technology such as exposure, development and etching make the specific region expose and not covered by the first protective layer 400.Aforementioned specific region comprises metal stack 330 surfaces, metal connecting layer 340 surfaces and insulating barrier 300 surfaces that coat micro-structural 310, as shown in Figure 1.
Then, please refer to Fig. 3.On aforementioned specific region of exposing with the second protective layer 500 (step 130) of the first protective layer 400 surface deposition oxidation materials.The depositional mode of the second protective layer 500 can adopt plasma-assisted chemical vapour deposition (Plasma-Enhanced Chemical Vapor Deposition equally; PECVD), aumospheric pressure cvd (Atmospheric pressure Chemical Vapor Deposition; APCVD) or low-pressure chemical vapor deposition (Low-pressure Chemical Vapor Deposition, LPCVD).
Fig. 4 is for illustrating the detailed step flow chart of step 130 in Fig. 1.At first, please coordinate simultaneously with reference to Fig. 5 to Figure 11, it is the section of structure that illustrates when in Fig. 4, step 131a～137a carries out.After aforementioned the second protective layer 500 depositions are complete; remove the second protective layer 500 (step 131) of the specific regions such as surface of insulating layer of metal stack 330 surfaces and this micro-structural 310 of coating with etching; make whereby the aforementioned metal connecting layer that exposes 340 surfaces and the first protective layer 400 be subjected to the covering of the second protective layer 500, as shown in Figure 5.
Then, as shown in Figure 6, utilize etching that metal stack 330 is removed, making originally, the position of metal stack 330 forms an etching space 301 (step 132) that only passes through insulating barrier 300.And in etching process, the part that is covered by the second protective layer 500 replaces photoresist commonly used and avoids suffering etching to corrode with the second protective layer 500.In addition, be with insulating barrier 300 because micro-structural 310 is outer and coat, therefore, after 330 etchings of metal bolt stack layer are removed, can't expose the micro-structural 310 in insulating barrier 300.
Next please refer to shown in Figure 7, utilize the high etching selectivity of 300 pairs of silicon base 200 of insulating barrier, carry out deep reactive ion etch (Deep Reactive Ion Etching by 301 pairs of silicon base of etching space 300, DRIE), remove local silicon substrate (step 133a), make etching space 301 extend to silicon base 200, form the etching space 201 that not yet connects silicon base 200.In etching process, because the second protective layer 500 is not removed, the part that is therefore covered by the second protective layer 500 still can replace photoresist commonly used and avoid suffering etching to corrode by the second protective layer 500 equally.In addition, be subject to too the protection of insulating barrier 300 due to micro-structural 310, also can avoid destroyed by etching.
Then, please refer to Fig. 8.Over cap 600 (step 134a) is set, and 500 of over cap 600 and the second protective layers see through adhesion layer 700 combinations on the second protective layer 500, make between over cap 600 and the second protective layer 500 specific range apart.Over cap 600 can be glass or silicon wafer, and the surface of over cap 600 can arrange one deck epoxides, makes over cap 600 avoid being damaged under encapsulation pressure due to the elastic buffer of going back oxide.In addition, required because of general manufacture of semiconductor, silicon base 200 all needs wear down to the thickness below 300um.But the thinner easy stress of silicon base 200 and produce warpage.Therefore, over cap 600 also in silicon base 200 another sides as support, to avoid the overall structure damage of breaking in processing procedure, improve the processing procedure qualification rate.
Come again, as shown in Figure 9, by carrying out etching (step 135a) with respect to etching space 201,301 silicon base 200 bottom surfaces, remove the silicon base 200 with respect to micro-structural 310 belows, and make etching space 201,301 through-silicon substrates, with microactuator suspension structure 310.Due within aforementioned micro-structural 310 is coated on insulating barrier 300, therefore, in etching process, micro-structural 310 can not be subject to etched destruction.Moreover, also can avoid spilling by micro-structural 310 inside the metallic particles that pollutes the board cavity.
Then, as shown in figure 10, according to micro-structural 310 cutting over caps 600 (step 136a), and remove the corresponding over cap 600 that is positioned at metal connecting layer 340 tops, make the second protective layer 500 of metal connecting layer 340 tops exposed.Therefore still be subject to the covering of the second protective layer 500 due to metal connecting layer 340, in the time of cutting over cap 600, can't hurt metal connecting layer 340.
Next, substitute as the light shield of metal connecting layer 340 with exterior domain with over cap 600, directly with the second protective layer 500 (step 137a) on etching removal metal connecting layer 340, with bare metal articulamentum 340, as shown in figure 11.Be subject to the protection of insulating barrier and over cap due to micro-structural, therefore can begin to avoid in etching process for structure being corroded.Moreover, therefore because the first protective layer 400 is different from the material of the second protective layer 500, can utilize the etching selectivity of oxide and nitride, allow metal connecting layer 340 specific region in addition still be subject to the covering of the first protective layer 400 and to avoid being subject to etching.At last, after with routing, metal connecting layer 340 and external conductor (not illustrating) being electrically connected, making metallic circuit 320 can see through routing (not illustrating) and metal connecting layer 340 and external conductor and carry out the signal transmission.Routing technology as used herein and external conductor are all general technology commonly used, not in this detailed description.
Figure 12 to Figure 15 for illustrating respectively the section of structure when in Fig. 4, step 131b～136b carries out, is a kind of method for manufacturing microstructure of another embodiment of the present invention.Roughly step is all identical with aforementioned embodiments, and difference is that aforementioned embodiments is after over cap is set, then is carried out etching and made micro-structural suspend (as earlier figures 8 and shown in Figure 9) by the silicon base bottom surface.Present embodiment is that over cap 600 (step 134b) is set is front; during by etching space 301 etching silicon substrate 200; namely utilize isotropic etching along silicon base 200 lattice planes, etching space 301 to be extended to the silicon base 200 of micro-structural 310 belows; suspend (step 133b) and reach micro-structural 310, as shown in figure 12.
Then, then arrange on the second protective layer 500 over cap 600 (step 134b, as shown in figure 13).Then according to micro-structural 310 cutting over caps 600, and remove the corresponding over cap 600 that is positioned at metal connecting layer 340 tops, make the second protective layer 500 of metal connecting layer 340 tops exposed (step 135b, as shown in figure 14).At last, substitute as the light shield of metal connecting layer 340 with exterior domain with over cap 600, directly remove the second protective layer 500 on metal connecting layer 340 with etching, with bare metal articulamentum 340 (step 136b, as shown in figure 15).Because Figure 13 in this embodiment is all identical with aforementioned embodiments to the step of section of structure representative shown in Figure 15, therefore again do not describe in detail at this.
By the invention described above embodiment as can be known, use method for manufacturing microstructure of the present invention and have following advantages.The first, in etching process, effectively avoid metal connecting layer and micro-structural to be subject to improper erosion damage.No matter and be to adopt from top to bottom etching or from bottom to top etching, etching solution all can't directly corrode micro-structural, avoids the metal exposed of micro-structural to wreck, and produces the metallic particles that pollutes the board cavity.The second, the precise light masking effect that utilizes the protective layer of oxide or nitride deposition and over cap to replace in the past carries out etching, micro-structural is reached suspend and remove the protective layer on metal connecting layer, and then alleviates and use the spent cost of photomask.The 3rd, when carrying out the over cap cutting, still be protected the protection of layer due to metal connecting layer, and it is damaged to avoid incised wound.The 4th, the setting of over cap provides support to resist stress for silicon base and insulating barrier, improves the processing procedure qualification rate.
Although the present invention discloses as above with embodiment; so it is not to limit the present invention, any person skilled in the art, without departing from the spirit and scope of the present invention; when can be used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the scope that claims define.
Claims (8)
1. a method for manufacturing microstructure, be applied to manufacture of semiconductor, and this method for manufacturing microstructure comprises:
Formation contains an insulating barrier of a micro-structural, a plurality of metallic circuit and a metal connecting layer on a silicon base, wherein this micro-structural is parallel with described a plurality of metallic circuits side by side in this insulating barrier, this metal connecting layer and described a plurality of metallic circuit are electrically connected, and this metal connecting layer exposes to this surface of insulating layer;
Deposit a protective layer in this metal connecting layer and this surface of insulating layer;
Etching this micro-structural that suspends;
It is characterized in that, also comprise:
When forming this insulating barrier, form a plurality of metal stack in all sides of this micro-structural;
After this protective layer of deposition, etching removes corresponding this protective layer that is positioned on described a plurality of metal stack and this micro-structural;
Described a plurality of metal stack are removed in etching, to form an etching space that connects this insulating barrier;
By this this silicon base of etching space etching, make this etching space extend to this silicon base;
One over cap is set on this protective layer; And
By this this silicon base of silicon base bottom surface etching, so that running through this silicon base, this etching space make this micro-structural suspend.
2. method for manufacturing microstructure according to claim 1, is characterized in that, over cap is a glass cover or a silicon wafer.
3. method for manufacturing microstructure according to claim 1, is characterized in that, this over cap surface has an epoxides.
4. method for manufacturing microstructure according to claim 1, is characterized in that, also comprises:
Remove corresponding this over cap that is positioned on this metal connecting layer;
The protective layer that is positioned on this metal connecting layer is removed in etching, so that this metal connecting layer exposes to this surface of insulating layer; And
Utilize routing to be electrically connected this metal connecting layer and an external conductor.
5. method for manufacturing microstructure according to claim 4, is characterized in that, over cap is a glass cover or a silicon wafer.
6. method for manufacturing microstructure according to claim 4, is characterized in that, this over cap surface has an epoxides.
7. a method for manufacturing microstructure, be applied to manufacture of semiconductor, it is characterized in that, this method for manufacturing microstructure comprises:
Formation contains an insulating barrier of a micro-structural, a plurality of metallic circuit, a plurality of metal stack and a metal connecting layer on a silicon base, wherein this micro-structural is parallel with described a plurality of metallic circuits side by side in this insulating barrier, described a plurality of metal stack is positioned at all sides of this micro-structural, this metal connecting layer and described a plurality of metallic circuit are electrically connected, and this metal connecting layer exposes to this surface of insulating layer;
Deposit a protective layer in this metal connecting layer and this surface of insulating layer;
Etching removes corresponding this protective layer that is positioned on described a plurality of metal stack and this micro-structural;
Described a plurality of metal stack are removed in etching, to form an etching space that connects this insulating barrier;
By this this silicon base of etching space etching, make this etching space extend to this silicon base;
One over cap is set on this protective layer;
By this this silicon base of silicon base bottom surface etching, so that running through this silicon base, this etching space make this micro-structural suspend;
Remove corresponding this over cap that is positioned on this metal connecting layer;
The protective layer that is positioned on this metal connecting layer is removed in etching, so that this metal connecting layer exposes to this surface of insulating layer; And
Utilize routing to be electrically connected this metal connecting layer and an external conductor.
8. a method for manufacturing microstructure, be applied to manufacture of semiconductor, it is characterized in that, this method for manufacturing microstructure comprises:
Formation contains an insulating barrier of a micro-structural, a plurality of metallic circuit, a plurality of metal stack and a metal connecting layer on a silicon base, wherein this micro-structural is parallel with described a plurality of metallic circuits side by side in this insulating barrier, described a plurality of metal stack is positioned at all sides of this micro-structural, this metal connecting layer and described a plurality of metallic circuit are electrically connected, and this metal connecting layer exposes to this surface of insulating layer;
Deposit a protective layer in this metal connecting layer and this surface of insulating layer;
Etching removes corresponding this protective layer that is positioned on described a plurality of metal stack and this micro-structural;
Described a plurality of metal stack are removed in etching, to form an etching space that connects this insulating barrier;
By this this silicon base of etching space etching, so that this micro-structural suspends;
One over cap is set on this protective layer;
Remove corresponding this over cap that is positioned on this metal connecting layer;
The protective layer that is positioned on this metal connecting layer is removed in etching, so that this metal connecting layer exposes to this surface of insulating layer; And
Utilize routing to be electrically connected this metal connecting layer and an external conductor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910174511 CN102030303B (en) | 2009-09-28 | 2009-09-28 | Microstructure manufacturing method |
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| CN 200910174511 CN102030303B (en) | 2009-09-28 | 2009-09-28 | Microstructure manufacturing method |
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| CN102030303A CN102030303A (en) | 2011-04-27 |
| CN102030303B true CN102030303B (en) | 2013-05-22 |
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| CN 200910174511 Expired - Fee Related CN102030303B (en) | 2009-09-28 | 2009-09-28 | Microstructure manufacturing method |
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