CN101638213B - Micro structural manufacture method capable of integrating semiconductor processing - Google Patents
Micro structural manufacture method capable of integrating semiconductor processing Download PDFInfo
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- CN101638213B CN101638213B CN 200810145283 CN200810145283A CN101638213B CN 101638213 B CN101638213 B CN 101638213B CN 200810145283 CN200810145283 CN 200810145283 CN 200810145283 A CN200810145283 A CN 200810145283A CN 101638213 B CN101638213 B CN 101638213B
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Abstract
The invention discloses a micro structural manufacture method capable of integrating semiconductor processing, comprising the following steps of generating an insulating layer on the surface of a silica-based layer, and the insulating layer is provided with at least one mutually-independent micro structures and a plurality of metal circuits; etching the micro structures and the metal circuits coated by the insulating layer, generating one metal connecting layer electrically connected with the metal circuits and an outer conductor on insulating layer; exposing the metal connecting layer out of the surface of the insulating layer to be coated by a protection layer for etching; and avoiding the micro structures and the metal connecting layer from being eroded and damaged by etchant.
Description
Technical field
The present invention relates to a kind of method for manufacturing microstructure, but be specifically related to a kind of method for manufacturing microstructure of integrating semiconductor processing, it can effectively avoid micro-structural and the improper erosion damage of metal.
Background technology
Existing semiconductor micro electromechanical system comprises various miniature semiconductor structure, for example: Immobile probe, runner, opening structure, or some movable springs, connecting rod, gear structures such as (rigid motion or flexible deformation).
Above-mentioned various structure is integrated with relevant semiconductor circuit each other, can be constituted various semiconductor application; Promoting the various function of micro mechanical structure by manufacturing approach, is the crucial pointer of following semiconductor micro electromechanical system, the severe challenge when also being following further research chip; If can research and develop the technology of improving convention, development in future property can't be estimated in fact.
Make micro-electro-mechanical sensors and actuator system at present and all need on silicon base layer, produce floated structure; Aforementioned processing procedure must adopt advanced semiconductor technology, for example: micro electronmechanical special operations such as wet etching, dry ecthing and sacrifice layer (sacrificial layer) removal.
Wet etching is a kind of effectively etching fast, and the etchant of unlikely other material of etching (etchant), and therefore, wet etching can have quite high selectivity (selectivity) to different materials usually.Yet except crystallization direction possibly influence the etch-rate, because chemical reaction can't have any preference to specific direction, so wet etching is a kind of isotropic etching (isotropic etching) in essence.Isotropic etching means that wet etching not only can vertically carry out etching, and has horizontal etch effect.Lateral etches can cause the phenomenon of so-called lateral erosion (undercut) to take place.
Opposite, in dry ecthing (electric paste etching), the electricity slurry is the gas that a kind of part is dissociated, the dry ecthing great advantage promptly is anisotropic etching (anisotropic etching).Yet the selectivity of dry ecthing is but come lowly (because the etching mechanism of dry ecthing is a kind of physical interaction basically than wet etching; Therefore the bump of ion not only can remove etched film, also can remove shielding simultaneously).
Have now a silicon base layer upper surface form at least one in the insulating barrier of tool micro electromechanical structure, micro electromechanical structure comprises at least one micro-structural and a plurality of metallic circuit, aforementioned existing structure is further analyzed, and still has following point:
Problem one: existing insulating barrier is provided with metal connecting layer; Metal connecting layer electrically links with metallic circuit; When insulating barrier carries out etching; Not shielded metal connecting layer will wreck structure because of weathering, and be that the emphasis that present utmost point desire solves belongs to so how effectively to protect metal connecting layer to avoid suffering improper erosion.
Problem two: when existing micro-structural is carried out etching, etching solution will directly corrode not shielded micro-structural and structure is wrecked, and be that the emphasis that present utmost point desire solves belongs to so how effectively to protect micro-structural to avoid suffering improper erosion.
Problem three: existing micro electromechanical structure must adopt light shield (mask); Can carry out the fine etching technology; But along with the design of micro-electromechanical technology is more and more meticulous; Causing the manufacturing of light shield more and more to be not easy, so not only increase production cost, is the emphasis place that present utmost point desire solves so how to adopt substituting light shield can carry out fine etching.
And in order effectively to solve aforementioned issues associated; Creator of the present invention based on the past at micro electronmechanical (Microelectric Machanic System; MEMS) the field research and development technology and the experience of accumulating; After test for several times and attempting in many ways, but develop the method for manufacturing microstructure that a kind of integrating semiconductor processing finally.
Summary of the invention
But technical problem to be solved by this invention provides a kind of method for manufacturing microstructure of integrating semiconductor processing; It can effectively avoid suffering improper etching with the outside metal connecting layer that is connected; Can effectively avoid micro-structural to expose and suffer improper erosion, and significantly simplify the required precision demand of light shield and then reduce whole cost.
In order to solve above technical problem; But the method for manufacturing microstructure of first kind of integrating semiconductor processing of the present invention comprises the steps: to form insulating barrier at a silicon base layer upper surface; Insulating barrier comprises at least one micro-structural and a plurality of metallic circuit; The metal connecting layer of insulating barrier moulding one and metallic circuit and external conductor electrically connect, metal connecting layer exposes to and covered by a protective layer; The all sides of said micro-structural are provided with a plurality of metal stack layers that covered by said protective layer; The protective layer of said micro-structural and said metal stack laminar surface deposition is removed in etching; And said metal stack layer is carried out etching remove the etching space that connects said insulating barrier to form.
But the method for manufacturing microstructure of second kind of integrating semiconductor processing of the present invention comprises the steps: moulding one insulating barrier on a silicon base layer; Insulating barrier has at least one micro-structural and a plurality of metallic circuit; Let micro-structural and metallic circuit coated by insulating barrier; The metal connecting layer that moulding one and metallic circuit electrically link on the insulating barrier, surface of insulating layer deposits a protective layer, and the protected layer of the metal connecting layer that exposes to surface of insulating layer is covered; The all sides of micro-structural are provided with the metal stack layer that a plurality of protected seams cover; The protective layer of said micro-structural and metal stack laminar surface deposition is removed in etching; The metal stack layer is carried out etching remove the etching space that connects insulating barrier to form; The silicon base layer front is carried out etching and is formed the etching space of non-through silicon base layer still; One over cap is set on the protective layer; The silicon base layer back side is carried out etching and is removed the etching space that forms the perforation insulating barrier; It is logical to let the etching space of etching space and insulating barrier of silicon base layer link up each other, makes micro-structural form suspended state; And over cap cut; The not protected lid of protective layer on the metal connecting layer is covered; Protective layer on the metal connecting layer is carried out etching to be removed; Let metal connecting layer expose to surface of insulating layer, make external conductor see through with the metal connecting layer electrically connect after, make metallic circuit see through routing and external engagement transmission signal.
But the method for manufacturing microstructure of the third integrating semiconductor processing of the present invention comprises the steps: moulding one insulating barrier on a silicon base layer; Insulating barrier has at least one micro-structural and a plurality of metallic circuit; Let micro-structural and metallic circuit coated by insulating barrier; The metal connecting layer that moulding one and metallic circuit electrically link on the insulating barrier, surface of insulating layer deposits a protective layer, and the protected layer of the metal connecting layer that exposes to surface of insulating layer is covered; The all sides of micro-structural are provided with the metal stack layer that a plurality of protected seams cover; The protective layer of said micro-structural and metal stack laminar surface deposition is removed in etching; The metal stack layer is carried out etching remove the etching space that connects insulating barrier to form; Etching space through insulating barrier carries out etch separates to silicon base layer, and said silicon base layer forms the etching space of silicon base layer, makes micro-structural form suspended state; And an over cap is set on the protective layer; Over cap is cut; The not protected lid of protective layer on the metal connecting layer is covered, the protective layer on the metal connecting layer is carried out etching remove, let metal connecting layer expose to surface of insulating layer; Make external conductor see through with the metal connecting layer electrically connect after, make metallic circuit see through routing and external engagement transmission signal.
But the method for manufacturing microstructure of the 4th kind of integrating semiconductor processing of the present invention comprises the steps: the insulating barrier of moulding one tool micro-structural on a silicon base layer; The all sides of micro-structural are provided with a plurality of metal stack layers that covered by a protective layer; The metal stack layer is carried out etching remove the etching space that connects insulating barrier to form; And the etching formation etching space of non-through silicon base layer is still carried out in the silicon base layer front; One over cap is set on the protective layer; The silicon base layer back side is carried out etching and is removed the etching space that forms the perforation silicon base layer; It is logical to let the etching space of etching space and insulating barrier of silicon base layer link up each other, makes micro-structural form suspended state.
But the method for manufacturing microstructure of the 5th kind of integrating semiconductor processing of the present invention comprises the steps: the insulating barrier of moulding one tool micro-structural on a silicon base layer; The all sides of micro-structural are provided with a plurality of metal stack layers that covered by a protective layer; The metal stack layer is carried out etching remove the etching space that connects insulating barrier to form; And silicon base layer being carried out etch separates through the etching space of insulating barrier, said silicon base layer forms the etching space of silicon base layer, makes micro-structural form suspended state.
But the method for manufacturing microstructure of integrating semiconductor processing of the present invention can obtain following effect:
The protected layer protection carrying out of metal connecting layer etching; Let directly attack metal articulamentum of etching solution; Avoid metal connecting layer to wreck; At last again the etched protective layer make external conductor see through with the metal connecting layer electrically connect after, make metallic circuit see through routing and external engagement and carry out the signal transmission.
Micro-structural receives dielectric protection layer to carry out etching, no matter is to adopt from top to bottom etching or from bottom to top etching, and etching solution all can't directly corrode micro-structural, avoids the metal exposed of micro-structural to wreck and produces the metallic particles that pollutes the board cavity.
Protective layer and over cap cover and replace accurate light shield effect and carry out etching, make micro-structural reach suspension, and the protective layer on the metal connecting layer is removed, and then alleviate the cost that uses light shield to expend; And when over cap cut, it is damaged that metal connecting layer avoids incised wound with protected layer protection, and being provided with of over cap will be supported antagonism stress to silicon base layer and insulating barrier in addition, and then avoid the stressed broken process rate that promotes.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
Fig. 1 to Figure 13 is a method for manufacturing microstructure sketch map of the present invention.
Reference numeral is among the figure: 10, silicon base layer; 101, etching space; 11, upper surface; 20, insulating barrier; 201, etching space; 21, micro-structural; 22, metallic circuit; 23, complementary metal oxide semiconductor circuit layer; 24, metal stack layer; 30, metal connecting layer; 40, first protective layer; 50, second protective layer; 60, over cap; 70, adhesion layer 70.
Embodiment
The embodiment of the invention sees also Fig. 1 to shown in Figure 13, but the method for manufacturing microstructure of the present invention's integrating semiconductor processing specifies as follows:
See also shown in Figure 1; At first at a silicon base layer 10 upper surfaces 11 moulding one insulating barrier 20; Insulating barrier 20 can be silicon dioxide; Insulating barrier 20 have at least one micro-structural (Microstructure) 21, a plurality of metallic circuit 22 and a plurality of complementary metal oxide semiconductor (ComplementaryMetal-Oxide-Semiconductor, CMOS) circuit layer 23, micro-structural 21, metallic circuit 22 and complementary metal oxide semiconductor circuit layer 23 are coated by insulating barrier 20 respectively.
Micro-structural 21 all sides are provided with metal stack layer 24; Metal stack layer 24 is formed by mutual storehouses of metal such as aluminium copper, tungsten or titaniums; It is to be used for the etching requisite space that metal stack layer 24 exposes; Metal stack layer 24 adopts and can be etched the material that liquid corrodes, and aforementioned micro-structural 21 is not contacted with metal stack layer 24 down by insulating barrier 20 coatings.
Insulating barrier 20 surface formings one and the metallic circuit 22 electrical metal connecting layer 30 that link, metal connecting layer 30 exposes and can be used to electrically link with external conductor, lets metallic circuit 22 and external conductor carry out signal and links.
See also shown in Figure 2; Insulating barrier 20 is second protective layer 50 of oxidation material in surface deposition one; Second protective layer 50 adopts plasma enhanced chemical vapor deposition (Plasma-Enhanced CVD; PECVD), aumospheric pressure cvd (Atmospheric Pressure CVD; APCVD) or low-pressure chemical vapor deposition (Low-Pressure CVD, LPCVD) etc. technology deposits, and makes the metal stack layer 24, metal connecting layer 30 and first protective layers 40 that expose to insulating barrier 20 surfaces covered by second protective layer 50.
See also shown in Figure 3ly, second protective layer 50 on metal stack layer 24 surface and second protective layers 50 that coat insulating barrier 20 surfaces of micro-structural 21 are carried out etching remove.
See also shown in Figure 4; To 24 etching of metal stack layer (adopting wet etching or dry ecthing); Remove metal stack layer 24 and then form the etching space 201 that connects insulating barrier 20, and in etching process, the part that is still covered by second protective layer 50; To receive second protective layer 50 to avoid being corroded, and the micro-structural 21 that coated by insulating barrier 20 also will be avoided being corroded as the etching reticle protection.
See also shown in Figure 5; Utilize the high etching selectivity of 20 pairs of silicon base layers 10 of insulating barrier, etching is carried out in silicon base layer 10 fronts of the etching space 201 of relative insulating barrier 20 (adopted dark active-ion-etch Deep Reactive Ion Etching, DRIE); Remove local silicon basic unit 10; And then the etching space 101 of the still non-through silicon base layer 10 of formation, and in etching process, the part that is still covered by second protective layer 50; To receive second protective layer 50 to avoid being corroded, and the micro-structural 21 that coated by insulating barrier 20 also will be avoided being corroded as the etching reticle protection.
See also shown in Figure 6ly, be provided with one on second protective layer 50 and be glass or be the over cap 60 of Silicon Wafer, combine through an adhesion layer 70 between over cap 60 and second protective layer 50; And the over cap 60 and second protective layer 50 are each other at a distance of a specific range; Over cap 60 is provided with one deck epoxides (epoxy) in the surface, over cap 60 sees through epoxides elastic buffer encapsulation pressure and avoids damaging, and silicon base layer 10 supports down with insulating barrier 20 protected lids 60; Make silicon base layer 10 and insulating barrier 20 when transporting, will avoid stressed breaking to go to sticks and staves; Because of the required silicon base layer of processing procedure 10 must wear downs below 300um, wear down will stress produce warpage, goes to sticks and staves as supporting to break easily as not using over cap 60; In case damage will be declared the processing procedure failure, cause process rate therefore to reduce.
See also shown in Figure 7; Silicon base layer 10 to the etching space 201 of relative insulating barrier 20 carries out etching (adopting dark active-ion-etch or wet etching) by the back side; Remove local silicon basic unit 10; Make etching space 101 connect silicon base layer 10, make the etching space 101 of silicon base layer 10 coherent each other logical, make micro-structural 21 form suspended state with the etching space 201 of insulating barrier 20; Aforementioned micro-structural 21 is coated down by insulating barrier 20, except as dark active-ion-etch light shield, more can avoid micro-structural 21 inner metallic circuit 22 exposed etchings to spill the metallic particles that pollutes the board cavity.
See also shown in Figure 8ly, cutting over cap 60 covers the not protected lid 60 of second protective layer 50 on the metal connecting layer 30, and over cap 60 carries out etching as the etching light shield to the specific region and removes.
See also shown in Figure 9ly, over cap 60 is in when cutting, and metal connecting layer 30 in 50 protections of second protective layer down; To avoid metal connecting layer 30 to be hurt; Second protective layer 50 on the metal connecting layer 30 carries out etching, lets metal connecting layer 30 expose to insulating barrier 20 surfaces, and in etching process; Micro-structural 21 receives insulating barrier 20 and over cap 60 protections to avoid being corroded; And first protective layer 40 that insulating barrier 20 sees through surperficial specific region carries out etching, utilizes the etching selectivity of oxide layer and nitration case, lets the specific region see through first protective layer 40 and protects and avoid being corroded; Make external conductor see through with metal connecting layer 30 electrically connects after, make metallic circuit 22 see through routing and external engagement is carried out transmission signal.
Another that following Figure 10 to Figure 13 is Fig. 6 to Fig. 9 implemented aspect:
See also shown in Figure 10; Employing waits tropism's dry ecthing or wet etching to form etching space 101 along silicon base layer 10 lattice plane etch separates silicon base layers 10, makes micro-structural 21 form suspended state, or; Adopt the parameter of the not long sidewall protection of dark active-ion-etch; Etching space 101 to silicon base layer 10 carries out etch separates silicon base layer 10 formation etching spaces 101, makes micro-structural 21 form suspended states, and aforementioned micro-structural 21 is coated down by insulating barrier 20; Except as the etching light shield, more can avoid micro-structural 21 inner metallic circuit 22 exposed etchings to spill the metallic particles that pollutes the board cavity.
See also shown in Figure 11ly, be provided with one on second protective layer 50 and be glass or be the over cap 60 of Silicon Wafer, combine through an adhesion layer 70 between over cap 60 and second protective layer 50; And the over cap 60 and second protective layer 50 are each other at a distance of a specific range; Over cap 60 is provided with one deck epoxides (epoxy) in the surface, over cap 60 sees through epoxides elastic buffer encapsulation pressure and avoids damaging, and silicon base layer 10 supports down with insulating barrier 20 protected lids 60; Make silicon base layer 10 and insulating barrier 20 when transporting, will avoid stressed breaking to go to sticks and staves; Because of the required silicon base layer of processing procedure 10 must wear downs below 300um, wear down will stress produce warpage, goes to sticks and staves as supporting to break easily as not using over cap 60; In case damage will be declared the processing procedure failure, cause process rate therefore to reduce.
See also shown in Figure 12ly, cutting over cap 60 covers the not protected lid 60 of second protective layer 50 on the metal connecting layer 30, and over cap 60 carries out etching as the etching light shield to the specific region and removes.
See also shown in Figure 13ly, over cap 60 is in when cutting, and metal connecting layer 30 in 50 protections of second protective layer down; To avoid metal connecting layer 30 to be hurt; Second protective layer 50 on the metal connecting layer 30 carries out etching, lets metal connecting layer 30 expose to insulating barrier 20 surfaces, and in etching process; Micro-structural 21 receives insulating barrier 20 and over cap 60 protections to avoid being corroded; And first protective layer 40 that insulating barrier 20 sees through surperficial specific region carries out etching, utilizes the etching selectivity of oxide layer and nitration case, lets the specific region see through first protective layer 40 and protects and avoid being corroded; Make external conductor see through with metal connecting layer 30 electrically connects after, make metallic circuit 22 see through routing and external engagement is carried out transmission signal.
Claims (9)
1. but the method for manufacturing microstructure of an integrating semiconductor processing; It is characterized in that, comprise the steps:
Moulding one insulating barrier on a silicon base layer; Said insulating barrier has at least one micro-structural and a plurality of metallic circuit; Let said micro-structural and metallic circuit coated by said insulating barrier; The metal connecting layer that moulding one and said metallic circuit electrically link on the said insulating barrier, said surface of insulating layer deposits a protective layer, makes the said metal connecting layer that exposes to said surface of insulating layer covered by said protective layer;
The all sides of said micro-structural are provided with a plurality of metal stack layers that covered by said protective layer;
The protective layer of said micro-structural and said metal stack laminar surface deposition is removed in etching; And
Said metal stack layer is carried out etching remove the etching space that connects said insulating barrier to form.
2. but the method for manufacturing microstructure of integrating semiconductor processing as claimed in claim 1 is characterized in that,
Said silicon base layer front is carried out etching and is formed the etching space of non-through said silicon base layer still; One over cap is set on the said protective layer; The said silicon base layer back side is carried out etching and is removed the etching space that forms the said silicon base layer of perforation; It is logical to let the etching space of etching space and said insulating barrier of said silicon base layer link up each other, makes said micro-structural form suspended state.
3. but the method for manufacturing microstructure of integrating semiconductor processing as claimed in claim 2; It is characterized in that, said over cap is cut, make the protective layer on the said metal connecting layer not covered by said over cap; Protective layer on the said metal connecting layer is carried out etching to be removed; Let said metal connecting layer expose to said surface of insulating layer, make external conductor see through with said metal connecting layer electrically connect after, make said metallic circuit see through routing and external engagement transmission signal.
4. but the method for manufacturing microstructure of integrating semiconductor processing as claimed in claim 1 is characterized in that,
Etching space through said insulating barrier carries out etch separates to said silicon base layer, and said silicon base layer forms the etching space of silicon base layer, makes said micro-structural form suspended state.
5. but the method for manufacturing microstructure of integrating semiconductor processing as claimed in claim 4; It is characterized in that; One over cap is set on the said protective layer, said over cap is cut, make the protective layer on the said metal connecting layer not covered by this over cap; Protective layer on the said metal connecting layer is carried out etching to be removed; Let said metal connecting layer expose to said surface of insulating layer, make external conductor see through with said metal connecting layer electrically connect after, make said metallic circuit see through routing and external engagement transmission signal.
6. but the method for manufacturing microstructure of an integrating semiconductor processing is characterized in that, comprises the steps:
Moulding one insulating barrier on a silicon base layer; Said insulating barrier has at least one micro-structural and a plurality of metallic circuit; Let said micro-structural and metallic circuit coated by said insulating barrier; The metal connecting layer that moulding one and said metallic circuit electrically link on the said insulating barrier, said surface of insulating layer deposits a protective layer, makes the said metal connecting layer that exposes to said surface of insulating layer covered by said protective layer;
The all sides of said micro-structural are provided with a plurality of metal stack layers that covered by said protective layer;
The protective layer of said micro-structural and said metal stack laminar surface deposition is removed in etching;
Said metal stack layer is carried out etching remove the etching space that connects said insulating barrier to form;
Said silicon base layer front is carried out etching and is formed the etching space of non-through said silicon base layer still; One over cap is set on the said protective layer; The said silicon base layer back side is carried out etching and is removed the etching space that forms the said insulating barrier of perforation; It is logical to let the etching space of etching space and said insulating barrier of said silicon base layer link up each other, makes said micro-structural form suspended state; And
Said over cap is cut; Make the protective layer on the said metal connecting layer not covered by said over cap; Protective layer on the said metal connecting layer is carried out etching to be removed; Let said metal connecting layer expose to said surface of insulating layer, make external conductor see through with said metal connecting layer electrically connect after, make said metallic circuit see through routing and external engagement transmission signal.
7. but the method for manufacturing microstructure of an integrating semiconductor processing is characterized in that, comprises the steps:
Moulding one insulating barrier on a silicon base layer; Said insulating barrier has at least one micro-structural and a plurality of metallic circuit; Let said micro-structural and metallic circuit coated by said insulating barrier; The metal connecting layer that moulding one and said metallic circuit electrically link on the said insulating barrier, said surface of insulating layer deposits a protective layer, makes to expose to
The said metal connecting layer of said surface of insulating layer is covered by said protective layer;
The all sides of said micro-structural are provided with a plurality of metal stack layers that covered by said protective layer;
The protective layer of said micro-structural and said metal stack laminar surface deposition is removed in etching;
Said metal stack layer is carried out etching remove the etching space that connects said insulating barrier to form;
Etching space through said insulating barrier carries out etch separates to said silicon base layer, and said silicon base layer forms the etching space of silicon base layer, makes said micro-structural form suspended state; And
One over cap is set on the said protective layer; Said over cap is cut; Make the protective layer on the said metal connecting layer not covered by said over cap, the protective layer on the said metal connecting layer is carried out etching remove, let said metal connecting layer expose to said surface of insulating layer; Make external conductor see through with said metal connecting layer electrically connect after, make said metallic circuit see through routing and external engagement transmission signal.
8. but the method for manufacturing microstructure of an integrating semiconductor processing is characterized in that, comprises the steps:
The insulating barrier of moulding one tool micro-structural on a silicon base layer;
The all sides of said micro-structural are provided with a plurality of metal stack layers that covered by a protective layer;
Said metal stack layer is carried out etching remove the etching space that connects said insulating barrier to form; And
Said silicon base layer front is carried out etching and is formed the etching space of non-through said silicon base layer still; One over cap is set on the said protective layer; The said silicon base layer back side is carried out etching and is removed the etching space that forms the said silicon base layer of perforation; It is logical to let the etching space of etching space and said insulating barrier of said silicon base layer link up each other, makes said micro-structural form suspended state.
9. but the method for manufacturing microstructure of an integrating semiconductor processing is characterized in that, comprises the steps:
The insulating barrier of moulding one tool micro-structural on a silicon base layer;
The all sides of said micro-structural are provided with a plurality of metal stack layers that covered by a protective layer;
Said metal stack layer is carried out etching remove the etching space that connects said insulating barrier to form; And
Etching space through said insulating barrier carries out etch separates to said silicon base layer, and said silicon base layer forms the etching space of silicon base layer, makes said micro-structural form suspended state.
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| CN102161469B (en) * | 2010-02-21 | 2014-12-10 | 汉积科技股份有限公司 | Method for forming suspending object on monolithic substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1334594A (en) * | 2001-08-24 | 2002-02-06 | 清华大学 | Process for mfg. micromechanical inductor with suspended structure on single surface of silicon substrate |
| CN101164863A (en) * | 2006-10-20 | 2008-04-23 | 精工爱普生株式会社 | Mems device and fabrication method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1334594A (en) * | 2001-08-24 | 2002-02-06 | 清华大学 | Process for mfg. micromechanical inductor with suspended structure on single surface of silicon substrate |
| CN101164863A (en) * | 2006-10-20 | 2008-04-23 | 精工爱普生株式会社 | Mems device and fabrication method thereof |
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| JP特开2000-3980A 2000.01.07 |
| JP特开2008-119792A 2008.05.29 |
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