CN102004718A - Merging unit based on field programmable gate array and microprocessor - Google Patents
Merging unit based on field programmable gate array and microprocessor Download PDFInfo
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- CN102004718A CN102004718A CN201010550203XA CN201010550203A CN102004718A CN 102004718 A CN102004718 A CN 102004718A CN 201010550203X A CN201010550203X A CN 201010550203XA CN 201010550203 A CN201010550203 A CN 201010550203A CN 102004718 A CN102004718 A CN 102004718A
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Abstract
The invention discloses a merging unit based on a field programmable gate array and a microprocessor. The merging unit comprises the microprocessor, a programmable gate array chip, a memory and a flash memory. The microprocessor, the programmable gate array chip, the memory and the flash memory are respectively in two-way connection with a bus, and 1 to 8 MAC are arranged in the programmable gate array chip. In the invention, sampling data processing is completed in MPC (Multimedia Personal Computer) 8247, data is transmitted to an FPGA (Field Programmable Gate Array) after IEC61850 information modeling is completed, and MAC function is realized in the FPGA, thus each PHY (Physical Layer) chip corresponds to one independent MAC, and the problems of data source independence and transmitting jitter are solved.
Description
Technical field:
The invention belongs to microelectronic, relate to a kind of high-voltage ac current high-acruracy survey field electronic mutual inductor merge cells, especially a kind of merge cells and its implementation based on field programmable gate array (FPGA) and microprocessor (PowerPC MPC8247) technology.
Background technology:
The China national grid company proposes " strong intelligent grid " development plan in May, 2009, it is that the strong electrical network that key, at different levels electric network coordination develops is the basis that proposition will be built with the extra-high voltage grid, and its construction is planned to be divided into three phases: 2009-2010 study emphasis intelligent grid development plan is worked; 2011-2015 is the all-round construction stage; 2016-2020 is for leading the improvement stage.And the principal character of whole intelligent grid construction is exactly the application of electronic mutual inductor and IEC61850 stipulations, is weight of emphasis that intelligent grid is built so the electronic mutual inductor merge cells of current intelligent grid development need is satisfied in development.
According to " intelligent substation technology guide rule " Q/GDW383-2009 standard, electronic mutual inductor and merge cells parameters thereof to be had higher requirement, the concrete parameter request of the part of merge cells is as follows:
1) each merge cells should be able to satisfy the requirement of maximum 12 input channels and at least 8 tunnel independence output ports;
2) merge cells should be able to be supported stipulations such as IEC60044-8 (GB-20840.8), IEC61850-9-2 simultaneously, energy flexible configuration when engineering is used;
3) merge cells output protection sampled value should not rely on outside to the time system solve the sampled data stationary problem, require sampled value to send at interval discrete value less than 10us;
4) merge cells output interface type: point-to-point interface (protection, peace from etc.), networking interface (observing and controlling, metering, so record, PMU etc.);
5) merge cells should be supported multiple sample frequency, is used to protect, the output interface sample frequency of observing and controlling is preferably 4000Hz.
Summary of the invention:
The object of the present invention is to provide a kind of merge cells hardware design methods that has provided a kind of based on field programmable gate array (FPGAXC3S500E) and microprocessor (PowerPC MPC8247) technology.
The technical problem to be solved in the present invention:
1. solved and had independent data controller (MAC) more than 8 the tunnel and satisfy IEC61850-9-2 protocol massages output.
2. solve the jitter problem between the multichannel IEC61850-9-2 protocol massages output channel, realized the synchronism (sampled value sends the interval discrete value less than 10us) of multichannel output.
3. be combined the unit by IEC61850-9 and carry out information modeling, realized the merge cells function design that proposes in the new guide rule of national grid.
The objective of the invention is to overcome the shortcoming of above-mentioned prior art, a kind of merge cells based on programmable gate array and microprocessor is provided, comprise microprocessor, programmable gate array chip, storer and flash memory, microprocessor, programmable gate array, storer and flash memory are connected with bus is two-way respectively; Be provided with 1-8 mac controller in the described programmable gate array chip.
Described programmable gate array chip comprises 8 mac controllers, and these 8 mac controllers are connected with the RAM interface is two-way respectively; This programmable gate array chip is used to read the fiber data that collecting unit, other merge cells are sent here, gives microprocessor after also conversion of string, decoding and the checking treatment; Receive the data of microprocessor, the coding back sends to protective device and sampled value network by optical fiber port according to IEC61850-9-2 and IEC60044-7/8 specified standard; Receiving station's end synchronizing signal is made synchronous processing.
The data that FPGA provides are read in described little processing, carry out data processing algorithm and according to the configuration information organized processing data of merge cells device, send to FPGA according to IEC61850-9-2 and IEC60044-7/8 specified standard and handle; Microprocessor also is responsible for supervision, the maintenance of collecting unit operating mode; Little processing also provides one road 100M fiber optic Ethernet interface to be used to connect the GOOSE network; And comprise that program is downloaded, the 10M RJ45 ethernet port of debugging usefulness.
The CPU of MPC8247ZQCMIBA is adopted in described little processing.
Described programmable gate array chip adopts the FPGA of XC3S500E-4PQ208I.
Described storer adopts the SDRAM of S42S32400B-6TI.
Described flash memory adopts the FLASH of S29GL128N90TAI.
The present invention is directed to independent 8 channel sample values and send the interval discrete value less than 10us Ethernet data output requirement, there are two problems if go control to send by CPU link layer mac controller, wherein first problem is the shared mac controllers of a plurality of sendaisles, the another one problem is to send to have jitter problem at interval, and discrete value is probably greater than 10us at interval.Based on above 2 consideration, best solution is to finish sampled data among the MPC8247 that proposes of the present invention to handle, data are delivered among the FPGA after finishing the IEC61850 information modeling, in FPGA, realize the mac controller function, the corresponding mac controller independently of each PHY chip like this, it is independent and send jitter problem well to have solved data source header.
Description of drawings:
Fig. 1 is the hardware elementary diagram of merge cells of the present invention.
Fig. 2 is the position versus figure of mac controller in the merge cells of the present invention and former mac controller.
The independent 8 channel sample values outputs of Fig. 3 (MAC realizes in FPGA).
Fig. 4 is the flow chart of data processing of merge cells of the present invention.
Embodiment:
Below in conjunction with accompanying drawing the present invention is done and to describe in further detail:
Referring to Fig. 1-4, a kind of merge cells based on programmable gate array and microprocessor comprises microprocessor, programmable gate array chip, storer and flash memory, and microprocessor, programmable gate array, storer and flash memory are connected with bus is two-way respectively; Be provided with 1-8 mac controller in the described programmable gate array chip.
Described programmable gate array chip comprises 8 mac controllers, and these 8 mac controllers are connected with the RAM interface is two-way respectively; This programmable gate array chip is used to read the fiber data that collecting unit, other merge cells are sent here, gives microprocessor after also conversion of string, decoding and the checking treatment; Receive the data of microprocessor, the coding back sends to protective device and sampled value network by optical fiber port according to IEC61850-9-2 and IEC60044-7/8 specified standard; Receiving station's end synchronizing signal is made synchronous processing.
The data that FPGA provides are read in described little processing, carry out data processing algorithm and according to the configuration information organized processing data of merge cells device, send according to the IEC61850-9 specified standard; Microprocessor also is responsible for supervision, the maintenance of collecting unit operating mode; Little processing also provides one road 100M fiber optic Ethernet interface to be used to connect the GOOSE network; And comprise that program is downloaded, the 10M RJ45 ethernet port of debugging usefulness.
With reference to Fig. 1, the hardware type selecting in this programme is as follows:
CPU：MPC8247ZQCMIBA；FPGA：XC3S500E-4PQ208I；SDRAM：S42S32400B-6TI；FLASH：S29GL128N90TAI。
Merge cells is mainly used in the digital signal that receives collecting unit, these signals is merged, handles the back export according to IEC 61850 standards.Following function mainly is provided:
A) receive and handle data from the electronic mutual inductor collecting unit, to its decode, verification;
B) merge cells carries out pre-service to the input data, such as the filtering drift;
C) receiving station's end synchronizing signal realizes sample-synchronous in the station;
D) receive the power supply status of each road collecting unit, and handle;
E) merge cells is to meet the external output data of agreement of IEC61850-9-2 regulation;
F) merge cells is exported the FT3 data according to the regulation of IEC60044-8 to other merge cells;
The major function of FPGA is: read the fiber data that collecting unit, other merge cells are sent here, give microprocessor after also conversion of string, decoding and the checking treatment; Receive the data of microprocessor, the coding back sends to protective device and sampled value network by optical fiber port according to IEC61850-9-2 and IEC60044-7/8 specified standard; Receiving station's end synchronizing signal is made synchronous processing.
The data that FPGA provides are read in little processing, carry out data processing algorithm and according to the configuration information organized processing data of merge cells device, send to FPGA according to IEC61850-9-2 and IEC60044-7/8 specified standard and handle; Microprocessor also is responsible for functions such as the supervision, maintenance of collecting unit operating mode; Little processing also provides one road 100M fiber optic Ethernet interface to be used to connect the GOOSE network; And comprise that program is downloaded, the 10M RJ45 ethernet port of debugging usefulness.
SDRAM, FLASH are the essential storeies of microprocessor work.
With reference to Fig. 2, mac controller residing position in system.Realize in the cpu chip of the most of mac controller of the existing scheme in market, and the quantity of mac controller is few and be that being not easy of fixing increases, model hierarchy of the present invention is shown in this figure right side, mac controller realizes that in fpga chip the quantity of mac controller is restricted hardly to be increased according to the requirement of engineering flexible configuration.
With reference to Fig. 3, the independent 8 channel sample values outputs of the present invention (MAC realizes in FPGA).The corresponding respectively data M AC controller separately of a plurality of independent PHY pio chips has thoroughly solved the independent and passage transmission synchronism problem of data source header control.
Above content is to further describing that the present invention did in conjunction with concrete preferred implementation; can not assert that the specific embodiment of the present invention only limits to this; for the general technical staff of the technical field of the invention; without departing from the inventive concept of the premise; can also make some simple deduction or replace, all should be considered as belonging to the present invention and determine scope of patent protection by claims of being submitted to.
Claims (7)
1. merge cells based on programmable gate array and microprocessor, it is characterized in that: comprise microprocessor, programmable gate array chip, storer and flash memory, microprocessor, programmable gate array, storer and flash memory are connected with bus is two-way respectively; Be provided with 1-8 mac controller in the described programmable gate array chip.
2. merge cells as claimed in claim 1 is characterized in that: described programmable gate array chip comprises 8 mac controllers, and these 8 mac controllers are connected with the RAM interface is two-way respectively; This programmable gate array chip is used to read the fiber data that collecting unit, other merge cells are sent here, gives microprocessor after also conversion of string, decoding and the checking treatment; Receive the data of microprocessor, the coding back sends to protective device and sampled value network by optical fiber port according to IEC61850-9-2 and IEC60044-7/8 specified standard; Receiving station's end synchronizing signal is made synchronous processing.
3. merge cells as claimed in claim 1, it is characterized in that: the data that FPGA provides are read in described little processing, carry out data processing algorithm and, send to FPGA according to IEC61850-9-2 and IEC60044-7/8 specified standard and handle according to the configuration information organized processing data of merge cells device; Microprocessor also is responsible for supervision, the maintenance of collecting unit operating mode; Little processing also provides one road 100M fiber optic Ethernet interface to be used to connect the GOOSE network; And comprise that program is downloaded, the 10M RJ45 ethernet port of debugging usefulness.
4. merge cells as claimed in claim 1 is characterized in that: the CPU of MPC8247ZQCMIBA is adopted in described little processing.
5. merge cells as claimed in claim 1 is characterized in that: described programmable gate array chip adopts the FPGA of XC3S500E-4PQ208I.
6. merge cells as claimed in claim 1 is characterized in that: described storer adopts the SDRAM of S42S32400B-6TI.
7. merge cells as claimed in claim 1 is characterized in that: described flash memory adopts the FLASH of S29GL128N90TAI.
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| CN103152136A (en) * | 2013-03-11 | 2013-06-12 | 南京因泰莱电器股份有限公司 | Method for receiving multipath IEC61850-9-2 sampling value in real time by using programmable logic device |
| CN103888331A (en) * | 2014-02-24 | 2014-06-25 | 北京科东电力控制系统有限责任公司 | General high speed bus device for distribution terminal and data interaction method |
| CN104391820A (en) * | 2014-11-25 | 2015-03-04 | 清华大学 | Universal floating point matrix processor hardware structure based on FPGA (field programmable gate array) |
| WO2015042956A1 (en) * | 2013-09-30 | 2015-04-02 | Siemens Aktiengesellschaft | A merging unit |
| CN106483892A (en) * | 2015-08-26 | 2017-03-08 | 力博特公司 | A kind of control system and power electronic equipment |
| CN106896282A (en) * | 2017-01-06 | 2017-06-27 | 许继集团有限公司 | A kind of data sampling method and the combining unit for data sampling |
| CN107526614A (en) * | 2017-08-30 | 2017-12-29 | 苏州思得普信息科技有限公司 | FPGA development boards and its communication means |
| CN108345243A (en) * | 2018-01-18 | 2018-07-31 | 国网浙江省电力有限公司电力科学研究院 | The digitized measurement tests FT3 to IEC61850-9-2 protocol conversion apparatus |
| CN108664444A (en) * | 2017-03-31 | 2018-10-16 | 北京大学 | Restructural wireless mac layer structure based on microprocessor on FPGA |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103152136B (en) * | 2013-03-11 | 2016-03-30 | 南京因泰莱电器股份有限公司 | A kind of method using programmable logic device real-time reception multichannel IEC61850-9-2 sampled value |
| CN103152136A (en) * | 2013-03-11 | 2013-06-12 | 南京因泰莱电器股份有限公司 | Method for receiving multipath IEC61850-9-2 sampling value in real time by using programmable logic device |
| WO2015042956A1 (en) * | 2013-09-30 | 2015-04-02 | Siemens Aktiengesellschaft | A merging unit |
| CN105453480A (en) * | 2013-09-30 | 2016-03-30 | 西门子公司 | A merging unit |
| CN103888331A (en) * | 2014-02-24 | 2014-06-25 | 北京科东电力控制系统有限责任公司 | General high speed bus device for distribution terminal and data interaction method |
| CN104391820B (en) * | 2014-11-25 | 2017-06-23 | 清华大学 | General floating-point matrix processor hardware structure based on FPGA |
| CN104391820A (en) * | 2014-11-25 | 2015-03-04 | 清华大学 | Universal floating point matrix processor hardware structure based on FPGA (field programmable gate array) |
| CN106483892A (en) * | 2015-08-26 | 2017-03-08 | 力博特公司 | A kind of control system and power electronic equipment |
| CN106896282A (en) * | 2017-01-06 | 2017-06-27 | 许继集团有限公司 | A kind of data sampling method and the combining unit for data sampling |
| CN106896282B (en) * | 2017-01-06 | 2019-05-14 | 许继集团有限公司 | A kind of data sampling method and the combining unit for data sampling |
| CN108664444A (en) * | 2017-03-31 | 2018-10-16 | 北京大学 | Restructural wireless mac layer structure based on microprocessor on FPGA |
| CN108664444B (en) * | 2017-03-31 | 2021-08-24 | 北京大学 | Reconfigurable wireless MAC layer structure based on FPGA microprocessor |
| CN107526614A (en) * | 2017-08-30 | 2017-12-29 | 苏州思得普信息科技有限公司 | FPGA development boards and its communication means |
| CN107526614B (en) * | 2017-08-30 | 2020-07-03 | 苏州思得普信息科技有限公司 | Communication method of FPGA development board |
| CN108345243A (en) * | 2018-01-18 | 2018-07-31 | 国网浙江省电力有限公司电力科学研究院 | The digitized measurement tests FT3 to IEC61850-9-2 protocol conversion apparatus |
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Effective date of registration: 20160705 Address after: 710075 Shaanxi city of Xi'an Province Tang Hing Road No. 7 Patentee after: China XD Electronic Corporation Patentee after: Xi'an XD High Voltage Apparatus Co., Ltd. Address before: 710075 Shaanxi city of Xi'an Province Tang Hing Road No. 7 Patentee before: China XD Electronic Corporation |
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Application publication date: 20110406 Assignee: Xi'an XD High Voltage Apparatus Co., Ltd. Assignor: China Xidian electric Limited by Share Ltd |Xi'an Xidian switchgear Co., Ltd. Contract record no.: 2016610000038 Denomination of invention: Merging unit based on field programmable gate array and microprocessor Granted publication date: 20130828 License type: Exclusive License Record date: 20160812 |
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