CN107526614A - FPGA development boards and its communication means - Google Patents
FPGA development boards and its communication means Download PDFInfo
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- CN107526614A CN107526614A CN201710765787.4A CN201710765787A CN107526614A CN 107526614 A CN107526614 A CN 107526614A CN 201710765787 A CN201710765787 A CN 201710765787A CN 107526614 A CN107526614 A CN 107526614A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
Abstract
The present invention relates to a kind of FPGA development boards, including：Micro USB interfaces, power module, fpga core chip and peripheral module, in addition to：The download debugging module being connected with the fpga core chip；The download debugging module includes：Communication module, master controller and peripheral circuit；The master controller connects the communication module and peripheral circuit respectively；The communication module has USB2.0 interfaces.Above-mentioned FPGA development boards, the learning difficulty of user is reduced, lift the learning efficiency of user, reduce the volume of FPGA development boards, improve Consumer's Experience and ease for use.Further relate to a kind of communication means of FPGA development boards.
Description
Technical field
The present invention relates to FPGA, more particularly to FPGA development boards and its communication means.
Background technology
Programmable logic technology：FPGA (Field-Programmable Gate Array, field programmable gate battle array
Row), it is the product further developed on the basis of Digital Logic field is by technologies such as PAL, GAL, CPLD, with ASIC
(Application-specific integrated circuit, application specific integrated circuit) complements each other, and overcomes ASIC conducts
The problem of custom circuit underaction, also solve deficiency of the devices such as GAL, CPLD on logical resource, meanwhile, it is prior
A bit, FPGA is the important tool in chip checking flow.Just because of this, FPGA is since the country is entered, just by height weight
Depending on country is also to rise year by year for the dynamics of the sector investment.FPGA manufacturers expand FPGA market part to exploit market
Volume, also the numerous and confused cooperation increased with colleges and universities and associated companies, carries out technical training and researches and develops development board, is promoting its product
User is also allowed to grasp FPGA technology simultaneously.
FPGA logic loads programming data to realize by internally static storage cell, is stored in memory list
Value in member determine logic unit logic function and each module between or the connecting mode between module and I/O, and finally
The function achieved by FPGA is determined, FPGA allows unlimited number of programming.
FPGA is used in the eda tool that hardware description language or schematic design entry provide to each manufacturer, passes through EDA
Programming data file is generated after the operation such as comprehensive simulating placement-and-routing of software, the programming write data into by downloader in piece
In RAM, then configuration enters mode of operation.
FPGA is to set its working condition by the program being stored in ram in slice, therefore, is needed in piece during work
RAM be programmed.During power-up, the data in non-volatile memory block are read in piece and programmed in RAM by fpga chip, are configured
Cheng Hou, FPGA enter working condition.After power down, FPGA reverts to white tiles, and internal logic relation disappears, and therefore, FPGA can be anti-
It is multiple to use.
When FPGA is programmed, configuration data can be directly downloaded in ram in slice, or outside non-volatile memory block
In, such as Flash.The data power down downloaded in internal RAM can lose, and upper electricity needs to re-download again.Download in Flash
Data power down will not lose, be configured to when electric on next time in FPGA.
Download and debugging technique (a variety of wireless downloading modes)：Current FPGA development boards use downloader and development board more
The mode of separation, reserve on development board and download debugging interface, download debugger be used as among bridge, pass through USB data line and row
Line connects computer and development board respectively.
FPGA the manufacturers Xilinx, Altera and Lattice of three main flows have respective download debugger：Xilinx
Platform USB Cable, Altera USB-Blaster and Lattice USB ispDownload Cable.This three
It is substantially similar to download debugging plan, is all by the way of respective download debugger coordinates PC end FPGA exploitation softwares.FPGA
After being understood after developing Software Create FPGA configuration file, during download to configuration file, configuration data and placement algorithm are sent out
Give download debugger, download debugger and be connected by USB with computer, in the case where USB device driver coordinates, after reception data according to
JTAG protocol translation interface, the non-volatile memory block matched somebody with somebody is downloaded to outside FPGA in a manner of JTAG or is directly downloaded in RAM.
The scheme that debugger internal hardware structure adds piece of CPLD using usb protocol modular converter more is downloaded, usb protocol modular converter makes
With special USB chips, communication, the transmission of data of downloader and PC ends software are realized, CPLD completes the conversion of data-interface
With the configuration of sequential.
Following technical problem be present in conventional art：
Because current download debugger hardware volume is larger, it is used separately with development board, is needed to use when using every time
USB connecting lines connect computer and development board with winding displacement, inconvenient for use.
Download debugger to communicate using USB interface, USB module must coordinate the FPGA of FPGA all big enterprises to develop software and make
With, it is necessary to the driver of manufacturer is installed, because the compatibility of operating system is different, often occurs and drives incompatible feelings
Condition, download debugger is caused not use.
FPGA softwares can verify to id information of fpga chip etc. during download, then to file decoding, under
Carry, verification, the tediously long complexity of whole process, cause speed of download slack-off, Consumer's Experience is poor.Download general inside debugger use
Expensive special USB conversion chips, further need exist for piece of CPLD chip, cause whole downloader hardware cost very high.
The content of the invention
Based on this, it is necessary to for above-mentioned technical problem, there is provided a kind of FPGA development boards, the learning difficulty of user is reduced,
The learning efficiency of user is lifted, reduces the volume of FPGA development boards, improves Consumer's Experience and ease for use.
A kind of FPGA development boards, including：MicroUSB interfaces, power module, fpga core chip and peripheral module, are also wrapped
Include：The download debugging module being connected with the fpga core chip；The download debugging module includes：Communication module, main control
Device and peripheral circuit；The master controller connects the communication module and peripheral circuit respectively；The communication module has
USB2.0 interfaces.
Above-mentioned FPGA development boards, the learning difficulty of user is reduced, lift the learning efficiency of user, reduce FPGA development boards
Volume, improve Consumer's Experience and ease for use.
In other one embodiment, the fpga core chip is Lattice MXO2 or MXO3 family chips.
In other one embodiment, the master controller uses STM32F0 microcontrollers.
In other one embodiment, the peripheral module is dialled including 36 expansible GPIO, 4 touch keys, 4
Code switch, 2 tri coloured lanterns, 8 LED and 27 segment numeral pipes；36 expansible GPIO, 4 touch keys, 4 dial-ups
Switch, 2 tri coloured lanterns, fpga core chip connection described in 8 LED and 27 segment numeral Guan Junyu.
In other one embodiment, the download debugging module has IAP functions.
A kind of communication means of FPGA development boards, using above-mentioned FPGA development boards, including：
The microcontroller is being connected computer, microcontroller electrification reset, USB initial configurations by USB data line
Afterwards, under the interruption control of main frame, a mass-memory unit itself will be enumerated into, in the form of moveable magnetic disc, is shown
Show in the explorer of computer；
After microcontroller establishes the enumeration process that mass-memory unit is completed in connection with PC main frames, that is, pass through bulk transfer
End points realizes the file system management to moveable magnetic disc；
PC main frames according to the configures descriptor information returned in enumeration process, calculating logic block size and data packet length,
Then FAT file system data are write into corresponding logical address, the SCSI lives that microcontroller needs to coordinate main frame as slave
The formatting of moveable magnetic disc is completed in order；
After operating system is completed to the file system management of moveable magnetic disc, drive and magnetic can be shown in file manager
Disk attribute, after the FPGA configuration files of JED forms deposit moveable magnetic disc, main frame is by bulk transfer end points by file data
Using logical block size as bag, the USB controller buffering area of microcontroller is transmitted packets to, microcontroller is sentenced after receiving data
Whether the disconnected logical block address sent is data address, and after being defined as data address, data are temporarily stored in RAM by FPGA
Flash programmings module passes through in Flash inside JTAG sequential programming to FPGA.
Brief description of the drawings
Fig. 1 is a kind of topology layout figure for FPGA development boards that the embodiment of the present application provides.
Fig. 2 is the topology layout figure that debugging module is downloaded in a kind of FPGA development boards that the embodiment of the present application provides.
Fig. 3 is the topology layout figure that peripheral module is downloaded in a kind of FPGA development boards that the embodiment of the present application provides.
Fig. 4 is a kind of one of flow chart of communication means of FPGA development boards that the embodiment of the present application provides.
Fig. 5 is the two of the flow chart of the communication means for a kind of FPGA development boards that the embodiment of the present application provides.
Fig. 6 is the three of the flow chart of the communication means for a kind of FPGA development boards that the embodiment of the present application provides.
Fig. 7 is the four of the flow chart of the communication means for a kind of FPGA development boards that the embodiment of the present application provides.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Refering to Fig. 1, a kind of FPGA development boards, including：Micro USB interfaces, power module, fpga core chip, peripheral hardware
Module and the download debugging module being connected with the fpga core chip.
This development board uses power supply interface and USB communication interface of the Micro USB interfaces as whole board.USB power source
Power module is inputed to, by low pressure difference linearity voltage stabilizing output+3.3V voltage, all module for power supply to board.
In other one embodiment, fpga core chip uses the MXO2/MXO3 family chips of Lattice companies,
The family chip main feature is as follows：
(1) electric instantaneous starting on, without waiting for the power on configuration time；
(2) 256Kbit user's flash memory and the embedded block RAMs of 240Kbit are up to；
(3) can be programmed by JTAG, I2C, SPI various ways；
(4) TransFR functions (field upgrade function) support Site Design upgrading, without interrupting equipment operation.
Chip takes JTAG configuration modes, and MCU is connected with MXO2/MXO3 fpga chips, and it is carried out using jtag interface
Configuration, and in the MCU other end, communicated by Micro USB interfaces with upper PC ends, realize to download and debug.
In other one embodiment, the master controller uses STM32F0 microcontrollers.
In other one embodiment, the download debugging module has IAP functions.(in Application
Programming, in-service units)
Master controller use with USB controller STM32F0 microcontrollers (abbreviation MCU), by USB2.0 interfaces with
Computer realizes usb communication, receives FPGA configuration file, configuration file is decoded, extracts useful configuration data, simultaneously
Configuration data is written in the non-volatile memory block Flash matched somebody with somebody outside FPGA by simulation jtag interface with JTAG sequential.In addition, control
Device processed can also upgrade itself program i.e. IAP functions in addition to downloading FPGA configuration file, according to setting for peripheral circuit
Put to determine that the mode of operation of controller is download configuration file pattern or IAP patterns.
Refering to Fig. 3, in other one embodiment, the peripheral module include 36 expansible GPIO, 4 touch by
5,4, key, 2,8 LED3 and 27 segment numeral pipes 1 of tri coloured lantern of toggle switch 4,2；36 expansible GPIO, 4 touch
Button, 4 toggle switch, 5,2 tri coloured lanterns, fpga core chip connection described in 8 LED and 27 segment numeral Guan Junyu.So
If, it is easy to user to carry out code debugging.
User can complete many FPGA and EDA experiment according to these peripheral hardwares, allow it quickly to grasp this gate technique.
Refering to Fig. 2, the download debugging module includes：Communication module, master controller and peripheral circuit；The master controller
The communication module and peripheral circuit are connected respectively；The communication module has USB2.0 interfaces.
It is the bridge for connecting PC end FPGA exploitation softwares and fpga chip to download debugging module, and main completion receives FPGA and matched somebody with somebody
Put file, to file decoding and change the work such as JTAG sequential, download configuration data to FPGA.
Above-mentioned FPGA development boards, the learning difficulty of user is reduced, lift the learning efficiency of user, reduce FPGA development boards
Volume, improve Consumer's Experience and ease for use.
A kind of communication means of FPGA development boards, using above-mentioned FPGA development boards, including：
Microcontroller with USB module by USB data line when connecting computer, microcontroller electrification reset, at the beginning of USB
After beginningization configuration, under the interruption control of main frame, a mass-memory unit itself will be enumerated into, with moveable magnetic disc
Form, it is shown in the explorer of computer, its enumeration process is following (referring to Fig. 4).
After the enumeration process that mass-memory unit is completed in connection is established refering to Fig. 5, MCU and PC main frame, that is, pass through batch
Transport endpoint realizes the file system management to moveable magnetic disc.PC main frames are believed according to the configures descriptor returned in enumeration process
Breath, calculating logic block size and data packet length, FAT file system data are then write into corresponding logical address, MCU conducts
Slave needs the formatting for coordinating the scsi command of main frame to complete moveable magnetic disc.
Refering to Fig. 6, after operating system is completed to the file system management of moveable magnetic disc, can be shown in file manager
Drive and Disk Properties, after the FPGA configuration file deposit moveable magnetic disc of JED forms, main frame will by bulk transfer end points
File data transmits packets to MCU USB controller buffering area using logical block size as bag, and MCU judges after receiving data
Whether the logical block address of transmission is data address, after being defined as data address, be not by data deposit MCU inside Flash and
It is to be temporarily stored in RAM to be passed through in Flash inside JTAG sequential programming to FPGA by FPGA Flash programmings modules.
Just need the GPIO for being configured to JTAG communications, in this functional module, need refering to Fig. 7, during MCU power-up initializings
The file data of reception is decoded, it is first determined whether being legal FPGA configuration file, then decoded effective
Configuration data.The ID number that JTAG mouths read FPGA is first passed through during programming, after determining that ID is correct, enables Flash program configuration feature,
Erasing needs the Flash page of programming, then using 16 bytes as a line, starts programming to the program configuration Flash inside FPGA.
Simultaneously verification data is read after the completion of programming, after verification is correct, Flash program configuration feature is closed, completes programming.
Concrete operating principle brief introduction：
In Lattice Diamond softwares, a FPGA engineering, compilation and synthesis generation configuration FPGA JEDEC are established
File.
After development board is connected into computer by Micro USB data lines, form is clicked on if prompting is formatted diskette
Change disk, format parameter is capacity 1M, and file system is FAT (acquiescence), and allocation unit size is 2048 bytes, and click starts
Format, the moveable magnetic disc of a 1M size can be generated after formatting, the JED files generated before are copied into the magnetic
In disk.After the download debugging module of development board receives and decodes this document, the programming of JTAG sequential is converted into FPGA Flash
In.FPGA reads configuration data from Flash, operation logic circuit, realizes the driving of FPGA board peripheral hardwares.
The usb communication method that the present invention designs employs USB mass-memory unit patterns, because operating system has to big
The driving of capacity storage device is supported, so being driven without user installation, this design solves driving cumbersome during usb communication
Problem, while can also have higher message transmission rate.
The more convenient method for down loading with high speed, by the mass-memory unit using STM32 microcontroller implementations
Carry out storage and operate the configuration realized to FPGA, both reduced BOM areas, and reduced user cost again.
JED files are decoded using MCU, and FPGA is configured, accelerate flash erasing, programming, verification
Process, significantly reduce setup time.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope that this specification is recorded all is considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more specific and detailed, but simultaneously
Can not therefore it be construed as limiting the scope of the patent.It should be pointed out that come for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (6)
1. a kind of FPGA development boards, including：Micro USB interfaces, power module, fpga core chip and peripheral module, it is special
Sign is, in addition to：The download debugging module being connected with the fpga core chip；
The download debugging module includes：Communication module, master controller and peripheral circuit；The master controller connects described respectively
Communication module and peripheral circuit；The communication module has USB2.0 interfaces.
2. FPGA development boards according to claim 1, it is characterised in that the fpga core chip is Lattice MXO2
Or MXO3 family chips.
3. FPGA development boards according to claim 1, it is characterised in that the master controller uses STM32F0 microcontrollers
Device.
4. FPGA development boards according to claim 1, it is characterised in that the peripheral module is expansible including 36
GPIO, 4 touch keys, 4 toggle switch, 2 tri coloured lanterns, 8 LED and 27 segment numeral pipes；Described 36 expansible
GPIO, 4 touch keys, 4 toggle switch, 2 tri coloured lanterns, fpga core core described in 8 LED and 27 segment numeral Guan Junyu
Piece connects.
5. FPGA development boards according to claim 1, it is characterised in that the download debugging module has IAP functions.
6. a kind of communication means of FPGA development boards, it is characterised in that opened using any described FPGA of claim 1 to 5
Plate is sent out, including：
The microcontroller is being connected computer by USB data line, microcontroller electrification reset, after USB initial configurations,
Under the interruption control of main frame, a mass-memory unit itself will be enumerated into, in the form of moveable magnetic disc, is shown in electricity
In the explorer of brain；
After microcontroller establishes the enumeration process that mass-memory unit is completed in connection with PC main frames, that is, pass through bulk transfer end points
Realize the file system management to moveable magnetic disc；
PC main frames are according to the configures descriptor information returned in enumeration process, calculating logic block size and data packet length, then
FAT file system data are write into corresponding logical address, microcontroller needs to coordinate the scsi command of main frame complete as slave
Into the formatting of moveable magnetic disc；
After operating system is completed to the file system management of moveable magnetic disc, drive and disk category can be shown in file manager
Property, after the FPGA configuration files of JED forms deposit moveable magnetic disc, main frame is by bulk transfer end points by file data to patrol
Block size is collected as bag, transmits packets to the USB controller buffering area of microcontroller, microcontroller judges hair after receiving data
Whether the logical block address sent is data address, after being defined as data address, data is temporarily stored in RAM and burnt by FPGA Flash
Writing module passes through in Flash inside JTAG sequential programming to FPGA.
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