CN101996928A - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- CN101996928A CN101996928A CN2009100565256A CN200910056525A CN101996928A CN 101996928 A CN101996928 A CN 101996928A CN 2009100565256 A CN2009100565256 A CN 2009100565256A CN 200910056525 A CN200910056525 A CN 200910056525A CN 101996928 A CN101996928 A CN 101996928A
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Abstract
A method for forming a semiconductor device comprises the following steps: providing a substrate; forming a dielectric layer on the surface of the substrate; forming a via exposing the substrate on the dielectric layer; forming a metal layer filling the via on the surface of the dielectric layer; carrying out heat treatment on the metal layer; and forming a covering layer on the surface of the metal layer after heat treatment. The invention can avoid bulge and defects on the surface of the metal layer and improve the performance of the device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of formation method of semiconductor device.
Background technology
Along with the making of integrated circuit develops to very lagre scale integrated circuit (VLSIC), the current densities of IC interior is increasing, and the number of elements that is comprised is also more and more, and this development makes crystal column surface can't provide enough areas to make required interconnection line.
For the interconnection line demand after satisfying element and dwindling, the very large scale integration technology institute a kind of method of employing usually that is designed to of two-layer and two-layer above multiple layer metal interconnection line.At present, the conducting of different metal layer or metal level and laying, be by between metal level and the metal level or the dielectric layer between metal level and the laying form an opening, in opening, insert electric conducting material, form that the contact hole structure realizes.In being 200610030809.4 Chinese patent file, application number can find more formation scheme about existing contact hole.
Simply introduce the forming process of contact hole structure below in conjunction with accompanying drawing.Fig. 1 to Fig. 4 is the schematic diagram of contact hole fill method in the prior art.
As shown in Figure 1, provide substrate 10,
As shown in Figure 2, the certain thickness interlayer dielectric layer 11 of deposition on Semiconductor substrate 10, and utilize photoetching, lithographic technique to remove the interlayer dielectric layer 11 at corresponding contact hole place until exposing substrate surface, to form groove opening 12.
As shown in Figure 3, utilize physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) method is on groove opening 12 surface deposition barrier layers 13;
As shown in Figure 4, in groove, fill metal level 14.
Along with further developing of the making scale of integrated circuit, the metal layer material of metal level 14 is mainly used Cu, the metal level 14 of described formation has stress, in follow-up technology, can form the multilayer cover layer on metal level 14 surfaces, and have multiple high temp technology in the subsequent step that forms metal level 14, bulge phenomenon and defective phenomenon can appear in described metal level 14 surfaces, cause device performance to descend.
Summary of the invention
The problem that the present invention solves is to avoid layer on surface of metal bulge phenomenon and defective phenomenon to occur.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, comprising: substrate is provided; Form dielectric layer at described substrate surface; Form the through hole that exposes substrate at described dielectric layer; Form the metal level of filling described through hole on described dielectric layer surface; Described metal level is heat-treated; Layer on surface of metal after heat treatment forms cover layer.
Compared with prior art, the present invention is after forming metal level, described metal level is heat-treated, and described heat treatment temperature is 380 degrees centigrade to 420 degrees centigrade, and the present invention can make the atom of metal level carry out rearranging of lattice, reduce the defects count of metal level, make metal level move back stress, avoid metal level bulge phenomenon and defective phenomenon to occur, cause device performance to descend, suitable temperature range has been selected in heat treatment of the present invention, can not influence device performance.
Description of drawings
Fig. 1 to Fig. 4 is the forming process schematic diagram of existing contact hole structure;
Fig. 5 is the schematic flow sheet of the formation method of semiconductor device of the present invention;
Fig. 6 to Figure 12 is the forming process schematic diagram of the formation method of semiconductor device of the present invention.
Embodiment
The present inventor is through a large amount of experiments; metal level and described semiconductor substrate materials that discovery is formed on the Semiconductor substrate do not match; the metal level that forms by prior art has the tensile stress existence usually; and further developing along with semiconductor technology; described layer on surface of metal also can form plural layers usually; make the stress of described metal level further enlarge; and after forming metal level, also have a high-temperature technology of multistep; described metal level and Semiconductor substrate and the follow-up film thermal coefficient of expansion that is formed on layer on surface of metal are all inequality; in the high-temperature technology of multistep; can bulge phenomenon and defective phenomenon occur at layer on surface of metal, cause device performance to descend.
For this reason, the invention provides a kind of formation method of semiconductor device, Fig. 5 is the schematic flow sheet of the formation method of semiconductor device of the present invention, specifically comprises the steps:
Step S101 provides substrate;
Step S102 forms dielectric layer at described substrate surface;
Step S103 forms the through hole that exposes substrate at described dielectric layer;
Step S104 forms the metal level of filling described through hole on described dielectric layer surface;
Step S105 heat-treats described metal level;
Step S106, the layer on surface of metal after heat treatment forms cover layer.
Below in conjunction with accompanying drawing, the formation method of semiconductor structure of the present invention is elaborated.
With reference to figure 6, provide substrate 200.
Described substrate 200 can be substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes or the substrate that is not patterned.
With reference to figure 7, form dielectric layer 300 on described substrate 200 surfaces.
The thickness of described dielectric layer 300 is 20 nanometer to 5000 nanometers, described dielectric layer 300 is used for lead on the substrate and the isolation between the lead, concrete described dielectric layer 300 can be before-metal medium layer (Pre-Metal Dielectric, PMD), also can be interlayer dielectric layer (Inter-Metal Dielectric, ILD).
Before-metal medium layer is to be deposited on the substrate with MOS device, utilize depositing operation to form, can form groove at subsequent technique in before-metal medium layer, form connecting hole with metal filled groove, described connecting hole is used for connecting the electrode of MOS device and the plain conductor of upper layer interconnects layer.
Interlayer dielectric layer is the dielectric layer of postchannel process between metal interconnecting layer, can form groove in the interlayer dielectric layer in subsequent technique, forms connecting hole with metal filled groove, and described connecting hole is used for connecting the lead of adjacent metal interconnects layer.
The material of described dielectric layer 300 is selected from SiO usually
2The perhaps SiO of Can Zaing
2USG (Undoped Silicon Glass for example, the silex glass that does not have doping), BPSG (BorophosphosilicateGlass, the silex glass of boron phosphorus doped), BSG (Borosilicate Glass, the silex glass of doped with boron), PSG (Phosphosilitcate Glass, the silex glass of Doping Phosphorus) etc.
Described dielectric layer 300 generally selects for use the dielectric material of low-k, the material of described dielectric layer 300 specifically to be selected from the carborundum (BLOK) that silica (Black Diamond) that fluorine silex glass (FSG), carbon mix and nitrogen mix at 130 nanometers and following process node.
The formation technology of described dielectric layer 300 can be any conventional vacuum coating technology, for example atomic deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like are not here done and are given unnecessary details.
With reference to figure 8, form photoresist figure 310 on described dielectric layer 300 surfaces.
Described photoresist figure 310 is used for corresponding with the through hole of follow-up formation, and as the mask of etching through hole.
At described dielectric layer 300 surperficial spin coating photoresists, then by exposure with on the mask with the corresponding figure transfer of through hole to photoresist, utilize developer solution that the photoresist of corresponding site is removed then, to form photoresist figure 310.
What need particularly point out is; in other embodiments; before described dielectric layer 300 surfaces form photoresist figure 310 steps; usually also can form bottom anti-reflection layer (Bottom Anti-Reflective Coating on described dielectric layer 300 surfaces; BARC); the effect of described bottom anti-reflection layer is mainly: prevent that light from passing through to reflect at the wafer interface behind the photoresist, the light of avoiding reflecting can interfere with incident light, makes that photoresist can uniform exposure.
With reference to figure 9, be mask with described photoresist figure 310, etching dielectric layer 300 forms through hole 301.
Described etching technics can be any conventional lithographic technique, for example chemical etching or plasma etching technology.In the present embodiment, the using plasma lithographic technique adopts CF
4, CHF
3, CH
2F
2, CH
3F, C
4F
8Perhaps C
5F
8In one or several as reacting gas etching dielectric layer 300.
Concrete etching technics parameter can for: select the plasma-type etching apparatus for use, the etching apparatus chamber pressure is 10 millitorr to 50 millitorrs, and the top radio-frequency power is 200 watts to 500 watts, and the bottom radio-frequency power is 150 watts to 300 watts, C
4F
8Flow is that per minute 10 standard cubic centimeters (10SCCM) are to per minute 50 standard cubic centimeters, the CO flow is that per minute 100 standard cubic centimeters are to per minute 200 standard cubic centimeters, the Ar flow is that per minute 300 standard cubic centimeters are to per minute 600 standard cubic centimeters, O
2Flow be per minute 10 standard cubic centimeters to per minute 50 standard cubic centimeters, etching dielectric layer 300 is until the through hole 301 that form to expose substrate 200.
With reference to Figure 10, remove photoresist figure 310.
Remove the photoresist graphics art and can remove technology, comprise that photoresist is removed solution removal, plasma bombardment is removed or the like for known photoresist.
In the present embodiment, adopt plasma bombardment to remove technology and remove photoresist figure 310, described plasma bombardment is removed the concrete parameter of technology and comprised: the etching apparatus chamber pressure is 50 millitorr to 100 millitorrs, and radio-frequency power is 300 watts to 500 watts, O
2Flow is that per minute 50 standard cubic centimeters are to per minute 250 standard cubic centimeters, N
2Flow be per minute 20 standard cubic centimeters to per minute 40 standard cubic centimeters, the CO flow be per minute 50 standard cubic centimeters to per minute 90 standard cubic centimeters, remove photoresist figure 310 with above-mentioned etching condition.
With reference to Figure 11, form the metal level 400 of filling described through hole 301 on described dielectric layer 300 surfaces.
Described metal level 400 materials are selected from aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps are selected from the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, and described metal level 400 thickness are 2000 dust to 3000 dusts.
Described metal level 400 is the interlayer electrode, is used to realize the conducting of each unit in the device.
In the present embodiment; because metallic copper has the ability of high-melting-point, low-resistance coefficient and high anti-electron transfer; preferably do exemplary illustrated with copper; but of particular note; the metal level 400 of selecting for use other conductive materials to form is higher than in 130 nanometer technologies at process node still can work; just transmission delay is bigger, specially illustrates at this, should too not limit protection scope of the present invention.
The formation technology of described metal level 400 can be selected known physical gas-phase deposition or electroplating technology for use, what need particularly point out is, the material difference that the formation technology of above-mentioned metal level 400 needs to select for use according to metal level 400 adopts different technology, adjusts different technological parameters.
In the present embodiment; select the material of metallic copper for use as metal level 400; usually also can form barrier layer (not shown) on the sidewall and the surface of through hole 301; described barrier material is selected from tantalum, tantalum nitride, titanium or titanium nitride; described barrier layer can be single layer structure or multilayer overlaying structure, and described barrier layer is used to stop the material of metal level 400 to spread in dielectric layer 300.
The technology on described formation barrier layer can be known depositing operation, for example physical gas-phase deposition or chemical vapor deposition method.
After carrying out formation barrier layer step, form the metal levels 400 of filling described through hole 301 on described dielectric layer 300 surfaces.
Existing technology can directly form the multilayer cover layer on metal level 400 after forming metal level 400 technologies.The present inventor finds; the metal level 400 that adopts existing technology to form has a large amount of defectives usually; the existence of described defective makes metal level 400 have stress; the metal level 400 that has stress is along with the cover layer of subsequent technique in metal level 400 surface formation multilayers; make the stress of described metal level 400 further enlarge; and after forming metal level; the follow-up high-temperature technology that also has multistep; described metal level 400 and Semiconductor substrate and the follow-up film thermal coefficient of expansion that is formed on layer on surface of metal are all inequality; in the high-temperature technology of multistep; the mutual fusion growth of a large amount of defectives at metal level 400; bulge phenomenon and defective phenomenon occur at layer on surface of metal, cause device performance to descend.
For this reason, the present invention proposes a kind of improved technology, after described dielectric layer 300 surfaces form the metal level 400 of filling described through hole 301, described metal level 400 is heat-treated, described Technology for Heating Processing can provide heat energy to described metal level 400, make the atom of metal level 400 can carry out rearranging of lattice, reduce the defects count of metal level 400, and can make metal level 400 move back stress.
Described heat treatment can be carried out in quick anneal oven or tubular type annealing furnace, the present inventor is through a large amount of experiments, having obtained preferable heat treatment temperature is 380 degrees centigrade to 420 degrees centigrade, this temperature range can effectively make the atom of metal level 400 carry out rearranging of lattice, reduce the defects count of metal level 400, make metal level 400 move back stress, it needs to be noted, form the just step of one of them in a large amount of processing step of semiconductor of metal level 400, before forming metal level 400, can be formed with other metal levels, 380 degrees centigrade to 420 degrees centigrade heat treatment temperatures can be avoided bringing extra stress to the metal level before forming metal level, make component failure.
The concrete parameter of described Technology for Heating Processing is: heat treatment temperature is 380 degrees centigrade to 420 degrees centigrade, and protective gas is N
2Perhaps Ar, shield gas flow rate be per minute 20 standard cubic centimeters to per minute 500 standard cubic centimeters, heat treatment time is 15 seconds to 25 seconds.
In described heat treatment, protective gas can make metal level 400 isolate oxygen, avoids the burning in the metal level.
With reference to Figure 12, metal level 400 surfaces after heat treatment form cover layer 500.
Described cover layer 500 can be single coat structure or sandwich construction.
Described cover layer 500 generally selects for use the dielectric material of low-k, the material of described cover layer 500 specifically to be selected from the carborundum that silica that fluorine silex glass, carbon mix and nitrogen mix at 130 nanometers and following process node.
What need particularly point out is that for fear of increasing stress for described metal level 400, the temperature of the formation technology of described cover layer 500 is lower than 420 degrees centigrade.
In the present embodiment, described cover layer 500 materials are selected from the carborundum that nitrogen mixes, the formation technology of described cover layer 500 can be the medium chemical vapor deposition method, in the medium chemical vapor depsotition equipment, carry out, reaction temperature is 300 degrees centigrade to 400 degrees centigrade, chamber pressure is that 5 holders are to 6 holders, interresponse time is 7 millimeters to 9 millimeters, power is 222 watts to 333 watts, the tetraethoxysilane flow is that per minute 200 standard cubic centimeters are to per minute 350 standard cubic centimeters, ammonia flow be per minute 650 standard cubic centimeters to per minute 750 standard cubic centimeters, helium gas flow is that per minute 1100 standard cubic centimeters are to per minute 1300 standard cubic centimeters, CH
4Flow is that per minute 550 standard cubic centimeters are to per minute 650 standard cubic centimeters.
The present invention is after forming metal level 400, described metal level 400 is heat-treated, described heat treatment temperature is 380 degrees centigrade to 420 degrees centigrade, the present invention can make the atom of metal level 400 carry out rearranging of lattice, reduces the defects count of metal level 400, makes metal level 400 move back stress, avoid metal level 400 bulge phenomenon and defective phenomenon to occur, cause device performance to descend, suitable temperature range has been selected in heat treatment of the present invention, can not influence device performance.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. the formation method of a semiconductor device is characterized in that, comprising:
Substrate is provided;
Form dielectric layer at described substrate surface;
Form the through hole that exposes substrate at described dielectric layer;
Form the metal level of filling described through hole on described dielectric layer surface;
Described metal level is heat-treated;
Layer on surface of metal after heat treatment forms cover layer.
2. the formation method of semiconductor device as claimed in claim 1 is characterized in that, described metal layer thickness is 2000 dust to 3000 dusts.
3. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, described metal layer material is selected from aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps is selected from the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.
4. the formation method of semiconductor device as claimed in claim 1 is characterized in that, described heat treated temperature is 380 degrees centigrade to 420 degrees centigrade.
5. the formation method of semiconductor device as claimed in claim 1 is characterized in that, the concrete parameter of described heat treatment is: heat treatment temperature is 380 degrees centigrade to 420 degrees centigrade, and protective gas is N
2Perhaps Ar, shield gas flow rate be per minute 20 standard cubic centimeters to per minute 500 standard cubic centimeters, heat treatment time is 15 seconds to 25 seconds.
6. the formation method of semiconductor device as claimed in claim 1 is characterized in that, described cover layer is single coat structure or sandwich construction.
7. the formation method of semiconductor device as claimed in claim 1 is characterized in that, described covering layer material is selected from the silica of fluorine silex glass, carbon doping or the carborundum that nitrogen mixes.
8. the formation method of semiconductor device as claimed in claim 7 is characterized in that, described tectal formation method is the medium chemical vapor deposition method.
9. the formation method of semiconductor device as claimed in claim 1 is characterized in that, described tectal formation technological temperature is lower than 420 degrees centigrade.
10. the formation method of semiconductor device as claimed in claim 9, it is characterized in that, described tectal concrete technological parameter is: reaction temperature is 300 degrees centigrade to 400 degrees centigrade, chamber pressure is that 5 holders are to 6 holders, interresponse time is 7 millimeters to 9 millimeters, power is 222 watts to 333 watts, the tetraethoxysilane flow is that per minute 200 standard cubic centimeters are to per minute 350 standard cubic centimeters, ammonia flow is that per minute 650 standard cubic centimeters are to per minute 750 standard cubic centimeters, helium gas flow is that per minute 1100 standard cubic centimeters are to per minute 1300 standard cubic centimeters, CH
4Flow is that per minute 550 standard cubic centimeters are to per minute 650 standard cubic centimeters.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103871868A (en) * | 2012-12-11 | 2014-06-18 | 北大方正集团有限公司 | Straight hole etching method |
| CN104037120A (en) * | 2013-03-06 | 2014-09-10 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing MIM capacitor |
| CN104174860A (en) * | 2014-08-14 | 2014-12-03 | 华中科技大学 | Preparation method for alloy nano-particles adopting core-shell structures |
| CN105428308A (en) * | 2014-09-16 | 2016-03-23 | 三星电子株式会社 | Methods for Fabricating Semiconductor Devices Using Liner Layers to Avoid Damage to Underlying Patterns |
| CN107004597A (en) * | 2014-12-23 | 2017-08-01 | 英特尔公司 | Decouple via filling |
| CN108470716A (en) * | 2018-05-18 | 2018-08-31 | 上海华虹宏力半导体制造有限公司 | Eliminate the method and semiconductor structure of shorted devices caused by metal defect |
| CN115513135A (en) * | 2022-11-17 | 2022-12-23 | 广州粤芯半导体技术有限公司 | Semiconductor processing method and semiconductor etching equipment |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20060117635A (en) * | 2005-05-13 | 2006-11-17 | 삼성전자주식회사 | Multilayered thin films, thin film transistor including the same, and manufacturing method thereof |
| KR20090038624A (en) * | 2007-10-16 | 2009-04-21 | 주식회사 동부하이텍 | Method for fabricating a barrier metal layer |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871868A (en) * | 2012-12-11 | 2014-06-18 | 北大方正集团有限公司 | Straight hole etching method |
| CN104037120A (en) * | 2013-03-06 | 2014-09-10 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing MIM capacitor |
| CN104174860A (en) * | 2014-08-14 | 2014-12-03 | 华中科技大学 | Preparation method for alloy nano-particles adopting core-shell structures |
| CN104174860B (en) * | 2014-08-14 | 2017-02-15 | 华中科技大学 | Preparation method for alloy nano-particles adopting core-shell structures |
| CN105428308A (en) * | 2014-09-16 | 2016-03-23 | 三星电子株式会社 | Methods for Fabricating Semiconductor Devices Using Liner Layers to Avoid Damage to Underlying Patterns |
| CN105428308B (en) * | 2014-09-16 | 2020-11-17 | 三星电子株式会社 | Method for manufacturing semiconductor device using pad layer |
| CN107004597A (en) * | 2014-12-23 | 2017-08-01 | 英特尔公司 | Decouple via filling |
| CN108470716A (en) * | 2018-05-18 | 2018-08-31 | 上海华虹宏力半导体制造有限公司 | Eliminate the method and semiconductor structure of shorted devices caused by metal defect |
| CN115513135A (en) * | 2022-11-17 | 2022-12-23 | 广州粤芯半导体技术有限公司 | Semiconductor processing method and semiconductor etching equipment |
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